双阈值多米诺或门性能估计及其工艺浮动下的适用性分析

 提出了一种基于小波神经网络,估计双阈值多米诺或门的漏功耗和速度,随着扇入的增加,非线性变化的系统方法.分析表明,此方法估计误差均小于5%,具有很高的准确性和稳定性,产生估计误差的原因为功耗比例变化和电容匹配的影响.最后,利用蒙特卡罗分析验证了此方法在工艺参数浮动下的适用性,并得出结论:在工艺参数的影响下,适用于较小扇入的漏功耗估计和较大扇入的延迟估计.     

亚70nm CMOS工艺低漏电流、高噪声容限的低功耗多输入多米诺或门的设计

提出了两种新的电路技术,在降低多输入多米诺"或门"的动态功耗的同时减小了漏电流,并提高了电路的噪声容限.采用新的电路技术设计了八输入多米诺"或门"并基于45nm BSIM4 SPICE 模型对其进行了模拟.模拟结果表明,设计的两种新多米诺电路在同样的噪声容限下有效地降低了动态功耗,减小了总的漏电流,同时提高了工作速度.与双阈值多米诺电路相比,设计的两种电路动态功耗分别降低了8.8%和11.8%,电路速度分别提高了9.5%和13.7%,同时总的漏电流分别降低了80.8%和82.4%.基于模拟结果,也分析了双阈值多米诺电路中求值点的不同逻辑状态对总的漏电流的影响.     

亚65nm工艺新型p结构多米诺与门设计

利用休眠晶体管、多阈值和SEFG技术(源跟随求值门技术),设计了一种新型的p结构多米诺与门.HSPICE仿真结果表明,在相同的时间延迟下,与标准双阈值多米诺与门、标准低阈值多米诺与门和SEFG结构相比,提出的新型多米诺与门的漏电流分别减小了43%,62%和67%,噪声容限分别增大了3.4%,23.6%和13.7%.从而有效地解决了亚65nm工艺下多米诺与门存在的漏电流过大,易受干扰的问题.分析并得到了不同结构的休眠多米诺与门的漏电流最低的输入矢量和时钟状态.     

一种0.8V低功耗低相位噪声锁相环的设计

本文提出了一种低电压应用的低功耗、低相位噪声锁相环（PLL）。其中压控振荡器（VCO）的工作电压为0.5V,其他模块的工作电压为0.8V。为了适应极低电压下的应用,文中振荡器采用了纯NMOS差分拓扑结构,鉴频鉴相器（PFD）采用改进的预充电结构,而电荷泵（CP）采用新型负反馈结构。预分频电路采用扩展的单相时钟逻辑电路构成,它可以工作在较高的频率下,节省了芯片面积和功耗。此外还采用了去除尾电流源等设计方法来降低相位噪声。采用SMIC 0.13μm RF CMOS工艺,在0.8V电源电压下,测得在整个锁定范围内,最差相位噪声为-112.4dBc/Hz@1MHz,其输出频率范围为3.166~3.383GHz。改进的PFD和新型CP功耗仅为0.39mW,占据的芯片面积仅100μm×100μm。芯片总面积为0.63mm2,在0.8V电源电压下功耗仅为6.54mW 。     

亚70nm CMOS工艺低漏电流、高噪声容限的低功耗多输入多米诺或门的设计

提出了两种新的电路技术,在降低多输入多米诺"或门"的动态功耗的同时减小了漏电流,并提高了电路的噪声容限.采用新的电路技术设计了八输入多米诺"或门"并基于45nm BSIM4 SPICE 模型对其进行了模拟.模拟结果表明,设计的两种新多米诺电路在同样的噪声容限下有效地降低了动态功耗,减小了总的漏电流,同时提高了工作速度.与双阈值多米诺电路相比,设计的两种电路动态功耗分别降低了8.8%和11.8%,电路速度分别提高了9.5%和13.7%,同时总的漏电流分别降低了80.8%和82.4%.基于模拟结果,也分析了双阈值多米诺电路中求值点的不同逻辑状态对总的漏电流的影响.     

CMOS工艺实现的高性能串联耦合正交振荡器

本文提出了一个高性能的正交振荡器。该振荡器采用具有顶层厚金属的SMIC CMOS 0.18um工艺实现。采用cascode串联耦合来产生正交信号。对NMOS差分对管引入源级退化电容来抑制其1/f噪声转化为振荡器的近端相位噪声。并最终采用专用的低噪声,高电源抑制能力的LDO来供电。正交振荡器测试显示4.78GHz信号输出时1MHz频偏处相位噪声－123.3dBc/Hz.频率范围为4.09GHz到4.87GHz,17.5%的调谐范围。调谐增益在44.5MHz/V至66.7MHz/V之间。核心芯片面积不包含pad和ESD保护电路的为0.41mm2。     

与工艺、电源电压和温度无关的低功耗振荡环设计

分析了传统片外时钟和片内时钟各自的特点和应用背景,在Chartered 0.35μm CMOS工艺下实现了一个低功耗PVT(工艺、电源电压、温度无关)振荡环,对片内时钟的稳定性和功耗进行改进。该振荡环无需精准的电压源,采用了误差补偿技术,通过偏置电压和延时单元的相互补偿,使得振荡频率对于工艺、温度和电源电压均有较大的容差能力。并且由于针对延时单元补偿的方式,令周期大小易于调整。蒙特卡罗仿真显示,工艺误差引起的偏差要比补偿前的偏差减小了60%。流片测试结果表明,在工作温度变化范围0~100°C时,振荡环输出的频率偏差为±3.22%;在电源电压变化范围为2.8~3.8 V时,振荡环输出的频率偏差为±3.36%;在电源电压3.3 V的情况下,整个芯片消耗的电流为950μA。     

超低功耗低相位噪声CMOS LC-VCO的设计与实现

设计了一种全集成交叉耦合变压器反馈的LC压控振荡器（LC-VCO）,该VCO即使在电源电压低于阈值电压的情况下实现了低相位噪声和超低功率消耗。该超低功耗的VCO采用SMIC 0.18um 数模混合&RF 1P6M CMOS工艺进行了流片验证。测试结果表明：电路在0.4 V电源供电和工作频率为2.433 GHz时,相位噪声为-125.3 dBc/Hz@1MHz,核心直流功耗仅为640uW。芯片的工作频率为2.28-2.48 GHz,调谐范围为200 MHz (8.7%),电路的优值为-195.7dB。该VCO完全可以满足IEEE 802.11b接收机的应用要求。     

基于TL494和IR2110的断路器操作电源的设计

动作电压试验、机械特性测试是最能反映高压断路器机械性能的测试.为了做好该项测试,可调电压的断路器操作控制电源是关键.文章设计了一种基于TL494和IR2110的断路器操作电源,介绍了TL494和IR2110的基本性能、使用方法.最后给出了控制电路的设计电路图,并对电路进行了分析.     

一种高性能采样/保持电路的设计

设计了一种基于标准0.35 μm CMOS工艺的高性能采样/保持电路.预充电技术和输出电容耦合技术的运用,降低了电路对运算放大器的要求,同时实现了低功耗.在Cadence Spectre环境下进行仿真,当输入信号为48.4375 MHz、2 Vpp的正弦波,采样速率为100 MSPS时,该采样/保持电路的SFDR达72.3 dB,THD为-65.2 dB,分辨率为11位;在3.3 V电源电压下,电路的功耗为27 mW.     

Robustness aware high performance high fan-in domino OR logic design

A novel technique using a keeper with a simultaneous low supply voltage and low body voltage is proposed to improve the overall performance of high fan-in OR gates without modifying the physical dimensions of the keeper. Simulation results of a 16-input domino OR gate using 45 nm CMOS technology show that the proposed technique could trade off between a high power/speed efficient operation and the robustness to noise effectively.Also, a Monte Carlo analysis indicates that the proposed domino OR gate is more robust to parameter variation compared to a conventional domino OR gate.     

灰度图像逻辑或运算 CNN 模板的顽健性设计

通过制定灰度图像的逻辑或运算法则,提出一类灰度图像逻辑或运算CNN,它可以在两幅灰度图像的对应像素点上执行逻辑或运算。对GLOGOR CNN的模板进行鲁棒性分析,建立了一个定理,并给出严格的数学证明。只要模板参数满足定理中给出的参数不等式,CNN就能执行逻辑或运算的任务。数值模拟验证了GLOGOR CNN在应用中的有效性及鲁棒性设计定理的可行性。     

Power optimization algorithm based on XNOR/OR logic

Based on the investigation of the XNOR/OR logical expression and the propagation algorithm of signal probability, a low power synthesis algorithm based on the XNOR/OR logic is proposed in this paper. The proposed algorithm has been implemented with C language. Fourteen Microelectronics Center North Carolina (MCNC) benchmarks are tested, and the results show that the proposed algorithm not only significantly reduces the average power consumption up to 27% without area and delay compensations, but also makes the runtime shorter.     

Speed enhancement techniques for Clock-Delayed Dual Keeper Domino logic style

ABSTRACT

Domino circuit topology for high-speed operation, robustness and lower power consumption is quintessential in design of digital systems. In this paper, various high speed and robust mechanisms are proposed to enhance the speed of Clock-Delayed Dual Keeper Domino (CDDK) circuit. Delayed enabling of keeper circuit in CDDK domino circuit reduces contention between keeper circuit and Pull-Down network (PDN). The speed of transition at the dynamic node of the CDDK domino circuit is enhanced through imposing techniques namely (i) controlled clock delay time in enabling the keeper transistor, (ii) keeper control signal voltage swing variation, (iii) sizing of keeper transistors and (iv) deploying an additional conditional discharge path. The robustness of CDDK circuit is increased by upsizing the keeper transistor without degrading the speed by stack arrangement of dual keeper transistors. The simulation of enhancement techniques has been performed using Cadence® Virtuoso ADEL and ADEXL environments employing UMC 90nm technology library. The simulation results of wide fan-in 64-input OR gate demonstrate that CDDK technique with additional discharge path offer 38% increase in speed and CDDK technique with keeper transistor upsizing offers 52% increase in noise gain margin without speed degradation while comparing with the conventional domino logic circuit.     

Pass transistor with dual threshold voltage domino logic design using standby switch for reduced subthreshold leakage current

Dual threshold voltages domino design methodology utilizes low threshold voltages for all transistors that can switch during the evaluate mode and utilizes high threshold voltages for all transistors that can switch during the precharge modes. We employed standby switch can strongly turn off all of the high threshold voltage transistors which enhances the effectiveness of a dual threshold voltage CMOS technology to reduce the subthreshold leakage current. Subthreshold leakage currents are especially important in burst mode type integrated circuits where the majority of the time for system is in an idle mode. The standby switch allowed a domino system enters and leaves a low leakage standby mode within a single clock cycle. In addition, we combined domino dynamic circuits style with pass transistor XNOR and CMOS NAND gates to realize logic 1 output during its precharge phase, but not affects circuits operation in its evaluation and standby phase. The first stage NAND gates output logic 1 can guarantee the second stage computation its correct logic function when system is in a cascaded operation mode. The processing required for dual threshold voltage circuit configuration is to provide an extra threshold voltage involves only an additional implant processing step, but performs lower dynamic power consumption, lower delay and high fan-out, high switching frequencies circuits characteristics. SPICE simulation for our proposed circuits were made using a 0.18 µm CMOS process from TSMC, with 10 fF capacitive loads in all output nodes, using the parameters for typical process corner at 25 °C, the simulation results demonstrated that our designed 8-bit carry look-ahead adders reduced chip area, power consumption and propagation delay time more than 40%, 45% and around 20%, respectively. Wafer based our design were fabricated and measured, the measured data were listed and compared with simulation data and prior works. SPICE simulation also manifested lower sensitivity of our design to power supply, temperature, capacitive load and process variations than the dynamic CMOS technologies.     

Design and simulation of an ultra-low power high performance CMOS logic: DMTGDI

An ultra-low power, high speed dual mode CMOS logic family called DMTGDI is introduced. This logic family takes over and improves main characteristics of Gate Diffusion Input (GDI) and Dual Mode Logic (DML). Simulations have been performed in 90 nm CMOS on a single bit full adder. DMTGDI shows 60% performance improvement over conventional DML, and significant reduction of power-delay product (PDP), of about 95% in static mode, and 75% in dynamic mode. Monte Carlo simulations reveal that DMTGDI is more robust under process variation comparing to conventional DML. Post layout simulation demonstrates negligible effect of parasitic elements on performance of the single bit adder.     

Thermal aware design and comparative analysis of a high performance 64-bit adder in FD-SOI and bulk CMOS technologies

Thermal behaviours of high-performance digital circuits in bulk CMOS and FDSOI technologies are compared on a 64-bit Kogge-Stone adder designed in 40 nm node. Temperature profiles of the adder in bulk and FDSOI are extracted with thermal simulations and hotspot locations are studied. The influence of local power density on peak temperature is examined. It is shown that high power density devices have significant influence on peak temperature in FDSOI. It is found that some group of devices that perform the same function are the most prominent heat generators. A modification on the design of these devices is proposed which decreases the hotspot temperatures significantly.     

高功耗2.5D封装的热性能优化设计分析

Based on ANSYS and Icepak softwares, the numerical analysis method is used to build up the thermal analysis model of the 2.5D package, which contains a high power CPU chip. The focus of the research is on the determination of the contributing factors and their effects on the thermal resistance and heat distribution of the package. The parametric analysis illustrates that the substrate conductivity, TIM conductivity and fin height are more crucial for heat conduction in the package. Furthermore, these major parameters are compared and analyzed by orthogonal tests, and the optimal solution for 2.5D integration is proposed. The factors' influence patterns on thermal resistance, obtained in this article, could be utilized as a thermal design reference.     

Variability-aware 7T SRAM circuit with low leakage high data stability SLEEP mode

The design of nanoscale static random access memory (SRAM) circuits becomes increasingly challenging due to the degraded data stability, weaker write ability, increased leakage power consumption, and exacerbated process parameter variations in each new CMOS technology generation. A new asymmetrically ground-gated seven-transistor (7T) SRAM circuit is proposed for providing a low leakage high data stability SLEEP mode in this paper. With the proposed asymmetrical 7T SRAM cell, the data stability is enhanced by up to 7.03x and 2.32x during read operations and idle status, respectively, as compared to the conventional six-transistor (6T) SRAM cells in a 65 nm CMOS technology. A specialized write assist circuitry is proposed to facilitate the data transfer into the new 7T SRAM cells. The overall electrical quality of a 128-bit×64-bit memory array is enhanced by up to 74.44x and 13.72% with the proposed asymmetrical 7T SRAM cells as compared to conventional 6T and 8T SRAM cells, respectively. Furthermore, the new 7T SRAM cell displays higher data stability as compared to the conventional 6T SRAM cells and wider write voltage margin as compared to the conventional 8T SRAM cells under the influence of both die-to-die and within-die process parameter fluctuations.