基于投影寻踪分析的芯片硬件木马检测

提出一种利用芯片旁路泄漏信息的硬件木马无损检测方法,通过基于绝对信息散度指标的投影寻踪技术,将芯片运行过程中产生的高维旁路信号投影变换到低维子空间,在信息损失尽量小的前提下发现原始数据中的分布特征,从而实现芯片旁路信号特征提取与识别。针对示例性高级加密标准(AES-128)木马电路的检测实验表明,该技术可以有效分辨基准芯片与硬件木马测试芯片之间的旁路信号特征差异,实现硬件木马检测。     

基于旁路分析的集成电路芯片硬件木马检测

针对密码芯片中硬件木马电路检测的困难性,介绍了根据芯片旁路信息进行硬件木马检测的思想．在形式化定义基于旁路分析的硬件木马检测问题的基础上,分析了含硬件木马与不含硬件木马的密码芯片对应旁路信号在主成份分析结果上的差异,并以此对FPGA实现的含硬件木马的DES密码原型芯片进行了检测实验,实验结果表明了基于旁路信号主成份分析在密码芯片硬件木马检测中的效果．     

一种基于核最大间距准则的硬件木马检测新方法

在功耗旁路信号统计模型的基础上,提出了一种基于核最大间距准则的硬件木马检测方法及改进的检测方法.将原始功耗旁路信号映射到高维空间,使其具有更高的可分性,然后再投影到低维子空间,从而发现原始数据中的非线性差异特征,实现功耗旁路信号的非线性特征提取与识别.针对AES加密电路中木马电路的检测实验表明,该方法测得超出检测边界的样本数(792)多于Karhunen-Loève变换(400),取得更好的检测效果.     

基于旁路分析的集成电路芯片硬件木马检测分析

本文基于传统密码芯片内检测电路硬件木马的难度较高,鉴于这种状况本课题综合各类芯片旁路信息提出了完善硬件木马检测方案的思路,以形式化定义了件木马检测相关问题,解读含与不含硬件木马的密码芯片相应旁路信号于主成份分析结果上显现出的差别,并通过标准实验检测了含有硬件木马的DES密码原型芯片,实验所得结果证实了芯片硬件木马检测中旁路信号主成份分析的有效性,值得推广。     

旁路信号主成分分析的欧式距离硬件木马检测

针对集成电路中的硬件木马问题,利用旁路信号分析技术,设计了一种基于集成电路芯片的硬件木马检测模型。在对提取出的旁路信号进行主成分分析降维基础上,运用欧式距离分类法进行硬件木马的分类识别和检测。最后运用功耗分析的方法进行了算法有效性验证。     

一种基于压缩边界Fisher分析的硬件木马检测方法

针对物理环境下旁路分析技术对电路中规模较小的硬件木马检出率低的问题,该文引入边界Fisher分析(MFA)方法,并提出一种基于压缩边界Fisher分析(CMFA)的硬件木马检测方法。通过减小样本的同类近邻样本与该样本以及类中心之间距离和增大类中心的同类近邻样本与异类样本之间距离的方式,构建投影空间,发现原始功耗旁路信号中的差异特征,实现硬件木马检测。AES加密电路中的硬件木马检测实验表明,该方法具有比已有检测方法更高的检测精度,能够检测出占原始电路规模0.04%的硬件木马。     

用于检测硬件木马延时的线性判别分析算法

针对芯片生产链长、安全性差、可靠性低,导致硬件木马防不胜防的问题,该文提出一种针对旁路信号分析的木马检测方法。首先采集不同电压下电路的延时信号,通过线性判别分析(LDA)分类算法找出延时差异,若延时与干净电路相同,则判定为干净电路,否则判定有木马。然后联合多项式回归算法对木马延时特征进行拟合,基于回归函数建立木马特征库,最终实现硬件木马的准确识别。实验结果表明,提出的LDA联合线性回归(LR)算法可以根据延时特征识别木马电路,其木马检测率优于其他木马检测方法。更有利的是,随着电路规模的增大意味着数据量的增加,这更便于进行数据分析与特征提取,降低了木马检测难度。通过该方法的研究,对未来工艺极限下识别木马电路、提高芯片安全性与可靠性具有重要的指导作用。     

一种木马电路的实现与特征分析

由于硬件木马等恶意电路的隐蔽性,攻击者可以利用其窃取机密信息,破坏硬件电路,造成严重的经济损失与社会危害.本文基于典型的芯片设计流程与EDA工具,首先建立硬件木马的电路模型,然后尝试在一简单ADC芯片中,利用其电路的剩余空间,设计实现了一种计数器木马电路.该木马电路的规模大约占芯片总面积的5.6%,将受污染的电路与真实电路一起用标准CMOS工艺HJ0.25μm流片,然后采用旁路功耗分析技术进行深入分析.实验数据表明,在正常工作情况下,受污染和没受污染的芯片功耗并无明显差异,而当木马触发条件满足时,受污染的芯片却成功的实现了攻击.     

芯片级木马检测技术研究综述

集成电路在各个领域都具有极其重要的作用,但是在当今集成电路设计、制造、测试、封装各种环节相分离的产业模式下,用户所使用的芯片可能会被别有用心者植入硬件特洛伊木马电路,这给信息安全领域带来了严重威胁,芯片级硬件木马的检测技术已经成为了芯片安全研究领域的新热点。首先介绍了硬件木马的概念、危害以及分类方式;然后对硬件木马检测技术国内外有影响的研究成果进行了详细的总结和评述,着重阐述了目前比较有效的旁路分析方法,指出基于功耗指纹分析的硬件木马检测技术是当前最有前途的一种检测方法;最后简要总结了硬件木马的主动防御机制。     

基于温度特征分析的硬件木马检测方法

硬件木马是一种在特定条件下使集成电路失效或泄露机密信息等的恶意电路,给现代信息系统带来了严重的安全隐患。该文基于硬件木马在芯片工作之初造成的温度响应特征,提出一种利用芯片温度变化特性并进行比对的硬件木马检测方法。该方法采用环形振荡器作为片内温度特征测量传感器,提取温度变化特征信息,并采用曲线拟合评价指标来评估硬件木马对温度变化特征的影响,通过比对无木马芯片温度响应特征从而完成木马检测。通过对10个不同芯片的检测,结果表明该方法能够对面积消耗32个逻辑单元硬件木马的检测率达到100%,对16个逻辑单元检测概率也能达到90%;同时检测结果表明该方法完成硬件木马检测后,能够对硬件木马的植入位置进行粗定位。     

Effective usage of redundancy to aid neutralization of hardware Trojans in Integrated Circuits

Hardware Trojans are malicious alterations in Integrated Circuits (ICs) that leak confidential information or disable the entire IC. The detection of these Trojans is performed through logic or side channel based testing. Under sub-nm technologies the detection of Hardware Trojans will face more problems due to process variations. Hence, there is a need to devise countermeasures which do not depend completely on detection. In order to achieve such a countermeasure, we propose to neutralize the effect of Hardware Trojans through redundancy. In this work, we present a Triple Modular Redundancy (TMR) based methodology to neutralize Hardware Trojans. In order to address the inevitable overhead on area, TMR will be implemented only on select paths of the circuit. Using a probabilistic model of a given digital circuit, we have measured the effect of Trojan on different paths of the circuit and found that equally probable output paths are vulnerable to Trojan placement. Therefore for security we propose that TMR should be implemented on the paths that lead to equally probable primary outputs. We have also shown that the detection of Trojans placed on predictable paths can be achieved through logic based testing methods. In order for the adversary to beat the proposed redundancy model, the size of the Trojan has to be larger. We have shown that such implementation can be detected using side channel based testing.     

硬件木马检测与防护

第三方技术服务的普及使得在集成电路（IC）设计制造过程中,芯片可能被恶意植入“硬件木马”,给芯片的安全性带来了极大挑战,由此,如何检测“安全芯片”中是否存在硬件木马,确保芯片的安全性开始受到人们的广泛关注.在简要介绍硬件木马概念及其危害的基础上,分析硬件木马的特点和结构,介绍了当前现有的几种硬件木马检测技术,给出了硬件木马检测技术的科学分类,重点分析了这些检测方法所面临的问题和挑战并提出了相应的改进措施,总结了未来硬件木马防测技术的发展趋势.     

硬件木马检测与防护

第三方技术服务的普及使得在集成电路（IC）设计制造过程中,芯片可能被恶意植入“硬件木马”,给芯片的安全性带来了极大挑战,由此,如何检测“安全芯片”中是否存在硬件木马,确保芯片的安全性开始受到人们的广泛关注。在简要介绍硬件木马概念及其危害的基础上,分析硬件木马的特点和结构,介绍了当前现有的几种硬件木马检测技术,给出了硬件木马检测技术的科学分类,重点分析了这些检测方法所面临的问题和挑战并提出了相应的改进措施,总结了未来硬件木马防测技术的发展趋势。     

Verification of physical designs using an integrated reverse engineering flow for nanoscale technologies

Considering the potential risks of piracy and malicious manipulation of complex integrated circuits using worldwide distributed manufacturing sites, an effective and efficient reverse engineering process allows the verification of the physical layout against the reference design. This paper provides an overview of the current process and details on a new tool for the acquisition and synthesis of large area images and the recovery of the design from a physical device. Using this reverse engineering process on a physical chip layout, a circuit graph based partitioning of circuit blocks and an Elliptic Curve Cryptography (ECC) module identification will be performed. For the first time, the error between the generated layout and the design GDS layout will be compared quantitatively as a figure of merit (FoM). We propose a new classification of malicious manipulations based on their layout impact.     

Resolution Enhancement Technology:Integrated Process Solutions using OPC

DUV lithography, using the 248 nm wavelength, is a viable manufacturing option for devices with features at 130 nm and less. Given the low kl value of the lithography, integrated process development is a necessary method for achieving acceptable process latitude. The application of assist features for rule based OPC requires the simultaneous optimization of the mask, illumination optics and the resist.Described in this paper are the details involved in optimizing each of these aspects for line and space imaging.A reference pitch is first chosen to determine how the optics will be set. The ideal sigma setting is determined by a simple geometrically derived expression. The inner and outer machine settings are determined, in turn,with the simulation of a figure of merit. The maximum value of the response surface of this FOM occurs at the optimal sigma settings. Experimental confirmation of this is shown in the paper.Assist features are used to modify the aerial image of the more isolated images on the mask. The effect that the diffraction of the scattering bars (SBs) has on the image intensity distribution is explained. Rules for determining the size and placement of SBs are also given.Resist is optimized for use with off-axis illumination and assist features. A general explanation of the material' s effect is discussed along with the affect on the through-pitch bias. The paper culminates with the showing of the lithographic results from the fully optimized system.     

Cost-effective test solutions for smart card and other integrated flash applications

From its emergence in the late 1980s as a lower cost alternative to early EEPROM technologies, flash memory has evolved to higher densities and speedsand rapidly growing acceptance in mobile applications.In the process, flash memory devices have placed increased test requirements on manufacturers. Today, as flash device test grows in importance in China, manufacturers face growing pressure for reduced cost-oftest, increased throughput and greater return on investment for test equipment. At the same time, the move to integrated flash packages for contactless smart card applications adds a significant further challenge to manufacturers seeking rapid, low-cost test.     

Theoretical analysis of the relationship between the Brillouin gain coefficient and the strain in the optical-fiber sensors

The relation between the power of the Brillouin signal and the strain is one of the bases of the distributed fiber sensors of temperature and strain. The coefficient of the Bfillouin gain can be changed by the temperature and the strain that will affect the power of the Brillouin scattering. The relation between the change of the Brillouin gain coefficient and the strain is thought to be linear by many researchers. However, it is not always linear based on the theoretical analysis and numerical simulation. Therefore, errors will be caused if the relation between the change of the Brillouin gain coefficient and the strain is regarded as to be linear approximately for measuring the temperature and the strain. For this reason, the influence of the parameters on the Brillouin gain coefficient is proposed through theoretical analysis and numerical simulation.     

An improved parallel thinning algorithm with two subiterations

The parallel thinning algorithm with two subiterations is improved in this paper. By analyzing the notions of connected components and passes, a conclusion is drawn that the number of passes and the number of eight-connected components are equal. Then the expression of the number of eight-connected components is obtained which replaces the old one in the algorithm. And a reserving condition is proposed by experiments, which alleviates the excess deletion where a diagonal line and a beeline intersect. The experimental results demonstrate that the thinned curve is almost located in the middle of the original curve connectivelv with single pixel width and the processing speed is high.