基于软件预处理的空间光调制器驱动电路研制

研制了一套基于软件预处理的多量子阱空间光调制器驱动电路.针对不同的多量子阱空间光调制器,软件预处理单元根据其反射特性,拟合出它的反射谱线.根据反射谱线产生相应的光电转换控制信号,增强了该驱动电路的通用性,降低了驱动电路的复杂性.改进一次扫描的方式,采用先粗扫再细扫的二次扫描方式,在保证扫描速度及分辨率的同时,有效降低了单元像素驱动电路的面积.SPICE仿真结果和芯片测试结果均证明,驱动电路芯片工作良好,驱动电压输出摆幅为0～VDD.驱动电压分辨率可达256级.总之,所设计的驱动电路满足空间光调制器的需求.     

A programmable driving circuit for multi-quantum-well spatial-light-modulator

A universal programmable driving circuit of multi-quantum-well spatial light modulator was described. The driving circuit, by double scanning and employing a new current-switching network, reduces the pixel??s estate and improves the output resolution. The results of test by chip show that the driving voltage could swing from 0 to V _DD, and its resolution could reach to 256 with only 65?×?65???m pixel estate.     

应用于AMOLED源极驱动的高精度DAC设计

针对OLED显示面板更高分辨率、更高精度的需求,本文提出了一种应用于高分辨率AMOLED源极驱动的高精度10bit DAC结构。设计的DAC由6bit的GAMMA校正电阻串DAC及4bit的基于尾电流源插值的输出缓冲器级联构成,达到高精度的同时占用较小的芯片面积。为进一步提高AMOLED驱动的灰阶电压精度,增加了一个DAC斜率可编程单元对线性DAC输出曲线进行进一步调节,以更好地拟合AMOLED显示屏所需的灰阶-电压曲线,此外,输出缓冲器采用尾电流源插值的方法来实现高精度的第二级DAC。在UMC 80nm CMOS工艺下,仿真结果表明设计的DAC的最大INL和DNL分别为0.47LSB、0.24LSB。在10kΩ电阻及30pF电容负载下,DAC电压从最低灰阶到最高灰阶的建立时间为3.38μs。驱动电路可以快速、精确地将图像数据转换为建立在像素电路上的电压,满足分辨率为1080×2 160驱动芯片的应用需求。     

A polymer electro-optic modulator with ultra wide-band and low driving voltage

In this paper, a polymer electro-optic modulator is designed and simulated using the full vectorial finite element method. First order edge elements are used in finite element implementation, and the finite element technique is used to obtain modulator response thoroughly. From the numerical analysis, frequency dispersions of modulator’s important parameters, such as microwave effective index nm , microwave characteristic impedance ZC and microwave loss a, are extracted. Our design exhibits elec...     

A 10 Gb/s 0.25 μm SiGe modulator driver for photonic-integration

A 10 Gb/s modulator driver in SiGe 0.25 μm BiCMOS technology with a chip area of only 0.54 mm² is presented. The intentions of designing this modulator driver are to amplify small incoming data signals at 10 Gb/s and to integrate the driver together with a silicon optical phase modulator (Mach–Zehnder modulator in push–pull configuration) on the same chip. The driver is designed to have a low power-consumption of 0.68 W but a high gain (S₂₁ = 37 dB). It consists of a differential pre-amplifier with common-mode feedback and automatic gain control, which is supplied by 2.5 V. The differential output stage is supplied with 3.5 V. The driver is designed to drive a Mach–Zehnder modulator, which uses in his arms carrier depletion in a reverse biased pn junction to adjust the refractive index. The differential output (5V_pp) delivers two times a voltage between 0 and 2.5 V. Therefore no bias-T is needed at the output to assure that the diodes of the interferometer arms are in the reverse biased mode. In addition to the low-power design, a passive network instead of an additional amplifier circuit for driving the cascode transistors, which reduce the collector–emitter voltage of each transistor in the output stage below breakdown, is presented. According to bit-error-ratio (BER) measurements with a pseudo-random-bit-sequence with the length of 2³¹ ? 1 the BER is better than 10^?12 for input voltage differences down to 50 mV_pp. The rise/fall time (20–80 %) is 45/30 ps respectively.     

基于电流型脉宽调制器的自适应反激驱动开关电源的设计

分析了一种采用3844B电流型脉宽调制器控制,实现多路输出的单端反激式大功率IGBT驱动电源。根据控制芯片特性与输出要求给出了详细的电路参数,设计了符合要求的高频变压器,提出改进的反馈控制方法,具有很强的自适应性。实验结果表明,该电源的可靠性更高,稳定性好,输出纹波小,能够适应规定电网电压波动195V到265V的要求,甚至更大的电压波动。     

一种数控电位器调节的压电陶瓷驱动电源

设计了一种用于驱动数字共焦显微仪压电陶瓷物镜驱动器,实现数控电位器调节的压电陶瓷驱动电源,由单片机系统、前级高压稳压电路、数控电位器、功率放大电路、高压稳压电源和放电回路组成。采用前级高压稳压代替电压放大级作为输入,通过高分辨率的数控电位器调节,经功率放大和放电回路后驱动压电陶瓷驱动器。该驱动电源输出电压稳定,数控可调且随输入电压呈线性变化,可实现对电压精密控制,适用于驱动压电陶瓷等容性负载。     

A 0.5 μm Concurrent Testable Chip of a Fifth-Order g m -C Filter

In this paper, we describe a testable chip of a fifth-order g _m -C low-pass filter that has a passband from 0 to 4.5 MHz. We use a current-mode method for the error detection of this filter. By comparing the current consumed by the circuit under test (CUT) and the current converted from the voltage levels of the CUT, abnormal function of circuit components can be concurrently and efficiently detected. A test chip has been fabricated using a 0.5 m, 2P2M CMOS technology. Measurement results show that this current-mode approach has little impact on the performance of the filter and can detect faults in the filter effectively. The area overhead of the circuitry for testing in this chip is about 18%.     

Experimental optimisation of MQW electroabsorption modulators withup to 40 GHz bandwidths

Three MQW electroabsorption modulator structures made of 7, 13 and 20 wells are reported. The bandwidth is shown to increase linearly with intrinsic region thickness up to 40 GHz, with negligible penalty on the drive voltage which remains at less than 2 V. It is suggested that 100 GHz bandwidth should be reached with low drive voltage     

Threshold-Volgage control schemes through substrate-bias for low-power high-speed CMOS LSI design

Lowering supply voltage,V _DD, is the most effective means to reduce power dissipation of CMOS LSI design. In lowV _DD, however, circuit delay increases and chip performance degrades. There are two means to maintain the chip performance: 1) to lower the threshold voltage,V _th, to recover circuit speed, or 2) to introduce parallel and/or pipeline architectures to make up for slow device speed. The first approach increases standby power dissipation due to lowV _th, while the second approach degrades worst case circuit speed caused byV _th fluctuation in lowV _DD. This paper presents two circuit techniques to solve these problems, in both of whichV _th is controlled through substrate bias. A Standby Power Reduction (SPR) scheme raisesV _th in a standby mode by applying substrate bias with a voltage-switch circuit. A Self-Adjusting Threshold-Voltage (SAT) scheme reducesV _th fluctuation in an active mode by adjusting substrate bias with a feed-back control circuit. Test chips are fabricated and effectiveness of the circuit techniques is examined. The SPR scheme reduces 50% of the active power dissipation while maintaining the speed and the standby power dissipation. The SAT scheme improves worst case circuit speed by a factor of 3 under a 1 VV _DD.     

Design and measurement of an MQW nipi waveguide modulator foroptoelectronic integrated circuits

A procedure for optimizing MQW hetero-nipi waveguide phase modulators is presented that includes both drive voltage and frequency response. Experimental phase change, absorption change, and frequency response measurements of a modulator designed using this algorithm are presented. In a 300-μm-long device consisting of 3 nipi periods, π phase shift is achieved with an applied voltage of 3.25 V with a frequency bandwidth on the order of 200 MHz     

600V HVIC高噪声抑制电平移位电路

A novel level shift circuit featuring with high dV/dt noise immunity and improved negative V_S capacity is proposed in this paper.Compared with the conventional structure,the proposed circuit adopting two cross-coupled PMOS transistors realizes the selective filtering ability by exploiting the path which filters out the noise introduced by the dV/dt.In addition,a differential noise cancellation circuit is proposed to enhance the noise immunity further.Meanwhile,the negative V_S capacity is improved by unifying the detected reference voltage and the logic block’s threshold voltage.A high voltage half bridge gate drive IC adopting the presented structure is experimentally realized by using a usual 600 V BCD process and achieves the stable operation up to 65 V/ns of the dV/dt characteristics.     

High-speed InGaAlAs/InAlAs multiple quantum well optical modulators

High-speed modulation over 22 GHz for waveguided InGaAlAs/InAlAs multiple quantum well (MQW) optical modulators is described. A large on/off ratio of over 25 dB is demonstrated with a low-drive voltage (6 V) operating in the 1.55-μm wavelength region. The design and characteristics of MQW p-i-n modulators are discussed. The causes of large-insertion loss and the required drive voltage bandwidth figure of merit for the MQW modulator are discussed. The frequency response measurements show that the response speed is limited by the RC time constant of the device. This suggests that the speed can be further enhanced by decreasing the size and capacitance of the device     

Improved control for high power static var compensator using novel vector product phase locked loop (VP-PLL)

This paper presents a new dual loop control using novel vector product phase locked loop (VP-PLL) for a high power static var compensator (SVC) with three-level GTO voltage source inverter (VSI). From a simple dq-axis equivalent circuit obtained by circuit DQ-transformation method, steady-state analysis is achieved for maximum controllable phase angle α_max per unit current between AC source and switching function of inverter. In addition, the system parameters L and C are designed and thus transient analysis is made for open-loop transfer function. This paper proposes software VP-PLL for more accurate α control than conventional hardware PLL because α_max becomes very small in high power SVC. Therefore, the overall controller has dual loop structure of inner VP-PLL for synchronizing the phase angle with AC source and outer Q-loop for compensating reactive power of load. Finally, the usability of the proposed control method is verified through the experiment of 100kvar power capacity with both stand alone and load linked operation.     

A low-drive-voltage, high-speed monolithic multiple-quantum-wellmodulator/DFB laser light source

A high-speed InGaAs/InAlAs multiple-quantum-well (MQW) intensity modulator and an InGaAsP/InGaAs MQW distributed feedback laser were monolithically integrated by using a hybrid growth technique combining molecular beam epitaxy and metalorganic vapor phase epitaxy. An operating drive voltage of only 2.0 V, a 20-dB on/off ratio, and a 3-dB bandwidth greater than 15 GHz were obtained. This device operated stably in a single mode and with a side-mode suppression ratio of more than 50 dB     

基于直流无刷电机的太阳能水泵控制系统设计

基于无位置传感器永磁无刷直流电机设计了一款以STM32为主控芯片的太阳能水泵控制系统。主要介绍了硬件设计和软件设计两大部分,硬件设计包含开关逆变电路、驱动电路、电压检测电路等。软件设计包含主程序、自检程序、中断程序和故障保护程序流程。设计核心是采用MOS管内阻采样三相电流,并通过反电势过零检测法获取转子位置信号。在三相潜水泵上进行验证,相关试验波形图和数据验证了该系统硬件电路的可靠性以及软件程序架构的可行性。     

Full-wave modelling and broadband characterization of coupled interconnects in high-speed VLSI

A time-domain full-wave method for the extraction of broadband equivalent circuit parameters of symmetrical coupled interconnection lines on chips is presented. This method is based on the two-dimensional finite-difference time-domain method. After determination of the even and odd mode propagation constant γ and characteristic impedance Z _c of the lines, the RLGC matrices per unit length can be obtained. Many techniques are proposed and used during the time-domain analysis to improve the efficiency. The circuit parameters extracted can be inserted into circuit simulation software to investigate the time-domain responses of high-speed integrated circuits on chips. The reliability of this method is verified by its applications to typical problems.     

Design considerations for a multiple-quantum-well nonresonantsurface-normal modulator

It is shown that by using optimal quantum-well thickness, and by using a symmetric back-to-back p-i-n structure, a non-Fabry-Perot surface-normal reflection modulator based on the quantum confined Stark effect in a GaAs/AlGaAs multiple-quantum-well (MQW) can provide intensity modulation with (a) at least 10-dB contrast ratio, (b) a drive voltage less than 10 V, and (c) an active-layer thickness less than 4 μm. The drive voltage for a given contrast ratio can be minimized by using the quantum-well structure with the maximum Δα/F      

一种全速率线性25Gb/s时钟数据恢复电路

面向高速光通信系统的应用,提出了一种全速率线性25Gb/s时钟数据恢复电路(Clock and Data Recovery Circuit,CDRC)。CDRC采用了混频器型线性鉴相器和自动锁频技术来实现全速率时钟提取和数据恢复。在设计中没有使用外部参考时钟。基于45nm CMOS工艺,该CDR电路从版图后仿真结果得到:恢复25Gb/s数据眼图的差分电压峰峰值V_pp和抖动峰峰值分别为1.3V和2.93ps;输出25GHz时钟的差分电压峰峰值V_pp和抖动峰峰值分别为1V和2.51ps,相位噪声为-93.6dBc/Hz@1MHz。该芯片面积为1.18×1.07mm²,在1V的电源电压下功耗为51.36mW。     

Tunable mixed-mode OTA-C universal filter

A novel electronically tunable mixed-mode universal biquad by using four single-output and one dual-output-operational transconductance amplifiers, two grounded capacitors is proposed. The proposed circuit has ability to realize voltage, current, transconductance, and transresistance mode, and can the following advantageous features: (i) realization of low-pass, band-pass, high-pass, notch, and all-pass filter responses from the same configuration, (ii) employment of only grounded capacitors ideal for integrated circuit implementation, (iii) orthogonal controlling of ω _o and Q for easily electronic tunability, and (iv) low active and passive sensitivity performance. Finally, to verify our architecture, we have designed this analog filter chip with TSMC 0.35-μm 2P4M CMOS technology. This chip operates to 1 MHz and consumes 30.95 mW. The chip area of the analog filter is about 0.823 mm².