LFSR加密新算法的研究与FPGA实现

提出了一种改进的线性反馈移位寄存器结构的安全加密模型,利用移位寄存器的灵活性高和成本低的特点结合FPGA器件的高速度和可重构的性能,从而使系统达到低成本、可实时配置算法文件和重组安全策略的目的,并详细论述了该模型的改进后的线性反馈移位寄存器加密算法的加密原理,然后介绍了该算法的FPGA实现及可重构技术,最后,通过对改进算法的加密时序图的分析和总体性能的评估,证明了该算法在保证安全性能的基础上具有很好的成本优势和可重构性。     

反馈移位寄存器在通用可重构处理器上的配置生成与优化设计

在序列密码算法中,反馈移位寄存器的操作使用频率高且移位位宽和反馈网络灵活多变,针对目前还没有一个通用可配置,支持不同规模的移位寄存器实现方法。本文利用通用可重构处理器基本运算单元数据流和控制流可配置的特点,充分挖掘移位寄存器中并行流水潜力,在通用可重构处理器上,设计反馈移位寄存器的四种不同实现方案,并对算子在通用处理器以及可重构处理器模型上进行性能对比分析。实验表明,运用可重构的方法实现A5密码算法中的反馈移位寄存器效率较Intel ATOM230处理器提高12.6倍,最后在考虑可重构处理器资源制约的条件下,对反馈移位寄存器的实现方法进行优化讨论。     

基于GH-PKC体制的盲签名方案

GH-PKC是一种新的基于GF(q)上三级线性反馈移位寄存器序列的公钥密码体制。其安全性基于有限域GF(q3)上的离散对数困难问题,但运算却在有限域GF(q)中进行。文中给出了一种新的基于GH-PKC的类ELGamal数字签名算法,并在此基础上构建了基于GH-PKC的盲签名方案,其安全性等价于解GF(q3)上离散对数困难问题,但是传输的数据量只有传统方案的1/3。     

基于m序列的可重构线性反馈移位寄存器研究

现今,m序列通常用线性反馈移位寄存器（LFSR）来产生,但产生的序列单一,且其串行的产生方式使得序列的产生速率随码序列周期的增大而成线性增大的趋势。文章分析了线性反馈寄存器的特征多项式,在电路中加入寄存器组,提出了一种改进型线性反馈移位寄存器结构。改进后的电路实现各级寄存器并行输出数据,克服了传统线性反馈移位寄存器产生m序列的速度受字长制约的限制,且电路可以重构特征多项式的系数因子产生多种序列。最后,以周期为15的m序列为例对电路进行了仿真和验证,实验结果表明序列产生速率提高了N／2倍（N为寄存器级数）。     

基于数乘移位寄存器随机滤波的压缩感知

针对随机滤波产生的测量矩阵中行向量间相关性大,重构效果不理想的问题,提出了一种数乘移位寄存器随机滤波问方法.利用数乘移位寄存器反馈线上存有固定值的乘法器,改变了测量矩阵单调循环的结构,减小了行向量之间相关性.分析了数乘移位寄存器随机滤波在一维稀疏信号、二维图像中的重构效果.仿真结果表明,数乘移位寄存器随机滤波具有良好的重构效果,且优于传统随机滤波和部分Hadamard矩阵、Gaussian矩阵.     

基于遗传算法搜索低旁瓣最大长度序列

最大长度序列通过线性反馈移位寄存器产生,广泛应用于脉冲压缩雷达中。针对不同反馈连接产生序列的非周期自相关函数旁瓣特性不同,而目前尚无有效办法寻找具有低旁瓣特性的最大长度序列,利用遗传算法搜索线性反馈移位寄存器的最佳反馈连接,该反馈连接产生最大长度序列非周期自相关函数特性非常好。通过MATLAB仿真了遗传算法搜索过程、最大长度序列非周期自相关函数,给出了4～15级线性反馈移位寄存器反馈连接表,并对最大长度序列非周期自相关函数进行加窗处理,获得了更好的旁瓣抑制效果。     

一类混沌序列线性复杂度的分析

针对传统密码学中由线性移位寄存器生成的序列在统计特性上的不足,提出一种基于混沌的序列密码生成方法,并在有限精度实现时引入Legendre扰动序列使得输出具有良好的统计特性。用B-M算法对其进行线性复杂度分析,并与等效的线性反馈移位寄存器的复杂度进行比较,结果显示该混沌序列具有良好的非线性特性,保密性好且软件实现简单。     

基于AES的可重构加密系统的FPGA设计

针对传统软件加密方法在速度和资源消耗上的不足,提出了基于AES高级加密标准的硬件设计方案。采用了目前流行的EDA技术,在FPGA芯片上实现一种可重构的加密系统,利用硬件描述语言实现加密算法中的移位、S盒置换函数、线性反馈移位寄存器等功能,设计输入、模型综合、布局布线、功能仿真都在Altera公司的Quartus II开发平台中完成,产生的下载文件通过Cyclone系列的FPGA芯片进行测试。实验结果表明,该系统具有独特的物理安全性和高速性。     

对一种新的序列密码结构的密码分析

对新提议的一种基于线性反馈移位寄存器、非线性反馈移位寄存器和过滤布尔函数的序列密码结构的安全性进行了研究,对这种结构给出了一种区分攻击.举例子说明了此攻击的有效性.这种新的攻击表明,此种新的序列密码结构存在潜在的安全弱点.     

无移位操作的快速comb乘法算法

有限域GF(2n)上乘法运算是影响GF(2n)上椭圆曲线密码实现效率的关键运算之一.基于窗口技术的comb乘法算法,被认为是目前有限域GF(2n)上乘法运算最快的算法之一.但是,它仍然使用了移位操作,而移位操作恰好又是域GF(2n)乘法运算中很耗时的操作.提出并实现了一种新的基于窗口技术的快速comb乘法算法,该算法避免了移位操作,且不增加异或运算次数.理论分析和实验结果表明,新算法有很好的实现效率,适合于有限域GF(2n)上椭圆曲线密码算法的软件实现.     

对称密码中复合域乘法运算可重构设计研究

复合域乘法运算是对称密码算法中的基本运算和重要模块,因操作复杂且计算时间长,其实现性能在很大程度上制约着对称密码算法的运算速度。文章研究了对称密码算法中的复合域乘法运算特点及实现原理,设计了以GF（28）为基域,扩展到GF（（28 ）h（k=1,2,3,4）域上的复合域乘法可重构架构,通过配置能够灵活高效地实现GF（2 8）、GF（（2H）2）、GF（2 8）3、CF（（28）4）域上的有限域乘法操作。同时结合处理器的指令设计方法,设计了通用的复合域乘法操作及配置指令,能够极大的提高对称密码算法中复合域乘法运算的处理效率。最后文章对复合域乘法可重构架构进行了模拟与验证,在0．18μmCMOS工艺标准单元库下进行逻辑综合以及布局布线,并对综合结果进行了性能评估。结果表明,文章提出的复合域乘法可重构架构及相应的专用指令,在灵活性的前提下提供了较高的执行效率,具有较高的实用价值。     

On the design of reconfigurable multipliers for integer and Galois field multiplication

Multiplication is a vital function for practically any DSP system. Some common DSP algorithms require different multiplication types, specifically integer or Galois Field (GF) multiplication. Since both functions share similarities in their structures, the potential is given for efficiently combining them in a single reconfigurable VLSI circuit, leading to competitive designs in terms of area, performance, and power consumption. This will be analysed and discussed in detail for 10 reconfigurable multiplier alternatives that are based on different strategies for the combination of integer and GF multiplication. Each result is compared to a reference architecture, showing area savings of up to 20% at a marginal increase in delay, and an increase in power consumption of 25% and above. This gives evidence that function-specific reconfigurable circuits can achieve considerable improvements in at least one design objective with only a moderate degradation in others. From this perspective, function-specific reconfigurable circuits can be considered feasible alternatives to standard ASIC solutions.     

可重构双基双域模乘器设计与实现

选择素数域和二进制域上基于字的Montgomery模乘算法,分析传统双域模乘器在二进制域上运算效率不高的问题,首先选择能够使两个域上模乘器延迟时间相当的字长,并对模乘器进行双域的可重构设计,使之能够同时支持素数域和二进制域上的运算。相较以往设计,采用双域双基设计的模乘器使时钟周期数平均缩短了48%。     

An O((log log n)2) time algorithm to compute the convexhull of sorted points on reconfigurable meshes

The problem of computing the convex hull of a set of n sorted points in the plane is one of the fundamental tasks in image processing, pattern recognition, cellular network design, and robotics, among many others. Somewhat surprisingly, in spite of a great deal of effort, the best previously known algorithm to solve this problem on a reconfigurable mesh of size √n×√n was running in O(log2 n) time. It was open for more than ten years to obtain an algorithm for this important problem running in sublogarithmic time. Our main contribution is to provide the first breakthrough: we propose an almost optimal convex hull algorithm running in O((log log n)²) time on a reconfigurable mesh of size √n×√n. With slight modifications, this algorithm can be implemented to run in O((log log n)²) time on a reconfigurable mesh of size √n/loglogn×√n/loglogn. Clearly, the latter algorithm is work-optimal. We also show that any algorithm that computes the convex hull of a set of n sorted points on an n-processor reconfigurable mesh must take Ω(log log n) time. Our result opens the door to an entire slew of efficient convex-hull-based algorithms on reconfigurable meshes     

Design,implementation and analysis of hardware efficient stream ciphers using LFSR based hash functions

Design and implementation of hardware efficient stream ciphers using hash functions and analysis of their periodicity and security are presented in this paper. The hash generation circuits used for the design and development of stream ciphers are low power, low hardware complexity Linear Feedback Shift Register (LFSR) based circuits. One stream cipher design uses LFSR based Toeplitz hash generation circuit together with LFSR keystream generator circuit, while the other design combines LFSR based filter generator circuit with LFSR based polynomial modular division circuit. Both designs possess good security and periodicity properties for the keystreams generated. The developed circuits can compete with the most popular classic LFSR based stream ciphers in hardware complexity at the same time providing additional advantage that the same circuit can be used for hash generation.     

Optimal design of reconfigurable parallel machining systems

A reconfigurable machining system is usually a modularized system, and its configuration design concerns the selections of modules and the determination of geometric dimensions in some specific modules. All of its design perspectives from kinematics, dynamics, and control have to be taken into considerations simultaneously, and a multidisciplinary design optimization (MDO) tool is required to support the configuration design process. This paper presents a new MDO tool for reconfigurable machining systems, and it includes the following works: (i) the literatures on the computer-aided design of reconfigurable parallel machining systems have been reviewed with a conclusion that the multidisciplinary design optimization is essential, but no comprehensive design tool is available to reconfigurable parallel machining systems; (ii) a class of reconfigurable systems called reconfigurable tripod-based machining system has been introduced, its reconfiguration problem is identified, and the corresponding design criteria have been discussed; (iii) design analysis in all of the disciplines including kinematics, dynamics, and control have been taken into considerations, and design models have been developed to evaluate various design candidates; in particular, the innovative solutions to direct kinematics, stiffness analysis for the design configurations of tripod-based machines with a passive leg, and concise dynamic modelling have been provided; and (iv) A design optimization approach is proposed to determine the best solution from all possible configurations. Based on the works presented in this paper, a computer-aided design and control tool have been implemented to support the system reconfiguration design and control processes. Some issues relevant to the practical implementation have also been discussed.     

Design of low power NFSR for RFID system with irregular clock pulse

This Paper describes the Low Power Non linear Feedback Shift Register (NFSR) for Radio Frequency Identification (RFID) System. RFID systems are widely used in many places for product tracking, monitoring the objects and more. The RFID tag stores its distinctive Electronic Product Code (EPC) with related product information within the tag's memory and encrypts this information before its send to the reader. The RFID tags encrypt the data using Pseudo random numbers. Mostly Linear Feedback Shift Register (LFSR) are used to generating pseudo-random sequences which is less security. Nonlinear Feedback Shift Registers (NFSR) is getting to be more famous in recent years because of the insecurity of LFSR. The output sequence of the LFSR is a linear function of the previous stage, it is easily predictable by intruders. Because of this, NFSR is used in many security systems for generating Pseudo-random numbers. The output sequence of NFSR is irrelevant to the previous stage. In this paper, we proposed a new architecture for NFSR, in this model NFSR is controlled by an LFSR with irregular clocking to generate maximal length sequences. The proposed model is designed using 16 nm CMOS technology and operated in the sub-threshold region. The examination is done using Tanner EDA-Industry Standard design environment. The simulation results demonstrate that the irregular clocking architecture reduces the total power consumption by 30 percent.     

一种基于体系结构模板的粗粒度可重构SoC设计方法

针对传统的面向应用领域的多核SoC体系结构设计方法存在系统结构探索空间大、设计复杂度高等问题,提出了一种基于体系结构模板的粗粒度可重构SoC系统架构设计方法。该设计方法以体系结构设计为中心,体系结构模板可重用、参数可配置,从而缩小了体系结构设计探索空间,提高了体系结构设计效率,降低了应用程序编译器开发复杂性。最后,以密码处理领域为例,将模板参数实例化,构建了一个面向密码处理领域的多核可重构指令集处理器SoC系统(Multi-RISP SoC)。实验结果表明,MultiRISP SoC系统与几个典型可重构平台在性能上相当,但系统构建更为快速高效。