Improved structure for adiabatic CMOS circuits design

Two adiabatic circuits with complementary structure and operation are proposed in this paper. They employ two-phase sinusoidal power clock. The power consumption of the proposed circuits is comparable to that of some previously reported circuits. The problem of floating output nodes is solved by connecting two MOS transistors to the power clock. In particular, using the proposed architecture more than one stage of gates can be computed simultaneously within a single clock-phase, compared to only one stage is computed in every phase by most other adiabatic logic families. With this feature, the latency of the complex logic circuit is greatly improved and the number of buffers required for a pipelining circuit is also reduced. In this paper, a 2:1 multiplexer and full adder are illustrated and simulated. From the PSPICE simulation results, the effectiveness of the proposed approach and the low power characteristic of the designed circuits are validated.     

Energy Efficient Adiabatic Multiplier-Accumulator Design

This paper presents a strategy for minimizing non-adiabatic dissipation in adiabatic arithmetic units. The non-adiabatic dissipation is minimized by architectural design involving a small number of complex logic gates. Circuit design of complex adiabatic gates, based on ordered binary decision diagrams (OBDD), is introduced. An optimized architecture for adiabatic parallel multipliers is proposed and savings in energy dissipation over competing architectures are estimated. Experimental results obtained from implementation of an adiabatic multiply-accumulate (MAC) unit suggest that the proposed strategy provides substantial improvement in energy efficiency over equivalent non-adiabatic and alternative adiabatic implementations, while achieving a competitive operating speed.     

Improved adiabatic pseudo-domino logic family

An improved input-isolation structure for APDL (adiabatic pseudo-domino logic) is proposed. The proposed circuit, IAPDL (improved APDL), provides a higher frequency performance in excess of 1 GHz with simple clock supplies. It is more compact compared with T-APDL (transmission gate-interfaced APDL) and the power dissipation is generally about half that of APDL. HSPICE simulations were performed and the results indicate that a reduction of up to 75% in power dissipation can be achieved compared to conventional CMOS     

交叉耦合绝热动态触发器及同步动态时序电路

本文提出交叉耦合绝热动态触发器及其同步时序电路综合方法。首先利用文献[1]的电路三要素理论定量描述交叉耦合型绝热锁存器，由绝热主锁存器和从锁存器构成一个单相输入的绝热触发器。在交叉耦合型绝热触发器的基础上，本文提出绝热同步动态时序电路综合方法，用此法设计出绝热8421BCD码错码检测电路（仅用50管），总功耗小于三个绝热ADL非门的功耗，计算机模拟验证本文方法的正确性。     

具有交叉耦合结构的能量恢复型电路

本文从改变能量传输方式的观点出发讨论了ＣＭＯＳ电路中的绝热开关原理,并对如何实现恢复进行了分析。本言语重点对具有交 耦合结构的绝热电路的特性作了分析比较,并在ＰＡＬ电路诉基础上提出了一种与之相补的绝热电路－ＰＡＬ－１电路。     

Adiabatic-CMOS/CMOS-adiabatic logic interface circuit

This paper describes the design of an adiabatic-CMOS/CMOS-adiabatic logic interface circuit for a group of low-power adiabatic logic families with a similar clocking scheme. The circuit provides interfacing between several recently proposed low-power adiabatic logic circuits and traditional digital CMOS circuits. One advantage of this design is that it is insensitive to clock overlap. With the proposed interface circuit, both adiabatic and CMOS logic circuits are able to co-exist on a single chip, taking advantage of the strengths of each approach in the design of low power systems.     

绝热开关的工作特性及其能耗分析

本文对绝热充电原理以及绝热开关的工作特性进行了详细讨论,建立了绝热开关的能耗计算模型。ＰＳＰＩＣＥ模拟证明了所提出的计算模型的正确性。文章最后对包括输入激励在内的整个绝热开关的能耗进行了综合分析,它是分析复杂绝热电路的基础并为在设计能量恢复型电路时合理选取在关参数提供了理论依据。     

量子绝热近似条件与量子几何势

阐述了传统量子绝热定理，给出了传统的量子绝热近似条件.基于传统的量子绝热近似条件存在不足，采用微扰论思想，通过 绝热变换不变，给出并讨论了新的绝热理论以及新的绝热近似条件.最后对新的绝热条件中所包含量子几何势的几何性进行了较为深入的分析和讨论.     

A Low Power 16‐Bit RISC Microprocessor Using ECRL Circuits

This paper presents a low power 16‐bit adiabatic reduced instruction set computer (RISC) microprocessor with efficient charge recovery logic (ECRL) registers. The processor consists of registers, a control block, a register file, a program counter, and an arithmetic and logical unit (ALU). Adiabatic circuits based on ECRL are designed using a 0.35 µm CMOS technology. An adiabatic latch based on ECRL is proposed for signal interfaces for the first time, and an efficient four‐phase supply clock generator is designed to provide power for the adiabatic processor. A static CMOS processor with the same architecture is designed to compare the energy consumption of adiabatic and non‐adiabatic microprocessors. Simulation results show that the power consumption of the adiabatic microprocessor is about 1/3 compared to that of the static CMOS microprocessor.     

三值绝热多米诺加法器开关级设计

通过对绝热多米诺电路和加法器的研究,该文提出一种新颖低功耗三值加法器的开关级设计方案。该方案首先利用开关-信号理论,结合绝热多米诺电路结构特点,推导出三值加法器本位和电路与进位电路的开关级结构式,由此得到一位三值加法器单元电路;然后通过单元电路的级联得到四位三值绝热多米诺加法器;最后,利用Spice软件对所设计的电路进行模拟,结果显示所设计的四位三值绝热多米诺加法器具有正确的逻辑功能,与四位常规多米诺三值加法器相比,能耗节省约61%。     

Study of Scaling Trends in Energy Recovery Logic: An Analytical Approach

This paper presents an analytical model to study the scaling trends in energy recovery logic. The energy performance of conventional CMOS and energy recovery logic are compared with scaling the design and technology parameters such as supply voltage, device threshold voltage and gate oxide thickness. The proposed analytical model is validated with simulation results at 90 nm and 65 nm CMOS technology nodes and predicts the scaling behavior accurately that help us to design an energy-efficient CMOS digital circuit design at the nanoscale. This research work shows the adiabatic switching as an ultra-low-power circuit technique for sub-100 nm digital CMOS circuit applications.     

Performance analysis of a complete adiabatic logic system driven by the proposed power clock generator

We analyze the energy performance of a complete adiabatic circuit/system including the Power Clock Generator （PCG） at the 90 nm CMOS technology node. The energy performance in terms of the conversion efficiency of the PCG is extensively carried out under the variations of supply voltage, process comer and the driver transistor＇s width. We propose an energy-efficient singe cycle control circuit based on the two-stage comparator for the synchronous charge recovery sinusoidal power clock generator （PCG）. The proposed PCG is used to drive the 4-bit adiabatic Ripple Carry Adder （RCA） and their simulation results are compared with the adiabatic RCA driven by the reported PCG. We have also simulated the logically equivalent static CMOS RCA circuit to compare the energy saving of adiabatic and non-adiabatic logic circuits. In the clock frequency range from 25 MHz to 1GHz, the proposed PCG gives a maximum conversion efficiency of 56.48%. This research work shows how the design of an efficient PCG increases the energy saving of adiabatic logic.     

新型绝热微环谐腔型低功耗硅基调制器的设计

为了改进绝热微环谐腔型的结构、降低谐振腔腔体损耗,采用了基于绝热过渡曲线的设计方法,提出了新型载流子注入/抽取结构,进行了理论分析和实验验证,取得了绝热微环谐振腔的谐振峰线宽、消光比及频率响应参量数据,比较了其与传统微环谐振腔的损耗.结果表明,使用所设计的外半径为2m的谐振腔的谐振峰线宽仅为普通微环谐振腔的29.5%,消光比为13.5dB,电阻电容限制带宽提高了4倍,10Gbit/s调制速率下能耗仅为5.1fJ/bit.这一结果大幅改善了绝热微环谐振腔的频率响应特性,降低了功耗.对腔形和载流子注入/抽取结构的研究可以进一步改善绝热微环谐振腔的性能,推动低能耗器件研究的发展.     

Modeling and design of a DFB laser integrated with a Mach-Zehndermodulator

A comprehensive model for a complex-coupled distributed feedback laser diode monolithically integrated with a Mach-Zehnder modulator is developed and validated by comparison with experimental data. Methods and their tradeoffs for reduction of adiabatic frequency chirp due to the parasitic reflections from the modulator are discussed     

Full-Wave Analysis and Design of Dielectric-Loaded Waveguide Filters Using a State-Space Integral-Equation Method

A full-wave analysis method for waveguide filters based on dielectric loaded resonators is proposed in this work. For such purpose, a state-space integral-equation formulation has been developed, and the efficient numerical evaluation of all matrices and singular integrals related to the method has been detailed. The novel technique has been first validated through the accurate analysis of a dielectric loaded rectangular cavity, and a simple stopband structure based on such basic building block. Then, making use of a computer-aided design tool, a four-pole bandpass filter based on dielectric loaded resonators has been efficiently designed. The accuracy of the proposed method has been validated through successful comparisons with data from technical literature and available commercial software.     

QSERL: quasi-static energy recovery logic

A new quasi-static energy recovery logic family (QSERL) using the principle of adiabatic switching is proposed in this paper. Most of the previously proposed adiabatic logic styles are dynamic and require complex clocking schemes. The proposed QSERL uses two complementary sinusoidal supply clocks and resembles the behavior of static CMOS. Thus, switching activity is significantly lower than dynamic logic. In addition, QSERL circuits can be directly derived from static CMOS circuits. A high-efficiency clock generation circuitry, which generates two complementary sinusoidal clocks compatible to QSERL, is also presented in this paper. The adiabatic clock circuitry locks the frequency of clock signals, which makes it possible to integrate adiabatic modules into a VLSI system. We have designed an 8×8 carry-save multiplier using QSERL logic and two phase sinusoidal clocks. SPICE simulation shows that the QSERL multiplier can save 34% of energy over static CMOS multiplier at 100 MHz     

Multilayer ceramic capacitor with ultra-low ESL for high-frequency decoupling applications

A novel multilayer ceramic capacitor is proposed using vertically oriented internal electrodes. Because this distinctive internal electrode configuration effectively reduces the current loop area in the device, the proposed capacitor provides ultra-low equivalent series inductance of 47.0 pH on average from a series resonant frequency to 3.0 GHz despite its relatively simple terminal structure. This excellent behaviour is both numerically and experimentally validated.     

三值低功耗多米诺JKL触发器设计及应用

通过对三值触发器和绝热多米诺电路的研究,提出一种新颖低功耗多米诺JKL触发器开关级设计方案。该方案首先利用开关—信号理论,根据三值JKL触发器真值表,推导出三值绝热多米诺JKL触发器开关级结构式;然后利用三值JKL触发器实现三值正循环门电路和三值反循环门电路的设计;最后,经Spice软件模拟证明所设计的三值绝热多米诺JKL触发器逻辑功能正确,与常规三值多米诺JKL触发器相比,能耗节省约69%。     

应用于显示器件的动态肤色校正方法

基于输入图像中需要调整的肤色区域动态地移向特征肤色区域的图像动态肤色校正方法,提出了一种适用于显示器件中硬件实现的动态肤色校正简化模型,进而设计实现了实时动态肤色校正电路,并将其应用于100 cm彩色交流等离子体显示器(AC PDP)中进行验证。仿真及实验结果表明,本文提出的实时动态肤色校正方法能够使得校正后的输出图像中皮肤颜色显得更加自然生动,更趋近于人们对肤色的先验理解,从而有效地提高了AC PDP的彩色再现能力。     

Proposed Nonlinear Microring Resonator Arrangement for Stopping and Storing Light

A simple system of an all-optical system for stopping and storing is proposed. A system consists of two microring and a nanoring resonators that can be integrated into a single system. The large bandwidth is generated by a soliton pulse within a Kerr-type nonlinear medium where an all-optical adiabatic and pulse bandwidth compression can be performed. The balance between the dispersion and nonlinear lengths of the soliton pulse exhibits the soliton behavior known as self-phase modulation, which produces a constant optical output. This means that light pulse can be trapped, i.e., stopped optically within the nanowaveguide.