TLM method for thermal investigation of IGBT modules in PWM mode

The insulated gate bipolar transistor (IGBT) is popularly used in high power, high frequency power-electronic applications such as motor control and inverters. These applications require well designed thermal management system to ensure the protection of IGBTs. Choice simulation tools for accurate prediction of device power dissipation and junction temperature become important in achieving optimised designs.In this paper, thermal analysis of a 1200 A, 3.3 kV IGBT module was investigated and analysed using the three-dimensional transmission line matrix (3D-TLM) method. The results show a three-dimensional visualisation of self-heating phenomena in the device. Since the comparison TLM results with the analytical solutions do not exist for this IGBT module, we use the MSC.NASTRAN tool to find the similar range of the temperatures. Results are compared.Typically, IGBT is used in a three-phase inverter leg where the control signals are generated via PWM scheme so, the prediction of the temperature rise is important in the pulse operation conditions for the IGBT device. A view of the dynamic thermal temperature rise is obtained with 100 W-step pulse dissipation applied at IGBT chips. The temperature rises are calculated using TLM method during the PWM load cycles. Simulations give clear indications of the importance of the spreader material and are helpful in selecting the proper one.TLM has been successful in modelling heat diffusion problems and has proven to be efficient in terms of stability and complex geometry. The three-dimensional results show that method has a considerable potential in power devices thermal analysis and design.     

A thermal, mechanical, and electrical study of voiding in the solder die-attach of power MOSFETs

Large area die-attach defects have been shown to increase the thermal impedance of power semiconductor devices. The changes in thermal performance are simulated and measured in the silicon die using one-, two-, and three-dimensional methods. Experimental measurements for devices with various levels of die-attach void growth are presented. This data is then correlated with finite element thermal modeling to improve the estimate of peak die temperature for voided semiconductor devices. The results present a complete understanding of the heat flow within the voided semiconductor package with an estimate of its impact on performance over its lifetime.     

A field theoretical comparison of FDTD and TLM

A field theoretical derivation of the three-dimensional TLM method with expanded node and of the three-dimensional TLM method with asymmetrical condensed node is given. In the derivation, the Method of Moments is applied to Maxwell's equations. The wave amplitudes are related to the tangential field components at the boundaries of the TLM cell. The same approach is applied to derive the FDTD method from Maxwell's equations. A complete dispersion analysis is given for the two TLM methods as well as for the FDTD method     

A simple metal-semiconductor substructure for the advanced thermo-mechanical numerical modeling of the power integrated circuits

The metallization of double-diffused metal-oxide semiconductor (DMOS) power devices, which operate under fast thermal cycling (FTC), undergoes thermal induced plastic metal deformation (TPMD). The design of the metallization has a significant impact on the device lifetime and thus requires a thorough understanding of the temperature, stress and strain distribution. A simple three-dimensional (3D) transistor substructure which is commonly found in various high integration Bipolar-CMOS-DMOS (BCD) technologies is analysed. The thermomechanical behaviour is studied with the finite element method (FEM) for investigation of two potential failure mechanisms: delamination of power metal and accumulation of plastic deformation in signal metallization layer (which leads to inter-metal dielectric cracking). These failure mechanisms are analysed on two versions of the structure: the first one has only signal and power metal lines and the second one has vias, in addition to the signal and power metal lines. The target of the paper is to propose an efficient finite element analysis (FEA) model that can be used for a qualitative assessment of thermo-mechanical phenomena in the metal system of high integration BCD technologies.     

MSM光电探测器电磁场特性的 TLM方法模拟

介绍了利用传输线矩阵方法模拟和分析金属－半导体－金属光电探测器的指栅电容的频率响应。应用时域电磁场三维TLM方法模拟分析了指栅间距和指栅间的耦合长度与光电探测器截止频率的关系。文中报道了本项研究所开发的三维电磁场时域模拟器TLM Simulator2.0及其功能。数值实验结果说明模拟器对微波结构的电磁场模拟是精确、有效的,具有很好的应用价值。     

Electrothermal modelling of GaAs MESFETs

In this paper a new analytic electrothermal model of a GaAs FET is proposed in order to evaluate the thermal field in the semiconductor body for an easy, fast and reliable layout design using a personal computer. The contribution to the thermal resistance of all the top and bottom layers of a typical chip and the interaction of the channel temperature with the drain current are taken into account. A comparison with a three-dimensional finite-difference simulator and experimental data confirms the accuracy of the model. The CAD tool in which the mathematical model has been implemented can be used for the layout design since it is able to calculate the optimal spacing between contiguous devices to minimize the mutual thermal coupling and also the optimal number of gate fingers and gate-to-gate spacing of a single power device with a multigate layout. The proposed technique is general and can be applied to silicon as well as to heterojunction FET devices.     

A three dimensional semiconductor device simulator for GaAs/AlGaAsheterojunction bipolar transistor analysis

A three-dimensional semiconductor device simulator was developed to study the steady-state characteristics of heterostructure compound semiconductor devices. The semiconductor partial differential equations-Poisson's equation and the two carrier transport equations-are solved using finite-difference discretization. The Gummel iteration method and indirect space matrix solution techniques are utilized for minimizing computation time and memory requirements. This simulator was applied to the analysis of heterojunction bipolar transistors. The effect of emitter grading on the current-voltage characteristic is demonstrated. A comparison between two- and three-dimensional simulations is also presented. The results show that three-dimensional analysis is indispensable, in particular for devices of small geometry     

Effective thermal conductivity of porous solder layers

Microscopic voids in the die attachment solder layers of power semiconductor devices degrade their overall thermal transfer performance. This paper presents analytical results of the effect of spherical and spheroidal void geometries on the thermal conductivity of bulk media. Analytical results are compared with axially symmetric and three-dimensional thermal simulations of single and multiple cavity defects in planar structures. The effective thermal conductivity of the die to the case attachment solder layer of two commercial metal oxide semiconductor field effect transistor (MOSFET) devices is estimated using these results, with cavity dimensions and distributions obtained by electron microscopy.     

Single-shot thermal energy mapping of semiconductor devices with the nanosecond resolution using holographic interferometry

A novel two-dimensional backside optical imaging method for thermal energy mapping inside semiconductor devices is presented. The method is based on holographic interferometry from the device backside and uses the thermo-optical effect. An image of the local thermal energy is obtained with 5-ns time resolution using a single stress pulse. The technique allows a unique recording of the internal device behavior. The method is demonstrated analyzing the nonrepetitive thermal and current flow dynamics in smart power electrostatic discharge (ESD) protection devices. A spreading of the current during the stress pulse is observed and explained by the effect of the negative temperature dependence of the impact ionization coefficient.     

Transmission-line-matrix (TLM) modeling of self-heating in AlGaN/GaN transistor structures

Self-heating in AlGaN/GaN (GaN—gallium nitride) heterostructures is an important issue for a large use of these devices in high-density power telecommunication applications. The equation of heat associated with this type of problem does not admit an analytical solution. Hence, we propose a numerical solution based on the use of a transmission line matrix (TLM). The method is easy to program and gives insights on temperature distribution throughout the device. It allows a better understanding of heat behavior and management at each layer that forms the structure. Some TLM simulation results have been compared with those obtained experimentally using integrated micro-Raman/infrared (IR) thermography methods, and have been found to agree within the bounds set by the resolution of the meshes used. The TLM has also the advantage upon other numerical methods of being unconditionally stable, one step and can adapt to complex geometries such as devices with several fingers.     

Simulating the dynamic electrothermal behavior of power electroniccircuits and systems

The simulator solves for the temperature distribution within the semiconductor devices, packages, and heat sinks (thermal network) as well as the currents and voltages within the electrical network. The thermal network is coupled to the electrical network through the electrothermal models for the semiconductor devices. The electrothermal semiconductor device models calculate the electrical characteristics based on the instantaneous value of the device silicon chip surface temperature and calculate the instantaneous power dissipated as heat within the device. The thermal network describes the flow of heat from the chip surface through the package and heat sink and thus determines the evolution of the chip surface temperature used by the semiconductor device models. The thermal component models for the device silicon chip, packages, and heat sinks are developed by discretizing the nonlinear heat diffusion equation and are represented in component form so that the thermal component models for various packages and heat sinks can be readily connected to one another to form the thermal network     

Mechanical Deformation of Sintered Porous Ag Die Attach at High Temperature and Its Size Effect for Wide-Bandgap Power Device Design

The mechanical properties of sintered Ag paste with microporous structure have been investigated by tensile and shear tests, focusing on the temperature-dependent plastic deformation at various temperatures from 25°C to 300°C, corresponding to the target operating temperature range of emerging wide-bandgap semiconductor devices. Specimens were prepared by sintering hybrid Ag paste consisting of microflake and submicron spherical Ag particles, simulating a typical bonding process for power semiconductor die attach. Mechanical tests revealed that the unique microstructure caused a brittle-to-ductile transition at temperature of around 160°C, remarkably lower than that of bulk Ag. The obtained Young’s modulus and shear modulus values indicate obvious softening with increasing temperature, together with a remarkable decrease in Poisson’s ratio. These plastic behaviors at elevated temperature can be explained based on Coble creep in the microporous network structure. Fracture surfaces after tensile and shear tests indicated unique features on scanning electron microscopy, reflecting the variation in the ductile behavior with the test temperature. Furthermore, these temperature-dependent mechanical parameters were employed in three-dimensional finite-element analysis of the thermomechanical stress distribution in wide-bandgap semiconductor module structures including Ag paste die attach of different sizes. Detailed thermal stress analysis enabled precise evaluation of the packaging design for wide-bandgap semiconductor modules for use in high-temperature applications.     

Full-wave analysis of photonic bandgap integrated optical components by the TLM-IE method

This paper presents the full-wave analysis of commonly encountered optical periodic structures by the novel transmission-line matrix/integral equation (TLM-IE) method. The TLM-IE is a three-dimensional full-wave hybrid technique that combines the advantages of the numerical TLM method in dense finite regions and those of the IE method in open regions where simple Green functions are available. The pre- and postprocessing tools of the TLM-IE solver provide visualization and physical insight into the dynamics of electromagnetic propagation in such devices. The aim of this effort is twofold: 1) to analyze the diffraction and reflection characteristics of photonic bandgap gratings and 2) to define optimization guidelines for the Q factor of integrated dielectric resonators.     

半导体功率发光二极管温升和热阻的测量及研究

通过电学测量方法得到了半导体功率发光二极管温升与热阻的加热响应曲线.曲线出现一个或多个台阶,反映了其内部的热阻构成与器件物理结构.同时采用遮光法对器件温升及热阻进行了修正.还应用瞬态加热响应原理对功率管的封装结构进行了监测.     

Application of the TLM method to transient thermal simulation ofmicrowave power transistors

The transmission line matrix (TLM) explicit method of numerical simulation has been used to model the transient thermal properties of various microwave heterojunction bipolar transistor (HBT's) power structures, used in a pulsed mode. Control of the time step during the simulation is of paramount importance and the paper outlines some of the problems encountered using time step control methods currently published and describes an improved algorithm. This improved time step control method has been implemented in a general purpose 3D TLM transient thermal simulator. Some simulation results are described for a variety HBT transistor structures with very different thermal time constants     

Thermal characterization of planar high temperature power module packages with sintered nanosilver interconnection

Many new innovations have emerged in the power electronics industry to aid in meeting the expanded market demand. In spite of that the interest in high temperature and high power applications has fueled new developments in wide bandgap semiconductor devices which are capable of operation above 200 °C, silicon devices are still prevalent in the marketplace and offer significant power ratings at affordable prices. Researches have kept pushing the limit of the application temperature of silicon devices. The key to offering functional and reliable silicon packages that can endure higher temperatures is through innovative thermal management and packaging. Effective thermal management of packaged devices can be accomplished through materials selection, design or a combination of the two. In this paper, we outline a newly designed packaging structure and the fabrication process of a functional double-sided power module switching units utilizing LTJT sintered silver for each interface. The thermal characteristics of the power module were measured in various cooling scenarios utilizing thermal transient measurements, structure function analysis and the transient dual interface method (TDIM), techniques developed by Mentor Graphics. Significant improvement of thermal performance of the fabricated module was demonstrated. The resulting improvements in thermal resistance of the power module, thermal simulation model agreement and construction, and comparison of double sided thermal results to single sided conventions are discussed.     

关于半导体器件热特性表征和控制技术的研究

根据对器件散热特性的分析,提出用特定脉宽的瞬态热阻抗表征器件的稳态散热特性.测量了特定器件热阻与温度的依赖关系,建议在实际工作中注意器件热阻并不为常数的客观事实.提出应力试验前后测量器件热阻可有效控制器件的某些制造缺陷.     

高功率微波效应的多物理场建模方法研究

为了实现对微波器件高功率微波效应的分析,主要从不同尺度半导体器件和波导器件出发,基于具有谱精度的谱元时域法,开展从微米尺度到纳米尺度半导体器件电热耦合一体化分析的方法以及高功率微波气体放电效应及抑制机理的研究.得到了半导体器件在电磁信号作用下发生的电热参数分布变化规律和微波器件在高功率微波下发生的气体放电及其抑制机理,根据以上相关效应机理,可为复杂电磁环境中的器件设计提供理论指导.     

压接式GCT封装的热特性分析

电力半导体器件的散热性能和热可靠性与其封装结构密切相关,选择合适的封装结构对改善器件的散热性能和提高热可靠性非常重要。文中根据压接式GCT器件封装结构特点,采用ANSYS软件利用有限元法分析了单芯片封装和多芯片封装结构的温度及热机械应力分布,并与常规的焊接式封装进行了对比。结果表明,压接式封装结构的散热效果比焊接式封装结构稍差,但其芯片上产生的热机械应力明显减小。多芯片封装采用常规的风冷散热器时芯片温度已经超过了器件的安全工作温度(125℃),应该采用热管散热器才能保证器件可靠地工作。