IDDQ测试技术及其实现方法

ＩＤＤＱ测试是近几年来国外比较流行的ＣＭＳＯ集成电路测试技术。ＩＤＤＱ测试能够２检测出传统的固定值故障电压测试所无法检测的ＣＭＯＳ集成电路内部的缺陷、所以,能够明显提高ＣＭＯＳ集成电路的使用可靠性。本文叙述了ＩＤＤＱ测试的基本原理和ＩＤＤＱ测试在集成电路测试系统上的实现方法及测试实例。     

自对准硅化物CMOS／SOI技术研究

在ＣＭＯＳ／ＳＩＭＯＸＳＯＩ电路制作中引入了自对准钴（Ｃｏ）硅化物（ＳＡＬＩＣＩＤＥ）技术，研究了ＳＡＬＩＣＩＤＥ工艺对ＳＯＩＭＯＳＦＥＴ单管特性和ＣＭＯＳ／ＳＯＩ电路速度性能的影响．实验表明，采用ＳＡＬＩＣＩＤＥ技术能有效地减小ＭＯＳＦＥＴ栅、源、漏电极的寄生接触电阻和方块电阻，改善单管的输出特性，降低ＣＭＯＳ／ＳＯＩ环振电路门延迟时间，提高ＣＭＯＳ／ＳＯＩ电路的速度特性．     

自对准硅化物SOI／CMOS技术研究

在ＳＯＩ／ＣＭＯＳ电路制作中引入了自对准钴硅化物（ＳＡＬＩＣＩＤＥ）技术，研究了ＳＡＬＩＣＩＤＥ工艺对ＳＯＩ／ＭＯＳＦＥＴ单管特性和ＳＯＩ／ＣＭＯＳ电路速度性能的影响。实验表明，ＳＡＬＩＣＩＤＥ技术能有效地减小ＭＯＳＦＥＴ栅、源、漏电极的寄生接触电阻和薄层电阻，改善单管的输出特性，降低ＳＯＩ／ＣＭＯＳ环振电路门延迟时间，提高ＳＯＩ／ＣＭＯＳ电路的速度特性。     

CMOS电路芯片ESD保护电路设计技术的发展

本文简要地回顾了ＣＭＯＳ电路芯片上ＥＳＤ保护电路设计技术发展概况，给出了在中小规模、大规模及超大规模各阶段的ＣＭＯＳ电路芯片上ＥＳＤ保护电路的主流技术，双寄生的ＳＣＲ结构ＶＬＳＩ ＣＭＯＳ芯片上ＥＳＤ保护电路的最新设计技术，就其ＥＳＤ保护原理、设计技术及取得的成果做了较详细分析和探讨。对于研制高密度、高速度的ＶＬＳＩ ＣＭＯＳ电路。开展高ＥＳＤ失效阈值电压，小几何尺寸及低ＲＣ延迟时间常数保护电路的     

掺HCI栅氧化对MOS结构电特性的影响

研究了栅氧化时掺ＨＣｌ的硅栅ＭＯＳＦＥＴ的ＤＤＳ－ＶＧＳ特性，阈电压和界面态。结果发现，ＨＣｌ掺入栅介质，可使ＩＤＳ－ＶＧＳ曲线正向漂移，ＰＭＯＳＦＥＴ阈电压绝对值减小，ＮＭＯＳＦＥＴ阈电压增大，Ｓｉ／ＳｉＯ２界面态密度下降，采用氯的负电中心和Ｓｉ／ＳｉＯ２界面硅悬挂键的键合模型对实验结果进行了解释。     

掺HCl栅氧化对MOS结构电特性的影响

研究了栅氧化时掺ＨＣｌ的硅栅ＭＯＳＦＥＴ的ＤＤＳ－ＶＧＳ特性、阈电压和界面态．结果发现，ＨＣｌ掺入栅介质，可使ＩＤＳ－ＶＧＳ曲线正向漂移，ＰＭＯＳＦＥＴ阈电压绝对值减小，ＮＭＯＳＦＥＴ阈电压增大，Ｓｉ／ＳｉＯ２界面态密度下降。采用氯的负电中心和Ｓｉ／ＳｉＯ２界面硅悬挂键的键合模型对实验结果进行了解释。     

接口电路LN4993失效机理分析

通过对接口电路ＬＮ４９９３几次现场失效及厂家筛选中失效电路的分析，并做了ＥＳＤ试验模拟试验，总结出ＬＮ４９９３几种失效模式，探讨其失效机理，发现这种ＭＮＯＳ电路ＥＳＤ损伤阈值为１５００Ｖ，电路失效多数是过电应力或静电损伤造成。     

自对准Ti－SALICIDE LDD MOS工艺研究

本文着重研究了０．６μｍ自对准Ｔｉ－ＳＡＬＩＣＩＤＥＬＤＤＭＯＳ工艺技术．ＴｉＳｉ２的形成采用两步快速热退火及选择腐蚀完成，Ｔｉ膜厚度的最佳选择使ＳＡＬＩＣＩＤＥ工艺与０．２μｍ浅结相容，源／漏薄层电阻为４Ω／□．上述技术已成功地应用于０．６μｍ自对准Ｔｉ－ＳＡＬＩＣＩＤＥＬＤＤＮＭＯＳ器件及其Ｅ／ＤＭＯＳ３１级环形振荡器的研制，特性良好．     

光波分复用技术讲座 第六讲 WDM环网技术和光联网发展

现在的ＷＤＭ光网络的演进与ＳＤＨ网络非常相似。从网络组成上看,ＳＤＨ有ＴＭ、ＡＤＭ、ＤＸＣ等几种网元,网络拓扑经过了点到点、自愈环和基于ＤＸＣ网状网的几个发展阶段。ＷＤＭ光网络也与此类似,有背对背ＷＤＭ终端、ＯＡＤＭ、ＯＸＣ等几种网元,在网络拓扑上也要经过点到点线性系统、ＷＤＭ自愈环和基于ＯＸＣ网状网的几个发展阶段。与ＳＤＨ网络相比,ＷＤＭ光网络容量更大,对业务透明,保护速度更快,如表１所示。ＷＤＭ光联网的演进由最初的线性点到点式传送结构,逐步转变为环型结构、网型结构。当前,ＯＡＤＭ的应用日趋增…     

MSCDEX的使用

ＭＳＣＤＥＸ的使用邵振付计算机对ＣＤ－ＲＯＭ驱动器的识别与操作同ＣＤ－ＲＯＭ驱动器的配置有关，这就是ＭＳＣＤＥＸ和ＣＤ－ＲＯＭ驱动程序的共同任务，下面作一简单介绍。ＭＳＣＤＥＸ命令提供ＣＤ－ＲＯＭ驱动器的配置、安装功能，可通过ＡＵＴＯＥＸＥＣ．ＢＡＴ...     

Delay and power monitoring schemes for minimizing power consumption by means of supply and threshold voltage control in active and standby modes

This paper describes newly developed delay and power monitoring schemes for minimizing power consumption by means of the dynamic control of supply voltage V/sub DD/ and threshold voltage V/sub TH/ in active and standby modes. In the active mode, on the basis of delay monitoring results, either VDD control or VTH control is selected to avoid any oscillation problem between them. In V/sub DD/ control, on the basis of delay monitoring results, VDD is adjusted so as to be maintained at the minimum value at which the chip is able to operate for a given clock frequency. In V/sub TH/ control, on the basis of power monitoring results, VTH is adjusted so as to maintain a certain switching current I/sub SW//leakage current I/sub LEAK/ ratio known to indicate minimum power consumption. In the standby mode, the precision of power monitoring (which detects optimum body bias by comparing subthreshold current I/sub SUBTH/ to substrate current I/sub SUB/) is improved by taking into consideration both the effects of lowering V/sub DD/ and the effects of the presence of gate-oxide leakage current. Experimental results with a 90-nm CMOS device indicate that use of the proposed power monitoring results in the successful minimizing of power consumption. It does so by making it possible to: 1) maintain the I/sub SW//ILEAK ratio in the active mode and 2) detect optimum body bias conditions (I/sub SUBTH/=ISUB) within an error of less than 20% with respect to actual minimum leakage current values in the standby mode.     

Metrics for performance benchmarking of nanoscale Si and carbon nanotube FETs including device nonidealities

This paper proposes a simple and accurate expression for inverter effective drive current for nanoscale Si and carbon nanotube FET (CNFET) performance benchmarking. The choice of I/sub eff/=(I/sub NL/+I/sub NM/+I/sub NH/-I/sub P/)/3, where I/sub NL/=I/sub DS(N-FET)/ (V/sub GS/=0.5V/sub DD/, V/sub DS/=V/sub DD/), I/sub NM/=I/sub DS(N-FET)/(V/sub GS/=0.75V/sub DD/, V/sub DS/=0.75V/sub DD/), I/sub NH/=I/sub DS(N-FET)/ (V/sub GS/=V/sub DD/, V/sub DS/=0.5V/sub DD/), and I/sub P/=I/sub SD(P-FET)/ (V/sub SG/=0.25V/sub DD/, V/sub SD/=0.25V/sub DD/), includes the effects of both the nFET and the pFET of an inverter and accurately captures the inverter delay performance over many CMOS technology nodes and in the presence of device nonidealities. The proposed metric indicates that the performance enhancement of CNFETs over Si MOSFETs is not as large as that predicted by I/sub Dsat/ in a circuit environment because of the nonideal I-V characteristics.     

用于百万像素级CMOS图像传感器的10位50MS/s流水线ADC设计

噪声和不匹配是流水线ADC中的重要误差源,采用Matlab软件对它们进行了计算和系统仿真.为了在没有降低表现的情况下控制功耗,采用了相同结构放大器共用相同的偏置电路技术,并且采用了共源共栅补偿技术来降低功耗.还设计并且测试了一个可用于大像素规模CMOS图像传感器系统的10位50MS/s流水线ADC原型.根据测试结果,当采样频率为50MHz时功耗仅为42mW,SINAD为45.69dB.设计在表现和功耗上取得了很好的平衡.     

一种高效单相电源Ⅰ类线性音频功放的设计

采用SMIC0.18μm3.3V CMOS工艺,实现了单相电源Ⅰ类线性音频功放的设计。为了提高AB类功放的效率,设计了一种新型结构的Ⅰ类线性音频功放,并理论推导了它的效率。Ⅰ类音频放大器中的电源转换器能根据输入音频信号连续调节AB类功放的功率电源电压以减小功率管上的压降。为了使单相电源下PMOS和NMOS功率管功耗同时得到优化,设计了增益变化的信号处理电路。输出级采用桥式结构,并由三级运放构成以提高线性度。测试结果表明,该功放向8Ω阻性负载提供功率在小于270mW范围内时,总谐波失真与噪声之和小于0.45%,最大效率达到70%;功率在100mW范围内时,效率比AB类提高了一倍,且测试效率曲线与理论推导吻合。     

A 5.7-GHz 0.18-/spl mu/m CMOS gain-controlled differential LNA with current reuse for WLAN receiver

This letter presents a 5.7 GHz 0.18 /spl mu/m CMOS gain-controlled differential LNA for an IEEE 802.11a WLAN application. The differential LNA, fabricated with the 0.18 /spl mu/m 1P6M standard CMOS process, uses a current-reuse technology to increase linear gain and save power consumption. The circuit measurement is performed using an FR-4 PCB test fixture. The LNA exhibits a noise figure of 3.7 dB, linear gain of 12.5 dB, P/sub 1dB/ of -11 dBm, and gain tuning range of 6.9 dB. The power consumption is 14.4 mW at V/sub DD/=1.8 V.     

Fully Integrated CMOS Power Amplifier With Efficiency Enhancement at Power Back-Off

This paper presents a new approach for power amplifier design using deep submicron CMOS technologies. A transformer based voltage combiner is proposed to combine power generated from several low-voltage CMOS amplifiers. Unlike other voltage combining transformers, the architecture presented in this paper provides greater flexibility to access and control the individual amplifiers in a voltage combined amplifier. In this work, this voltage combining transformer has been utilized to control output power and improve average efficiency at power back-off. This technique does not degrade instantaneous efficiency at peak power and maintains voltage gain with power back-off. A 1.2 V, 2.4 GHz fully integrated CMOS power amplifier prototype was implemented with thin-oxide transistors in a 0.13 mum RF-CMOS process to demonstrate the concept. Neither off-chip components nor bondwires are used for output matching. The power amplifier transmits 24 dBm power with 25% drain efficiency at 1 dB compression point. When driven into saturation, it transmits 27 dBm peak power with 32% drain efficiency. At power back-off, efficiency is greatly improved in the prototype which employs average efficiency enhancement circuitry.     

A speaker driver for a single phase supply class G & I

A speaker driver applied to class G/classⅠwith a single phase power supply is presented.Gain expanding and compressing technology are employed in the signal processing circuit to optimize power dissipation.The circuit is implemented in 0.18μm N-well CMOS.Experimental results show that the speaker driver has a good audio sound quality and power efficiency.Less than 0.006%THD at a low power range and less than 0.4%at a medium power range can be obtained with a 1 kHz sine wave signal.Maximum output power of 360 mW can be gained at a load of 8Ω.The power efficiency is about twice that of a traditional class AB driver at the power range of 80 mW and shows more than 18%improvement at the higher output power range.     

Characterization of 1.9- and 1.4-nm ultrathin gate oxynitride by oxidation of nitrogen-implanted silicon substrate

For gate oxide thinned down to 1.9 and 1.4 nm, conventional methods of incorporating nitrogen (N) in the gate oxide might become insufficient in stopping boron penetration and obtaining lower tunneling leakage. In this paper, oxynitride gate dielectric grown by oxidation of N-implanted silicon substrate has been studied. The characteristics of ultrathin gate oxynitride with equivalent oxide thickness (EOT) of 1.9 and 1.4 nm grown by this method were analyzed with MOS capacitors under the accumulation conditions and compared with pure gate oxide and gate oxide nitrided by N/sub 2/O annealing. EOT of 1.9- and 1.4-nm oxynitride gate dielectrics grown by this method have strong boron penetration resistance, and reduce gate tunneling leakage current remarkably. High-performance 36-nm gate length CMOS devices and CMOS 32 frequency dividers embedded with 57-stage/201-stage CMOS ring oscillator, respectively, have been fabricated successfully, where the EOT of gate oxynitride grown by this method is 1.4 nm. At power supply voltage V/sub DD/ of 1.5 V drive current Ion of 802 /spl mu/A//spl mu/m for NMOS and -487 /spl mu/A//spl mu/m for PMOS are achieved at off-state leakage I/sub off/ of 3.5 nA//spl mu/m for NMOS and -3.0 nA//spl mu/m for PMOS.     

Power-Combining Transformer Techniques for Fully-Integrated CMOS Power Amplifiers

Fully integrated CMOS power amplifiers (PAs) with parallel power-combining transformer are presented. For the high power CMOS PA design, two types of transformers, series-combining and parallel-combining, are fully analyzed and compared in detail to show the parasitic resistance and the turn ratio as the limiting factor of power combining. Based on the analysis, two kinds of parallel-combining transformers, a two-primary with a 1:2 turn ratio and a three-primary with a 1:2 turn ratio, are incorporated into the design of fully-integrated CMOS PAs in a standard 0.18-mum CMOS process. The PA with a two-primary transformer delivers 31.2 dBm of output power with 41% of power-added efficiency (PAE), and the PA with a three-primary transformer achieves 32 dBm of output power with 30% of PAE at 1.8 GHz with a 3.3-V power supply.     

Half-V/SUB DD/ bit-line sensing scheme in CMOS DRAMs

A sensing scheme in which the bit line is precharged to half V/SUB DD/ is introduced for CMOS DRAMs. The proposed circuitry uses a PMOS memory array and incorporates the following features: (1) a complementary sense amplifier consisting of NMOS and PMOS cross-coupled pairs; (2) clocked pulldown of the latching node; (3) complementary clocking of the PMOS pullup; (4) full-sized dummy cell generation of reference potential for sensing; (5) shorting transistor to equalize precharge potential of bit lines; and (6) depletion NMOS decoupling transistors for multiplexing bit lines. The study shows that the half-V/SUB DD/ bit-line sensing scheme has several unique advantages, especially for high-performance high-density CMOS DRAMs, which compared to the full-V/SUB DD/ bit-line sensing scheme used for NMOS memory arrays or the grounded bit-line sensing scheme for PMOS arrays in CMOS DRAMs.