部分K值逻辑函数中准完备集之最小覆盖的一些结果

多值逻辑是计算机科学与技术的一个重要分支。目前的计算机结构和计算机程序大多基于二值逻辑，但由于多值逻辑有着许多独特的功能和广阔的应用前景，随着计算机科学与技术的不断进步，多值逻辑得到了前所未有的发展。     

多值逻辑网络的输出跟踪牵制控制

本文利用代数状态空间方法,研究了多值逻辑控制网络的输出跟踪牵制控制.首先利用矩阵的半张量积给出了带牵制控制的多值逻辑控制网络的代数表示.其次基于该代数表示,定义了一组合适的能达集,并建立了多值逻辑控制网络输出跟踪牵制控制器的设计方法.再次,利用多值逻辑哑算子的性质,给出了多值逻辑控制网络分布式输出跟踪控制问题可解的充要条件.最后将所得的理论结果应用于网络演化博弈的演化行为分析.     

多值逻辑与范布尔代数

多值逻辑的广泛应用,越来越引起人们的关注。本文提出在满足良序关系的多值逻辑系统中,用二值范布尔代数表示多值逻辑变量分量系数的方法,该方法使用二值逻辑运算来处理多值逻辑问题,在多元多值的情况下,亦能方便地借助计算机进行辅助设计与分析。     

多值逻辑量子置换门的酉矩阵表示

理论上量子可逆电路不存在能量耗散问题,因此量子计算系统对环境产生的负面影响可以达到最低.多值逻辑量子置换门是构建多值逻辑量子电路的基本单元.该文从数学的角度研究多值逻辑量子置换门的酉矩阵,提出了一种构造多值逻辑量子置换门酉矩阵的方法,并对其正确性进行了讨论.在此基础之上,又给出了构造混合多值逻辑量子置换门酉矩阵的框架,利用此框架可以方便地构造任何混合逻辑量子置换门的酉矩阵.酉矩阵是量子门的数学模型,可以清晰地反映出量子门的数学性质.研究量子门的酉矩阵对验证量子门的正确性和可靠性,分析量子状态在电路中的演化过程及发展趋势具有一定的意义.     

关于部分多值逻辑函数集中准完备集的若干性质

Sheffer函数的最简判定是多值逻辑函数集完备性判定问题中的一个重要的理论和实际问题.文中根据多值逻辑函数理论中“保关系”的系统思想,使用群论和组合数学的工具,研究了部分多值逻辑函数集中准完备类相应关系的若干性质.给出并证明了非空关系Gm是完全关系以及子群H是Gm的对称群的充要条件,定出了部分k值逻辑中完满对称函数类Fs,m中函数集的个数.以上工作为解决部分多值逻辑中Sheffer函数的判定提供了研究基础.     

关系数据库中信息空缺与多值逻辑的研究

研究了信息空缺问题中的多值逻辑，并讨论了多值逻辑对逻辑代数、关系数据库的影响以及SQL对多值逻辑的支持。     

部分多值逻辑函数集中准完备集的分类问题研究

Sheffer函数的最简判定是多值逻辑函数集完备性判定问题中的一个重要的理论和实际问题。根据部分多值逻辑函数的完备性理论,研究了部分多值逻辑函数集中准完备集的分类问题,从而为解决部分多值逻辑中Sheffer函数的判定问题提供了研究基础。     

混合数系统全并行乘法算法及其实现

本文应用多值逻辑理论研究高速乘法,提出了普通二进制和对称二进制冗余数的混合数系统的全并行乘法算法以及实现它的三值ECL(3V-ECL)线路.所设计的阵列乘法器具有速度高、结构简单和工艺性好的特点.因此,很适合制作LSI.用于计算机中,与普通的乘法器一样.     

多值逻辑函数发生器的优化设计方法

将二值逻辑系统的设计方法巧妙地溶入了多值逻辑系统的设计当中,找到了实现多值逻辑系统设计的最优方法.并通过典型实例的分析,总结出三点结论,可望促进多值逻辑技术的普及与发展.     

一种实现三值逻辑电路的DNA计算模型

近年来,随着生物计算和量子计算研究的深入,多值逻辑电路的各种实现成为一个热门的研究方向.发夹结构是DNA分子一种特殊杂交方式的产物,具有结果稳定、特异性强的优点.本文首次提出了一种利用DNA分子来实现多值逻辑电路的方法,用DNA分子的多发夹结构来表示三值逻辑的值,并给出"与"运算和"或"运算的计算模型,该模型适合应用于大规模的多值逻辑电路.     

多值DYL可编程逻辑阵列及其复杂性

本文提出一种采多元逻辑电路的多值可编程逻辑阵列。该阵列由输入译码器，二值“或非”“阵列，二值“或”列及输出译码器四部分组成，具有规则的形状和简单的结构，并且易于实现超大规模集成，此外还讨论了该阵列的逻辑设计和结构复杂性。     

TMLNN: triple-valued or multiple-valued logic neural network

We discuss the problem of representing and processing triple-valued or multiple-valued logic knowledge using neural network. A novel neuron model, triple-valued or multiple-valued logic neuron (TMLN), is presented. Each TMLN can represent a triple-valued or multiple-valued logic rule by itself. We will show that there are two TMLNs: TMLN-AND (triple-valued or multiple-valued "logic AND") neuron and TMLN-OR (triple-valued or multiple-valued "logic OR") neuron. Two simplified TMLN models are also presented, and show that a multilayer neural network made up of triple-valued or multiple-valued logic neurons (TMLNN) can implement a triple-valued or multiple-valued logic inference system. The training algorithm for TMLNN is presented and can be shown to converge. In our model, triple-valued or multiple-valued logic rules can be extracted from TMLNN with ease. TMLNN can thus form a base for representing logic knowledge using neural network.     

Toward novel designs of reversible ternary 6:2 Compressor using efficient reversible ternary full-adders

Integrated circuits always face with two major challenges including heat caused by energy losses and the area occupied. In recent years, different strategies have been presented to reduce these two major challenges. The implementations of circuits in a reversible manner as well as the use of multiple-valued logic are among the most successful strategies. Reversible circuits reduce energy loss and ultimately eliminate the problem of overheating in circuits. Preferring multiple-valued logic over binary logic can also greatly reduce area occupied of circuits. When switching from binary logic to multiple-valued logic, the dominant thought in binary logic is the basis of designing computational circuits in multiple-valued logic, and disregards the capabilities of multiple-valued logic. This can cause a minimal use of multiple-valued logic capabilities, increase complexity and delay in the multiple-valued computational circuits. In this paper, we first introduce an efficient reversible ternary half-adder. Afterward, using the reversible ternary half-adder, we introduce two reversible versions of traditional and comprehensive reversible ternary full-adders. Finally, using the introduced reversible ternary full-adders, we propose two novel designs of reversible ternary 6:2 Compressor. The results of the comparisons show that although the proposed circuits are similar to or better than previous corresponding designs in terms of criteria number of constant input and number of garbage outputs, they are superior in criterion quantum cost.

     

Designing new ternary reversible subtractor circuits

The reducing of the width of quantum reversible circuits makes multiple-valued reversible logic a very promising research area. Ternary logic is one of the most popular types of multiple-valued reversible logic, along with the Subtractor, which is among the major components of the ALU of a classical computer and complex hardware. In this paper the authors will be presenting an improved design of a ternary reversible half subtractor circuit. The authors shall compare the improved design with the existing designs and shall highlight the improvements made after which the authors will propose a new ternary reversible full subtractor circuit. Ternary Shift gates and ternary Muthukrishnan–Stroud gates were used to build such newly designed complex circuits and it is believed that the proposed designs can be used in ternary quantum computers. The minimization of the number of constant inputs and garbage outputs, hardware complexity, quantum cost and delay time is an important issue in reversible logic design. In this study a significant improvement as compared to the existing designs has been achieved in as such that with the reduction in the number of ternary shift and Muthukrishnan-Stroud gates used the authors have produced ternary subtractor circuits.     

A Framework for Automated Reasoning in Multiple-Valued Logics

The language of signed formulas offers a first-order classical logic framework for automated reasoning in multiple-valued logics. It is sufficiently general to include both annotated logics and fuzzy operator logics. Signed resolution unifies the two inference rules of annotated logics, thus enabling the development of an SLD-style proof procedure for annotated logic programs. Signed resolution also captures fuzzy resolution. The logic of signed formulas offers a means of adapting most classical inference techniques to multiple-valued logics.     

部分四值逻辑中Sheffer函数的判定

多值逻辑是指一切逻辑值的取值数大于2的逻辑。Sheffer函数的判定问题是多值逻辑完备性理论中的一个重要问题,此问题的解决依赖于定出多值逻辑函数集中所有准完备集的最小覆盖。在深入研究部分四值逻辑中Sheffer函数的基础上,根据部分四值逻辑中准完备集的最小覆盖,给出了一个部分四值逻辑中Sheffer函数的判定算法。此算法能够判定任意一个函数是不是部分四值逻辑中的Sheffer函数。     

Identification of incompletely specified multiple-valued Kleeneanfunctions

This paper focuses on incompletely specified multiple-valued Kleenean functions (1991). It is easy to verify that they do not have functional completeness in the class of all functions on the unit interval. Therefore, not all incompletely specified functions on the unit interval are incompletely specified multiple-valued Kleenean functions. In this paper, we will clarify a necessary and sufficient condition for an incompletely specified function to be an incompletely specified multiple-valued Kleenean function. Further, we show an algorithm which derives one of the logic formulas representing the incompletely specified multiple-valued Kleenean function. In considering the application of multiple-valued Kleenean functions, we will show an example which suggests the possibility that input-output data can be described abstractly in terms of multiple-valued Kleenean functions     

关于部分K值逻辑中的单纯可离函数集性质的一些结果

在多值逻辑函数结构理论中，Sheffer函数的判定与构造是其中的一个重要的组成部分。其判定问题与函数集完备性之判定密切相关，而完备性之判定又可归结为定出其中的所有准完备集。对于部分多值逻辑，其函数集的完备性问题已彻底解决，即定出了其中的所有准完备集(共七类)，但其中的Sheffer函数之判定与构造问题尚未彻底解决。     

A Novel Multiple-Valued CMOS Flip-Flop Employing Multiple-Valued Clock

A new CMOS quaternary D flip-flop is implemented employing a multiple-valued clock. PSpice simulation shows that the proposed flip-flop has correct operation. Compared with traditional multiple-valued flip-flops, the proposed multiple-valued CMOS flip-flop is characterized by improved storage capacity, flexible logic structure and reduced power dissipation.