0．35μm SiGe BiCMOS 3．1～10．6GHz超宽带低噪声放大器

基于AMS 0.35 μm SiGe BiCMOS工艺,设计了一种应用于3.1～10.6 GHz频段的超宽带低噪声放大器;采用多个反馈环路,实现超宽带范围内的阻抗匹配以及低噪声性能;详细分析了匹配电路的特性.在片测试结果表明,在工作频带内,电路增益S21达到14 dB,增益波动小于2 dB;输入回波损耗S11小于-10 dB;噪声系数NF小于3.5 dB.电路采用3 V供电,功耗为30 mW.     

采用0.18 μmCMOS工艺超宽带低噪声放大器的设计

提出了一个采用TSMC 0.18μmCMOS工艺设计的,工作频段为3.1～5.2 GHz的超宽带低噪声放大器.放大器采用了前置带通滤波器的并联负反馈共源共栅结构,并从宽带电路.高频电路器件选择等方面讨论了超宽带低噪声放大器的设计,结果表明,在整个工作频段,电路输入输出匹配S11S22均小于-14 dB,最高增益为15.92 dB,增益波动为1.13 dB,电路工作电压为1.8 V,功耗为27 mW,噪声系数NF为1.84～2.11 dB.     

双频段低噪声放大器的设计

适应多标准移动通信终端的迅速发展,设计了能够在800 MHz和1.8 GHz两个不同频段独立工作的低噪声放大器.放大器使用噪声性能优良的SiGeHBT管子,采用Cascode结构减小Miller电容的影响,发射极串联电感消除放大器输入端噪声系数和功率匹配的耦合,输入匹配电路采用单通道串并联LC电路,计算串并联电感和电容值,可以在两个工作频点发生谐振.输出端通过调整负载阻抗到50Ω,采用简单的电路实现功率输出.ADS的仿真结果表明,本文设计的低噪声放大器在800MHz和1.8 GHz两个工作频段的S21分别达到了24.3 dB和21.3 dB,S11均达到了-13 dB,S22均在-27dB以下,两个频段的噪声系数分别为3.3 dB和2.0 dB.     

低压中和化CMOS差分低噪声放大器设计

以设计低电压LNA电路为目的,提出了一种采用关态MOSFET中和共源放大器输入级栅漏寄生电容Cgd的CMOS差分低噪声放大器结构.基于该技术,采用0.35μmCMOS工艺设计了一种工作在5.8GHz的低噪声放大器.结果表明,在考虑了各种寄生效应的情况下,该低噪声放大器可以在0.75V的电源电压下工作,其功耗仅为2.45mW.在5.8GHz工作频率下:该放大器的噪声系数为2.9dB,正向增益S21为5.8dB,反向隔离度S12为-30dB,S11为-13.5dB.     

CMOS宽带线性可变增益低噪声放大器设计

文章设计了一种48MHz~860MHz宽带线性可变增益低噪声放大器,该放大器采用信号相加式结构电路、控制信号转换电路和电压并联负反馈技术实现。详细分析了线性增益控制、输入宽带匹配和噪声优化方法。采用TSMC0.18μm RF CMOS工艺对电路进行设计,仿真结果表明,对数增益线性变化范围为-5dB~18dB,最小噪声系数为2.9dB,S11和S22小于-10dB,输入1dB压缩点大于-14.5dBm,在1.8V电源电压下,功耗为45mW。     

一种多模式低噪声放大器的设计

基于SMIC 0.18 μm CMOS工艺,采用可重构结构,设计了一种应用于北斗、GPS导航系统接收机的可切换双频段低噪声放大器。采用Cadence Spectre RF仿真器进行仿真和验证。结果表明,在1.2 GHz频段,该放大器的增益为17.6 dB,噪声系数为2.8 dB,S11为-11.1 dB,S22为-11.3 dB;在1.57 GHz频段,该放大器的增益为15.1 dB,噪声系数为2.98 dB,S11为-11.7 dB,S22为-10.6 dB。芯片尺寸仅为1 260 μm×844 μm。在1.8 V供电电压下,直流功耗仅为28.8 mW。     

S 频段pHEMT 双通道低噪声放大器芯片的设计

采用GaAs 0.13μmp HEMT MMIC流片工艺设计和制作了一种S频段双通道低噪声放大器芯片,芯片内部集成了两个低噪声放大器通道、一级单刀双掷(SPDT)开关和一个晶体管-晶体管逻辑(TTL)电平转换电路。低噪声放大器电路采用一级共源共栅场效应管(Cascode FET)结构实现,使其具有比单管更高的增益,简化了芯片拓扑,降低了芯片设计难度。经流片测试,在1.9~2.1GHz的工作频带内,芯片噪声系数优于1.4dB,增益大于22.5dB,输入驻波优于1.8,输出驻波优于1.4,输出1dB压缩点(P1dB)为10dBm。大量芯片样本在片测试统计数据表明该低噪声放大器成品率大于90%,性能指标优于目前同类商业芯片指标。     

CMOS光接收机宽带前置放大器的设计

采用TSMC0.18μmCMOS工艺设计了光接收机宽带前置放大器。该前置放大器采用具有反馈特性的跨阻放大器实现,采用了RGC(RegulatedCasacoe)电路作为输入级,同时在电路中引入电感并联补偿的技术,以拓展前置放大器的带宽。仿真结果表明:1.8V单电压源供电情况下,电路功耗15.2mW,中频互阻增益为58.4dBΩ,-3dB带宽可达到10.2GHz,可工作在10Gb/s速率。     

应用于DSRC系统的5.8GHz CMOS LNA设计

基于TSMC 0.18μm CMOS RF工艺,完成了一个全集成共源-共栅低噪声放大器设计。版图后仿真结果表明:1.8V电源电压下,电路静态功耗约为17mW;在DSRC系统工作频段上,电路实现了良好的综合性能指标,输入反射系数(S11)和输出反射系数(S22)小于-15dB,增益(S21)大于14.0dB,反向隔离度(S12)达到32dB,噪声系数小于2dB,并且工作稳定。     

基于ADS仿真的宽带低噪声放大器设计

设计了一个S频段宽带低噪声放大器.该放大器采用两级E-PHEMT晶体管(ATF541M4)级联结构,单电源供电模式.应用微波仿真软件ADS对匹配电路进行了优化设计,最后通过S参数及谐波平衡仿真得到放大器的各项性能参数,在2.7～3.1 GHz频率范围内噪声系数小于0.6 dB,带内增益大于30 dB,带内平坦度小于±1 dB,输入输出驻波比小于1.6 dB,1 dB增益压缩点输入功率不小于-15 dBm.仿真结果表明,该设计完全满足性能指标要求.     

6?10 GHz ultra-wideband CMOS LNA

A two-stage matched ultra-wideband CMOS low noise amplifier (LNA) is presented. The LNA is designed to achieve a low noise figure with high voltage gain. The LNA fabricated in a 0.13 mum CMOS process shows a 3.9 dB average noise figure with a 27 dB voltage gain in the 6-10 GHz frequency band with a power consumption of 14 mW.     

Design of a fully differential CMOS LNA for 3.1-10.6 GHz UWB communication systems

A fully differential complementary metal oxide semiconductor （CMOS） low noise amplifier （LNA） for 3.1-10.6 GHz ultra-wideband （UWB） communication systems is presented. The LNA adopts capacitive cross-coupling common-gate （CG） topology to achieve wideband input matching and low noise figure （NF）. Inductive series-peaking is used for the LNA to obtain broadband flat gain in the whole 3.1-10.6 GHz band. Designed in 0.18 um CMOS technology, the LNA achieves an NF of 3.1-4.7 dB, an Sll of less than -10 dB, an S21 of 10.3 dB with ±0.4 dB fluctuation, and an input 3rd interception point （IIP3） of -5.1 dBm, while the current consumption is only 4.8 mA from a 1.8 V power supply. The chip area of the LNA is 1×0.94 mm^2.     

0.18 /spl mu/m 3-6 GHz CMOS broadband LNA for UWB radio

A 3-6 GHz CMOS broadband low noise amplifier (LNA) for ultra-wideband (UWB) radio is presented. The LNA is fabricated with the 0.18 /spl mu/m 1P6M standard CMOS process. Measurement of the CMOS LNA is performed using an FR-4 PCB test fixture. From 3 to 6 GHz, the broadband LNA exhibits a noise figure of 4.7-6.7 dB, a gain of 13-16 dB, and an input/output return loss higher than 12/10 dB, respectively. The input P/sub 1 dB/ and input IP3 (IIP3) at 4.5 GHz are about -14 and -5 dBm, respectively. The DC supply is 1.8 V.     

A CMOS variable gain LNA for UWB receivers

A CMOS variable gain low noise amplifier(LNA) is presented for 4.2-4.8 GHz ultra-wideband application in accordance with Chinese standard.The design method for the wideband input matching is presented and the low noise performance of the LNA is illustrated.A three-bit digital programmable gain control circuit is exploited to achieve variable gain.The design was implemented in 0.13-μm RF CMOS process,and the die occupies an area of 0.9 mm~2 with ESD pads.Totally the circuit draws 18 mA DC current from 1.2 V DC supply,the LNA exhibits minimum noise figure of 2.3 dB,S(1,1) less than -9 dB and S(2,2) less than -10 dB.The maximum and the minimum power gains are 28.5 dB and 16 dB respectively.The tuning step of the gain is about 4 dB with four steps in all.Also the input 1 dB compression point is -10 dBm and input third order intercept point(IIP3) is -2 dBm.     

一种无电感超宽带低噪声放大器的设计

基于Jazz 0.35 μm SiGe工艺,设计了一款工作在3～10 GHz频带范围内的超宽带低噪声放大器.该放大器采用电阻负反馈结构,并在发射极并联电容,以补偿晶体管高频增益的下降.仿真结果显示,在整个工作频带内,放大器的增益在22.3 dB以上,平坦度保持在1 dB以内,噪声系数在3.7 dB到4.6 dB之间,输入输出反射系数(S_(11)及S_(22))均在-12 dB以下.整个设计最大的优点是没有用到片上电感,使得芯片面积大大缩小,对于商业应用具有极大的吸引力.     

S-band low noise amplifier using 1 μm InGaAs/InAlAs/InP pHEMT

This paper discusses the design of a wideband low noise amplifier (LNA) in which specific architecture decisions were made in consideration of system-on-chip implementation for radio-astronomy applications. The LNA design is based on a novel ultra-low noise InGaAs/InAlAs/InP pHEMT. Linear and non-linear modelling of this pHEMT has been used to design an LNA operating from 2 to 4 GHz. A common-drain in cascade with a common source inductive degeneration, broadband LNA topology is proposed for wideband applications. The proposed configuration achieved a maximum gain of 27 dB and a noise figure of 0.3 dB with a good input and output return loss (S₁₁ < -10 dB, S₂₂ < -11 dB). This LNA exhibits an input 1-dB compression point of -18 dBm, a third order input intercept point of 0 dBm and consumes 85 mW of power from a 1.8 V supply.     

Design of UWB switched gain controlled LNA using 0.18 μm CMOS

A switched gain controlled low noise amplifier (LNA) for the 3.1- 4.8 GHz ultra-wideband system is presented. The LNA is fabricated with the 0.18 mum 1P6M standard CMOS process. Measurement of the LNA was performed using an RF probe station. In gain mode, measured results show a noise figure of 4.68-4.97 dB, gain of 12.5-13.9 dB, and input/output return loss higher than 10/8.2 dB. The input IP3 (IIP3) at 4.1 GHz is 1 dBm, and consumes 14.6 mW of power. In bypass mode, measured results show a gain of-7.0 to -8.7 dB, and input/output return loss higher than 10/6.3 dB. The input IP3 at 4.1 GHz is 9.2 dBm, and consumes 1 muW of power.     

GaAs 0.5 dB NF dual-loop negative-feedback broadband low-noise amplifier IC

A GaAs dual-loop negative-feedback low-noise amplifier (LNA) designed for the square kilometre array is presented. Effects of transformer non-idealities on LNA performance are discussed. The LNA has 0.5 dB noise figure and -10 dB input return loss from 0.6 to 1.6 GHz.     

WLAN中带ESD保护的低噪声放大器设计

介绍了一个基于IBM0.18μmCMOS工艺,用于无线局域网(WLAN)IEEE802.11a的带ESD保护电路的低噪声放大器(LNA)。通过分析电感负反馈共源共栅放大器的输入阻抗、增益和噪声系数,以及ESD保护电路对低噪声放大器性能的影响,对该5GHz低噪声放大器进行设计和优化。测试结果表明,当电源电压为1.8V时,消耗电流为6.5mA,增益达到10dB,输入匹配达到-18dB,噪声为4.29dB,线性度IIP3为4dBm。