Prediction of IMD in LDMOS transistor amplifiers using a new large-signal model

In this paper, the intermodulation distortion (IMD) behavior of LDMOS transistors is treated. First, an analysis is performed to explain measured IMD characteristics in different classes of operation. It is shown that the turn-on region plays an important role in explaining measured IMD behavior, which may also give a clue to the excellent linearity of LDMOS transistors. Thereafter, with this knowledge, a new empirical large-signal model with improved capability of predicting IMD in LDMOS amplifiers is presented. The model is verified against various measurements at low as well as high frequency in a class-AB power amplifier circuit.     

Accurate pHEMT nonlinear modeling in the presence of low-frequency dispersive effects

Low-frequency (LF) dispersive phenomena due to device self-heating and/or the presence of "traps" (i.e., surface state densities and bulk spurious energy levels) must be taken into account in the large-signal dynamic modeling of III-V field-effect transistors when accurate performance predictions are pursued, since these effects cause important deviations between direct current (dc) and dynamic drain current characteristics. In this paper, a new model for the accurate characterization of these phenomena above their cutoff frequencies is presented, which is able to fully exploit, in the identification phase, large-signal current-voltage (I-V) measurements carried out under quasi-sinusoidal regime using a recently proposed setup. Detailed experimental results for model validation under LF small- and large-signal operating conditions are provided. Furthermore, the I-V model proposed has been embedded into a microwave large-signal pseudomorphic high electron-mobility transistor (pHEMT) model in order to point out the strong influence of LF modeling on the degree of accuracy achievable under millimeter-wave nonlinear operation. Large-signal experimental validation at microwave frequencies is provided for the model proposed, by showing the excellent intermodulation distortion (IMD) predictions obtained with different loads despite the very low power level of IMD products involved. Details on the millimeter-wave IMD measurement setup are also provided. Finally, IMD measurements and simulations on a Ka-band highly linear power amplifier, designed by Ericsson using the Triquint GaAs 0.25-/spl mu/m pHEMT process, are shown for further model validation.     

Highly linear 0.18-/spl mu/m CMOS power amplifier with deep n-Well structure

The linearity of a 0.18-/spl mu/m CMOS power amplifier (PA) is improved by adopting a deep n-well (DNW). To find the reason for the improvement, bias dependent nonlinear parameters of the test devices are extracted from a small-signal model and a Volterra series analysis for an optimized nMOS PA with a proper matching circuit is carried out. From the analysis, it is revealed that the DNW of the nMOS lowers the harmonic distortion generated from the intrinsic gate-source capacitance (C/sub gs/), which is the dominant nonlinear source, and partially from drain junction capacitance (C/sub jd/). Single-ended and differential PAs for 2.45-GHz WLAN are designed and fabricated using a 0.18-/spl mu/m standard CMOS process. The single-ended PA with the DNW improves IMD3 and IMD5 about 5 dB with identical power performances, i.e., 20 dBm of P/sub out/, 18.7 dB of power gain and 31% of power-added efficiency (PAE) at P/sub 1dB/. The IMD3 and IMD5 are below -40 dBc and -47dBc, respectively. The differential PA with the DNW also shows about 7 dB improvements of IMD3 and IMD5 with 20.2 dBm of P/sub out/, 18.9 dB of power gain and 35% of PAE at P/sub 1dB/. The IMD3 and IMD5 are below -45 dB and -57 dBc, respectively. These performances of the linear PAs are state-of-the-art results.     

26.5–30-GHz Resistive Mixer in 90-nm VLSI SOI CMOS Technology With High Linearity for WLAN

A resistive mixer with high linearity for wireless local area networks is presented in this paper. The fully integrated circuit is fabricated with a 90-nm very large scale integration silicon-on-insulator (SOI) CMOS technology and has a very compact size of 0.38 mm$, times,$0.32 mm. Design guidelines are given to optimize the circuit performance. Analytical calculations and simulations with an SOI large-signal Berkeley simulation model show good agreement with measurements. At an RF of 27 GHz, an IF of 2.5 GHz and zero dc power consumption, a conversion loss of 9.7 dB, a single-sideband noise figure of 11.4 dB, and a high third-order intercept point at the input of 20 dBm are measured at a local-oscillator (LO) power of 10 dBm. At lower LO power of 0-dBm LO power, the loss is 10.3 dB. To the knowledge of the author, the circuit has by far the highest operation frequency reported to date for a resistive CMOS mixer. Furthermore, it provides the highest linearity for a CMOS mixer operating at such high frequencies.     

Improved large-signal GaN HEMT model suitable for intermodulation distortion analysis

In this article, a complete empirical large-signal model of GaN high electron-mobility transistors (HEMTs) is presented. The developed nonlinear model employs differentiable trigonometric function continuously to describe the drain-source current characteristic and its higher order derivatives, making itself suitable for the simulation of intermodulation distortion (IMD) in microwave circuits. Besides, an improved charge-conservative gate charge model is proposed to accurately trace the nonlinear gate-source and gate-drain capacitances. The model validity is demonstrated for different 0.25-µm gate-length GaN HEMTs. The simulation results of small-signal S-parameters, radio frequency (RF) large-signal power performances and two-tone IMD products show an excellent agreement with the measured data.     

A 2.4-GHz 24-dBm SOI CMOS Power Amplifier With Fully Integrated Reconfigurable Output Matching Network

In this paper, the potential of load adaptation for enhanced backoff efficiency in RF power amplifiers (PAs) has been investigated through a 0.13-mum silicon-on-insulator (SOI) CMOS fabrication technology. The RF power performance of the adopted SOI CMOS process has been preliminarily characterized by on-wafer load-pull measurements on a custom unit power transistor. A 2.4-GHz 24-dBm 2-V SOI CMOS PA with fully integrated reconfigurable output matching network has then been designed and experimentally characterized. A significant efficiency improvement of up to 34% has been achieved through load adaptation, peak efficiency being as high as 65%. Linear operation has also been demonstrated under two-tone excitation, as a 16-dBm output power has been attained while complying with a - 40-dBc third-order intermodulation distortion specification.     

Frequency-Selective Predistortion Linearization of RF Power Amplifiers

This paper presents a frequency-selective RF vector predistortion linearization system for RF multicarrier power amplifiers (PAs) affected by strong differential memory effects. Differential memory effects can be revealed in two-tone experiment by the divergence for increasing tone-spacing of the vector Volterra coefficients associated with the lower and upper intermodulations tones. Using large-signal vector measurement with a large-signal network analyzer, a class-AB LDMOS RF PA is demonstrated to exhibit a strong differential memory effect for modulation bandwidth above 0.3 MHz. New frequency-selective RF and baseband predistortion linearization algorithms are proposed to separately address the linearization requirements of the interband and inband intermodulation products of both the lower and upper sidebands. Theoretical verification of the algorithms are demonstrated with Matlab simulations using a Volterra/Wiener PA model with memory effects. The baseband linearization algorithm is next implemented in a field-programmable gate array and experimentally investigated for the linearization of the class-AB LDMOS PA for two carrier wideband code-division multiple-access signals. The ability of the algorithm to selectively linearize the two interband and four inband intermodulation products is demonstrated. Adjacent channel leakage ratio of up to 45 dBc for inband and interband are demonstrated experimentally at twice the typical fractional bandwidth.     

Low-power/low-voltage RF microsystems for wireless sensors networks

This paper presents radio-frequency (RF) microsystems (MSTs) composed by low-power devices for use in wireless sensors networks (WSNs). The RF CMOS transceiver is the main electronic system and its power consumption is a critical issue. Two RF CMOS transceivers with low-power and low-voltage supply were fabricated to operate in the 2.4 and 5.7 GHz ISM bands. The measurements made in the RF CMOS transceiver at 2.4 GHz, which showed a sensitivity of −60 dBm with a power consumption of 6.3 mW from 1.8 V supply. The measurements also showed that the transmitter delivers an output power of 0 dBm with a power consumption of 11.2 mW. The RF CMOS transceiver at 5.7 GHz has a total power consumption of 23 mW. The target application of these RF CMOS transceivers is for MSTs integration and for use as low-power nodes in WSNs to work during large periods of time without human operation, management and maintenance. These RF CMOS transceivers are also suitable for integration in thermoelectric energy scavenging MSTs.     

Large-Signal Model for AlGaN/GaN HEMTs Accurately Predicts Trapping- and Self-Heating-Induced Dispersion and Intermodulation Distortion

In this paper, an accurate table-based large-signal model for AlGaN/GaN HEMTs accounting for trapping- and self-heating-induced current dispersion is presented. The B-spline-approximation technique is used for the model-element construction, which improves the intermodulation-distortion (IMD) simulation. The dynamic behavior of the trapping and self-heating processes is taken into account in the implementation of the model. The model validity is verified by comparing the simulated and measured outputs of the device tested under pulsed and continuous large-signal excitations for devices of 1-mm gate width. Single- and two-tone simulation results show that the model can efficiently predict the output power and its harmonics and the associated IMD under different input-power and bias conditions.     

RF electro-thermal modeling of LDMOSFETs for power-amplifier design

A new approach for the electro-thermal modeling of LDMOSFETs for power-amplifier design that bypasses pulsed-IVs and pulsed-RF measurements is presented in this paper. The existence of low-frequency dispersion in LDMOSFETs is demonstrated by comparing pulsed IVs with iso-thermal IVs. The modeling technique uses iso-thermal IV and microwave measurements to obtain the temperature dependence of small-signal parameters. Optimized tensor-product B-splines, which distribute knots to minimize fitting errors, are used to represent the small-signal parameters and extract the large-signal model as a function of voltages and temperature. The model is implemented on ADS and is verified by simulating and measuring the power harmonics and IMD large-signal performance of a power amplifier. The impact on the model of temperature-dependent drain and gate charge is investigated. The presented model is found to compare well and, in some cases, exceed the existing MET model for LDMOSFETs     

Quantifying memory effects in RF power amplifiers

This paper proposes a system-level behavioral model for RF power amplifiers (PAs), which exhibit memory effects, that is based on the parallel Wiener system. The model extraction is performed using two-tone intermodulation distortion (IMD) measurements with different tone frequency spacings and power levels. It is found that by using such a model, more accurate adjacent-channel power-ratio levels may be predicted for high PAS close to the carrier frequency. This is validated using IS-95B CDMA signals on a low-power (0.5 W) class-AB PA, and on a high-power (45 W) class-B PA. The model also provides a means to quantify memory effects in terms of a figure-of-merit that calculates the relative contribution to the IMD of the memoryless and memory portion of the PA nonlinearity. This figure-of-merit is useful in providing an estimate of the amount of correction that a memoryless predistortion system may have on PAS that exhibit memory effects.     

Requirements for low intermodulation distortion in GaN-AlxGa1-xN high electron mobility transistors: a modelassessment

A model analysis of the large-signal characteristics of GaN-Al_xGa_1-xN high-electron mobility transistors (HEMTs) with particular emphasis on intermodulation distortion (IMD) and the third-order intercept point. Since the nonlinearity depends critically on the carrier transport behavior, a Monte Carlo (MC) based numerical simulation scheme has been employed. The focus is to identify parameters and their interdependencies with a view of setting optimal limits for enhanced microwave performance. A case is made for increased mole fraction for the barrier layer, reducing the transit length, and introducing a thin AlN interfacial layer for suppressing real space transfer for enhancing the device performance. Finally, high-temperature predictions of the nonlinear behavior and IMD have been made, by carrying out the MC simulations at 600 K. In a process a favorable case is made for the GaN system as a potential candidate for microwave and RF applications at elevated temperatures     

Discrete-time parametric amplification based on a three-terminal MOS varactor: analysis and experimental results

This paper discusses discrete-time parametric amplification based on large-signal operation of a three-terminal MOS varactor. The principle of operation is described in detail and analytical estimates of performance are derived. Detailed measurements are reported for a prototype implemented in standard digital CMOS technology. It is demonstrated that the technique can be used to provide micropower, low-gain, low-noise, large-signal amplification.     

Large-signal analysis of MOS varactors in CMOS -G/sub m/ LC VCOs

MOS varactors are used extensively as tunable elements in the tank circuits of RF voltage-controlled oscillators (VCOs) based on submicrometer CMOS technologies. MOS varactor topologies include conventional D = S = B connected, inversion-mode (I-MOS), and accumulation-mode (A-MOS) structures. When incorporated into the VCO tank circuit, the large-signal swing of the VCO output oscillation modulates the varactor capacitance in time, resulting in a VCO tuning curve that deviates from the dc tuning curve of the particular varactor structure. This paper presents a detailed analysis of this large-signal effect. Simulated results are compared to measurements for an example 2.5-GHz complementary -G/sub m/ LC VCO using I-MOS varactors implemented in 0.35-/spl mu/m CMOS technology.     

RF CMOS modeling: a novel empirical large-signal model for an RF-MOSFET

A novel empirical model for large-signal modeling of an RF-MOSFET is proposed. The proposed model is validated in the DC, AC, small-signal and large-signal characteristics of a 32-finger nMOSFET fabricated in SMIC's 0.18 μm RF CMOS technology. The power dissipation caused by self-heating is described. Excellent agreement is achieved between simulation and measurement for DC, S-parameters (50 MHz-40 GHz), and power characteristics, which shows that our model is accurate and reliable.     

基于MOS Model 20的RF-SOI LDMOS大信号建模

提出了一种新的基于Philips MOS Model 20 (MM20) 的RF-SOI (radio frequency silicon-on-insulator) LDMOS (laterally diffused MOS) 大信号等效电路模型. 描述了弱雪崩效应以及由热效应引起的功率耗散现象. 射频寄生元件由实验测得的S参数解析提取,并通过必要的优化快速准确地获得最终值. 模型的有效性是通过一20栅指 (每指栅长L=1μm,宽W=50μm) 体接触高阻RF-SOI LDMOS在直流,交流小信号和大信号条件下的实验数据验证的. 结果表明,直流、S参数 (10MHz~20.01GHz) 以及功率特性的仿真和实验测得数据能够很好地拟合,说明本文提出的模型具有良好和可靠的精度. 本文完成了对MM20在RF-SOI LDMOS大信号应用领域的拓展. 模型由Verilog-A描述,使用ADS (hpeesofsim)电路仿真器.     

A Study of the Single-Frequency Quenched-Domain Mode Gunn-Effect Oscillator

A large-signal analysis of the high-frequency quenched-domain mode (Q-mode) of Gunn-effect devices has been developed. This is a phenomenological model and includes such effects as distinct domain formation and quenching processes, domain behavior in the presence of an RF voltage, displacement current, voltage dependence of the domain width, and others. The basis of the analysis is to obtain an instantaneous current-voltage transfer characteristic for the device and use it to generate the current waveform corresponding to a given periodic voltage waveform. The basic results of the large-signal analysis are then obtained from these current waveforms. The analysis reveals the distinguishing features of Q-mode oscillators. Admittance measurements on the oscillating device have been made and support the theoretical results for single-frequency operation. Applications of this analysis for investigating other nonlinear properties of these devices are suggested.     

RF Characterization of Microwave Power Fet's

The large-signal S-parameter S/sub 22/ and the optimum load for maximum output power are two parameters commonly used in the RF characterization of microwave power FET's. Using a nonlinear circuit model of the device, the dependence on RF power of each of these parameters is investigated. A method is given for computing the optimum load from the Iarge-signal S/sub 22/. Equivalent load-pull data can thus be obtained without the need for load-pull measurements. The gain compression characteristics of the transistor for arbitrary load can be computed from large-signal S/sub 21/, and S/sub 22/ data.     

Transformer-coupled cascode stage for mm-wave power amplifiers in sub-μm CMOS technology

An amplifier topology based on a transformer-coupled cascode stage is presented and compared with the most used solutions for sub-μm CMOS power amplifiers, which are the common-source stage, cascode stage, and capacitive-coupled cascode stage. The comparison was carried out by designing each amplifier in a 65-nm CMOS technology and for a 60-GHz operating frequency. The design was optimized for a trade off among power gain, saturated output power, and linearity. Operating from a 1.2-V supply voltage, the proposed amplifier improves both small-signal and large-signal performance with respect to the most common approaches, thus demonstrating effectiveness with sub-μm CMOS technologies and mm-wave operation.     

Power-Combining Transformer Techniques for Fully-Integrated CMOS Power Amplifiers

Fully integrated CMOS power amplifiers (PAs) with parallel power-combining transformer are presented. For the high power CMOS PA design, two types of transformers, series-combining and parallel-combining, are fully analyzed and compared in detail to show the parasitic resistance and the turn ratio as the limiting factor of power combining. Based on the analysis, two kinds of parallel-combining transformers, a two-primary with a 1:2 turn ratio and a three-primary with a 1:2 turn ratio, are incorporated into the design of fully-integrated CMOS PAs in a standard 0.18-mum CMOS process. The PA with a two-primary transformer delivers 31.2 dBm of output power with 41% of power-added efficiency (PAE), and the PA with a three-primary transformer achieves 32 dBm of output power with 30% of PAE at 1.8 GHz with a 3.3-V power supply.