可级联拆分查找表：增强型逻辑结构

提高FPGA芯片的性能和面积效率是FPGA结构研究的目标。结合现有的可拆分查找表和可级联查找表结构的优点,提出了可级联拆分查找表逻辑结构。通过在普通可拆分查找表结构中插入可配置选择器,实现了其中2个子查找表单元的可级联,大大减小了电路中2个子查找表之间的互连延迟。在MCNC测试电路集下,可级联拆分查找表在电路总面积相近的情况下,性能上平均提升12%。     

基于无限冲激响应的微波光子级联滤波器

为进一步拓展微波光子滤波器的 FSR(自由谱范围)和提高滤波器的Q值,进行了 IIR(无限冲激响应)滤波器分别与FIR(有限冲激响应)滤波器和 IIR滤波器级联的研究。分析了两种级联结构的滤波特性并给出了相应的传输函数。IIR滤波器与FIR滤波器级联后的FSR与Q值是IIR滤波器的2n倍;IIR滤波器与IIR滤波器级联后的FSR是各个IIR滤波器的FSR的最小公倍数。用 Matlab软件仿真验证了两种级联结构的频率响应特性,实验验证了 IIR滤波器与 IIR滤波器的级联特性。IIR滤波器与 IIR滤波器的级联有望实现宽频率范围内的单通带滤波器。     

IIR数字滤波器的FPGA实现

本文介绍了一种采用级联结构在FPGA上实现任意阶IIR数字滤波器的方法。此设计扩展性好：便于调节波波器的性能，可以根据不同的要求在不同规模的FPGA上加以实现。     

一种基于查找表的移位寄存器链的设计

提出了一种基于查找表的移位寄存器链的设计,以查找表的配置存储单元作为移位模块,以查找表的输入信号作为移位地址选择信号,通过对时钟和写使能的控制进行移位操作.1个查找表最大实现32个时钟周期的移位操作,4个查找表通过配置,可实现4条相互独立的32位移位寄存器链,或首尾级联实现一个128位的移位寄存器链.基于28nm工艺,...     

高阶IIR数字滤波器的FPGA描述

介绍高阶IIR数字滤波器采用级联结构在FPGA上实现的方法。利用Matlab信号处理工具箱中的滤波器设计和分析工具（FDATool）很方便地设计出符合应用要求的未经量化的IIR滤波器，并进一步用VHDL语言加以描述，通过编译、功能仿真、综合和时序仿真之后就可以在FPGA上实现了。此设计扩展性好，在实际使用中，可适当修改外围参数改变滤波器的频率响应，根据不同的要求在不同规模的FPGA上加以实现。     

改进查找表译码算法在TPC中的应用研究

TPC(Turbo乘积码)是一种串行级联分组码,它采用简单的行列交织结构,不仅易于硬件实现,而且具有优异的纠错性能。为进一步降低TPC的译码延时,在研究TPC编译码原理的基础上,将改进查找表译码算法引入Chase算法,用于对测试序列的代数译码。以(31,21)BCH码作为TPC子码,仿真分析了TPC的译码性能,对测试序列分别采用传统的查找表算法和快速查找表算法后的TPC译码延时进行了比较。结果表明:相对传统的查找表译码算法,测试序列的代数译码采用新算法,可有效降低TPC的译码延时。     

一种新的用于有记忆功放的查找表预失真器

 针对有记忆非线性功放提出了一种新的基于查找表的记忆型预失真器.该记忆型预失真器采用无记忆预失真器的级联扩展,其横向滤波器结构相比记忆多项式方法降低了复杂度,却能够得到与其相近的线性化效果.并且针对查找表固有的量化误差大和自适应收敛速度慢的缺点,分别采用线性内插和加权窗迭代更新的方法加以改进.在非线性功放的记忆多项式模型下,通过多载波WCDMA宽带信号和OFDM宽带信号验证了基于查找表的记忆型预失真器的良好线性化效果和改进方法的有效性.     

IIR滤波器并行实现结构研究

基于多项式信号的并行表达,得到了一种IIR滤波器并行结构.通过对该并行结构的分析,得到了一种高效的IIR滤波器脉动阵实现结构.这种结构具有阵列规模小,处理速度快的优点.     

一种高阶线性FIR滤波器设计

为了解决高阶线性FIR滤波器占用查找表资源过多的问题,提出了一种采用对称查找表的分布式结构。利用线性FIR滤波器系数对称的特点,设计了深度更小的对称查找表。采用时分复用技术和流水线技术,有效节约了查找表资源,提高了FIR滤波器的运行频率。在Xilinx XC5VLX110T FPGA芯片上,实现了1 023阶的基于对称查找表的FIR滤波器。结果表明,相比于分段查找表结构,对称查找表结构的FIR滤波器节约了48%的Block Rom资源,提升了15%的最高时钟频率。     

精密测距系统中IIR滤波器的设计

文中介绍了精密测距系统中 IIR 滤波器的设计,给出了 IIR 级联滤波器设计的算法流程。并对所设计的滤波器进行了仿真验证,实验结果表明：本文所设计的滤波器,能有效地从调制信号中提取出包络信号。     

Synthesis of grating lattice circuits

The realization of high-performance components based on optical infinite impulse response (IIR) filter design theory is desirable for next-generation global optical networks. Previously proposed IIR filter synthesis methods are matrix factorization techniques for a lattice circuit using ring resonators. The size of ring resonator limits the bandwidth of the lattice filters. In this paper, two configurations of grating lattice filters are synthesized by using a scattering matrix representation for the grating. The grating is one of the most powerful optical elements both in fiber optics and photonic integrated circuits. One configuration is a serial grating lattice filter configuration and the other is a parallel grating lattice filter configuration. The actual frequency response of the synthesized grating lattice filter is calculated to show the design limitation due to the frequency response of the element gratings     

数据通信总线技术的现状与未来发展趋势

文章结合中兴通讯ZXR10数据产品中通信总线实际应用情况,阐述了各种数据通信总线的工作时钟频率范围、带宽范围以及它们各自的优势和缺陷.文章认为并行总线由于自身缺陷,已经不适合进行高速传输,高速串行点对点连接将代替传统的并行接口;数据交换也不再是简单地通过驱动电路和并行数据线进行,而是通过特殊的串行高速总线连接;传统的在一条总线上同时挂载多个设备的模式正逐渐消亡,总线功能已被一个集中式的交换模块取代,而交换模块和各个设备都是通过高速串行点对点的方式进行连接.     

A Serial Input/Output Circuit with 8 bit and 16 bit Selection Modes

This paper presents a serial interface circuit that permits selection of the amount of data converted from serial‐to‐parallel and parallel‐to‐serial and overcomes the disadvantages of the conventional serial input/output interface. Based on the selected data length operating mode, 8 bit or 16 bit serial‐to‐parallel and 8 bit or 16 bit parallel‐to‐serial conversion takes place in data blocks of the selected data length.     

一种人工神经网络自适应IIR滤波器

本文提出了一种人工神经网络自适应ＩＩＲ滤波器，这种自适应ＩＩＲ滤波器采用并联型结构，用人工神经网络实现，并保证系统在自适应过程中的稳定性，从而得到了一种稳定的、高度并行的自适应ＩＩＲ滤波器，从根本上改变了以往的串行数值迭代系统，使滤波器自适应过程仅需要几个微秒就可以完成。从而有可能用神经自适应系统完成对快速变化信号的实时处理。本文给出了计算机模拟的结果，理论和模拟结果均表明该结构是稳定的，收敛速度也有明显增加。     

FPGA based multi-channel variable-length FFT implementation

High-speed real-time digital frequency analysis is one major field of Fast Fourier Transform (FFT) application, such as Synthetic Aperture Radar(SAR) processing and medical imaging. In SAR processing, the image size could be 4 k×4 k in normal and it has become larger over the years. In the view of real-time, extensibility and reusable characteristics, an Field Programmable Gate Array(FPGA) based multi-channel variable-length FFT architecture which adopts radix-2 butterfly algorithm is proposed in this paper. The hardware implementation of FFT is partially reconfigurable architecture. Firstly, the proposed architecture in the paper has flexibility in terms of chip area, speed, resource utilization and power consumption. Secondly, the proposed architecture combines serial and parallel methods in its butterfly computations. Furthermore, on system-level issue, the proposed architecture takes advantage of state processing in serial mode and data processing in parallel mode. In case of sufficient FPGA resources, state processing of serial mode mentioned above is converted to pipeline mode. State processing of pipeline mode achieves high throughput.     

基于CPLD的I~2C总线接口设计

在电路设计中,I2C总线是比较常用的两线式串行通信方式,大多数的CPU都擅长于并口操作,不具备直接操作I2C总线接口的能力。为了使不具备I2C总线接口能力的CPU通过对并口的简单操作实现对I2C总线接口的控制,在分析I2C总线常用工作模式的基础上,设计实现工作于主机模式的,以CPLD完成I2C总线开始信号、结束信号的输出,以及并行数据到I2C总线模式串行数据转换或I2C模式串行数据到并行数据转换的I2C接口模块。采用该模块,可以使不具备I2C总线接口的CPU通过并口方便地控制I2C总线设备,简化系统程序设计。     

Design methodology for subdigit pipelined digit-serial IIR filters

A novel architecture for high performance two's complement digit-serial IIR filters is presented. The application of the digit-serial computation to the design of IIR filters introduces delay elements in the feedback loop of the IIR filter. This offers the possibility of pipelining the feedback loop inherent in the IIR filters. To fully explore the advantages offered by the use of digit-serial computation, the digit serial structure is based on the feed forward of the carry digit, which allows subdigit pipelining to increase the throughput rate of the IIR filters. A systematic design methodology is presented to derive a wide range of digit-serial IIR filter architectures which can be pipelined to the subdigit level. This will give designers greater flexibility in finding the best trade off between hardware cost and throughput rate. It is shown that the application of digit-serial computations for the realisation of IIR filters combined with the possibility of subdigit pipelining, results in an increase in the computation speed with a considerable reduction in silicon area consumption when compared to an equivalent bit-parallel IIR filter realisations.     

A CMOS serial link for fully duplexed data communication

This paper describes a CMOS serial link allowing fully duplexed 500 Mbaud serial data communication. The CMOS serial link is a robust and low-cost solution to high data rate requirements. A central charge pump PLL for generating multiphase clocks for oversampling is shared by several serial link channels. Fully duplexed serial data communication is realized in the bidirectional bridge by separating incoming data from the mixed signal on the cable end. The digital PLL accomplishes process-independent data recovery by using a low-ratio oversampling, a majority voting, and a parallel data recovery scheme. Mostly, digital approach could extend its bandwidth further with scaled CMOS technology. A single channel serial link and a charge pump PLL are integrated in a test chip using 1.2 μm CMOS process technology. The test chip confirms upto 500 Mbaud unidirectional mode operation and 320 Mbaud fully duplexed mode operation with pseudo random data patterns     

On the convergence properties of the Hopfield model

The main contribution of the present work is showing that the known convergence properties of the Hopfield model can be reduced to a very simple case, for which an elementary proof is provided. The convergence properties of the Hopfield model are dependent on the structure of the interconnections matrix W and the method by which the nodes are updated. Three cases are known: (1) convergence to a stable state when operating in a serial mode with symmetric W; (2) convergence to a cycle of length 2, at most, when operating in a fully parallel mode with symmetric W; and (3) convergence to a cycle of length 4 when operating in a fully parallel mode with antisymmetric W. The three known results are reviewed and it is proven that the fully parallel mode of operation is a special case of the serial model of operation. There are three more cases than can be considered using this characterization: serial mode of operation, antisymmetric W; serial mode of operation, arbitrary W; and fully parallel mode of operation, arbitrary W. By exhibiting exponential lower bounds on the length of the cycles in other cases, it is proven that the three known cases are the only interesting ones