Reconfigurable Filter Coprocessor Architecture for DSP Applications

Digital Signal Processing (DSP) is widely used in high-performance media processing and communication systems. In majority of these applications, critical DSP functions are realized as embedded cores to meet the low-power budget and high computational complexity. Usually these cores are ASICs that cannot be easily retargeted for other similar applications that share certain commonalities. This stretches the design cycle that affects time-to-market constraints. In this paper, we present a reconfigurable high-performance low-power filter coprocessor architecture for DSP applications. The coprocessor architecture, apart from having the performance and power advantage of its ASIC counterpart, can be reconfigured to support a wide variety of filtering computations. Since filtering computations abound in DSP applications, the implementation of this coprocessor architecture can serve as an important embedded hardware IP.     

Mapping of generalized template matching onto reconfigurable computers

Image processing algorithms for template matching, two-dimensional (2-D) digital filtering, morphologic operations, and motion estimation share some common properties. They can all benefit from using reconfigurable computers that use coprocessor boards based on field-programmable gate array (FPGA) chips. This paper characterizes those applications as generalized template matching (GTM) operations and describes the mapping of the GTM operations onto reconfigurable computers. A three-step approach is described. The first two steps enumerate and prune the design space of basic GTM building blocks, which consist of FPGA buffers and GTM computation cores. The last step is to achieve a solution through an optimal combination of these building blocks where the cost function is the FPGA computation time and the constraints are FPGA coprocessor board resources. Various FPGA buffers are presented so as to introduce design options of basic GTM building blocks. Algorithms used for the mapping are described. Experimental results are summarized to reveal the relationship between the GTM mapping results and FPGA board resource parameters.     

A framework for reconfigurable computing: task scheduling and context management-a summary

Reconfigurable computing is consolidating itself as a real alternative to ASICs (Application Specific Integrated Circuits) and general-purpose processors. The main advantage of reconfigurable computing derives from its unique combination of broad applicability, provided by the reconfiguration capability, and achievable performance, through the potential parallelism exploitation. The key aspects of the scheduling problem in a reconfigurable architecture are discussed, focusing on a task scheduling methodology for DSP and multimedia applications, as well as the context management and scheduling optimizations.     

面向DSP应用的可重构计算

DSP应用的特点是计算密集并适合并行处理,传统的可编程处理器与ASIC在性能和灵活性上各有优劣.因此出现了一种新的计算模式-可重构计算.由于它能将效率和灵活性很好地结合在一起,故正得到广泛的关注和研究.本文在介绍可重构计算的概念和分类的基础上,着重讨论了一些主流的可重构计算系统,分析了各类系统应用于DSP的特点,对可重构计算在计算模型,编译器,映射技术以及开发环境等方面的现状和趋势进行了探讨,并给出了自己的思考.     

Reconfigurable Computing for Digital Signal Processing: A Survey

Steady advances in VLSI technology and design tools have extensively expanded the application domain of digital signal processing over the past decade. While application-specific integrated circuits (ASICs) and programmable digital signal processors (PDSPs) remain the implementation mechanisms of choice for many DSP applications, increasingly new system implementations based on reconfigurable computing are being considered. These flexible platforms, which offer the functional efficiency of hardware and the programmability of software, are quickly maturing as the logic capacity of programmable devices follows Moore's Law and advanced automated design techniques become available. As initial reconfigurable technologies have emerged, new academic and commercial efforts have been initiated to support power optimization, cost reduction, and enhanced run-time performance.This paper presents a survey of academic research and commercial development in reconfigurable computing for DSP systems over the past fifteen years. This work is placed in the context of other available DSP implementation media including ASICs and PDSPs to fully document the range of design choices available to system engineers. It is shown that while contemporary reconfigurable computing can be applied to a variety of DSP applications including video, audio, speech, and control, much work remains to realize its full potential. While individual implementations of PDSP, ASIC, and reconfigurable resources each offer distinct advantages, it is likely that integrated combinations of these technologies will provide more complete solutions.     

一种面向流应用加速的可重构协处理器

以图形处理、数字信号处理等为代表的流应用,对微处理器提出了高并行度、高性能和高带宽的要求。针对流应用加速的流处理器体系架构得到了广泛研究。流体系结构大多集成大量的功能单元、开发多层次并行和存储来加速流应用,但同时增加了系统功耗和芯片面积。分析和比较了近年来主流的流处理器架构,提出了一种用于流应用加速的可重构协处理器。该协处理器针对流应用特点,实现了数据级和指令级并行,并集成了多个可以动态配置的运算单元,可动态配置其运算类型和数据类型,提升系统灵活性,降低芯片面积。针对典型算法,该处理器实现了更高的加速比,综合后延时为9.74 ns,功耗为63.69 mW。     

空间太阳望远镜星载数据处理系统中的 动态可重构协处理器研究

本文提出了一种为空间太阳望远镜星载数据处理系统而设计的动态可重构协处理器方案,该方案利用4bits粒度可重构阵列将传统的基于指令流的运算方式变为基于数据流与配置流的运算方式,并通过指令流水实现了动态可重构单元与主处理器的协同工作.文章最后还给出了该方案在Xilinx XC2V3000上的实现及该实现用于乘法和1024点复数快速傅立叶变换时的性能.     

嵌入式粗颗粒度可重构处理器的软硬件协同设计流程

 面向多媒体应用的可重构处理器架构由主处理器和动态配置的可重构阵列(Reconfigurable Cell Array,RCA)组成.协同设计流程以循环流水线和流水线配置技术为基础,采用启发式算法对应用中较大的关键循环进行了软硬件划分,使用表格调度算法实现了任务在RCA上的映射.经过FPGA验证,H.264基准中的核心算法平均执行速度相比于PipeRench,MorphoSys,以及TI DSP TMS320C64X提高了3.34倍.     

A framework for reconfigurable computing: task scheduling andcontext management

Dynamically reconfigurable architectures are emerging as a viable design alternative to implement a wide range of computationally intensive applications. At the same time, an urgent necessity has arisen for support tool development to automate the design process and achieve optimal exploitation of the architectural features of the system. Task scheduling and context (configuration) management become very critical issues in achieving the high performance that digital signal processing (DSP) and multimedia applications demand. This article proposes a strategy to automate the design process which considers all possible optimizations that can be carried out at compilation time, regarding context and data transfers. This strategy is general in nature and could be applied to different reconfigurable systems. We also discuss the key aspects of the scheduling problem in a reconfigurable architecture such as MorphoSys. In particular, we focus on a task scheduling methodology for DSP and multimedia applications, as well as the context management and scheduling optimizations     

An architecture for next-generation radio access networks

With fourth-generation wireless technologies envisioned to provide high bandwidth for content-rich multimedia applications, next-generation mobile communication systems are well poised to lead the technology march. Incumbent with the new technology is the challenge of providing flexible, reconfigurable architectures capable of catering to the dynamics of the network, while providing cost-effective solutions for service providers. In this article we focus on IP-based radio access network architectures for next-generation mobile systems. We provide an insight into wireless mesh-based connectivity for the RAN network elements - using short high-bandwidth links to interconnect the network entities in a multihop mesh network for backhauling traffic to the core. A generic self-similar fractal topology, using optical wireless transmission technology, is described. We study the performance of the architecture and conclude that mesh-based architectures are well suited to provide highly scalable, dynamic radio access networks with carrier-class features at significantly low system costs.     

High Performance Reconfigurable FIR Filter Architecture Using Optimized Multiplier

In mobile communication systems and multimedia applications, need for efficient reconfigurable digital finite impulse response (FIR) filters has been increasing tremendously because of the advantage of less area, low cost, low power and high speed of operation. This article presents a near optimum low- complexity, reconfigurable digital FIR filter architecture based on computation sharing multipliers (CSHM), constant shift method (CSM) and modified binary-based common sub-expression elimination (BCSE) method for different word-length filter coefficients. The CSHM identifies common computation steps and reuses them for different multiplications. The proposed reconfigurable FIR filter architecture reduces the adders cost and operates at high speed for low-complexity reconfigurable filtering applications such as channelization, channel equalization, matched filtering, pulse shaping, video convolution functions, signal preconditioning, and various other communication applications. The proposed architecture has been implemented and tested on a Virtex 2 xc2vp2-6fg256 field-programmable gate array (FPGA) with a precision of 8-bits, 12-bits, and 16-bits filter coefficients. The proposed novel reconfigurable FIR filter architecture using dynamically reconfigurable multiplier block offers good area and speed improvement compared to existing reconfigurable FIR filter implementations.     

Clock buffer chip with multiple target automatic skew compensation

This paper describes the application of a digital delay locked loop that compensates for variable delays on the clock chip, printed circuit board clock traces, and the clock systems on multiple ASICs. For a computer system consisting of nine PC boards (“modules”) plugged into a back plane with two clock chips per board and six ASICs per clock chip, a locking range of 25-150 MHz was achieved with a maximum skew in the system of less than 1 ns     

Virtual memory window for application-specific reconfigurable coprocessors

The complexity of hardware/software (HW/SW) interfacing and the lack of portability across different platforms, restrain the widespread use of reconfigurable accelerators and limit the designer productivity. Furthermore, communication between SW and HW parts of codesigned applications are typically exposed to SW programmers and HW designers. In this work, we introduce a virtualization layer that allows reconfigurable application-specific coprocessors to access the user-space virtual memory and share the memory address space with user applications. The layer, consisting of an operating system (OS) extension and a HW component, shifts the burden of moving data between processor and coprocessor from the programmer to the OS, lowers the complexity of interfacing, and hides physical details of the system. Not only does the virtualization layer enhance programming abstraction and portability, but it also performs runtime optimizations: by predicting future memory accesses and speculatively prefetching data, the virtualization layer improves the coprocessor execution-applications achieve better performance without any user intervention. We use two different reconfigurable system-on-chip (SoC) running Linux and codesigned applications to prove the viability of our concept. The applications run faster than their SW versions, and the overhead due to the virtualisation is limited. Dynamic prefetching in the virtualisation layer further reduces the abstraction overhead.     

FleXilicon Architecture and Its VLSI Implementation

In this paper, we present a new coarse-grained reconfigurable architecture called FleXilicon for multimedia and wireless communications, which improves resource utilization and achieves a high degree of loop level parallelism (LLP). The proposed architecture mitigates major shortcomings with existing architectures through wider memory bandwidth, reconfigurable controller, and flexible word-length support. VLSI implementation of FleXilicon indicates that the proposed pipeline architecture can achieve a high speed operation up to 1 GHz using 65-nm SOI CMOS process with moderate silicon area. To estimate the performance of FleXilicon, we modeled the processor in SystemC and implemented five different types of applications commonly used in wireless communications and multimedia applications and compared its performance with an ARM processor and a TI digital signal processor. The simulation results indicate that FleXilicon reduces the number of clock cycles and increases the speed for all five applications. The reduction and speedup ratios are as large as two orders of magnitude for some applications.      

A real-time electrical impedance tomograph

Electrical properties of tissues in the human body can be imaged using a technology known as Electrical Impedance Tomography. In this modality, sinusoidal electrical currents are applied to the body using electrodes attached to the skin, and voltages that are developed on the electrodes are measured. Using these data, a reconstruction algorithm computes the conductivity and permittivity distributions within the body. This paper describes the reconstruction algorithm, image display algorithm, and hardware of a real-time Electrical Impedance Tomograph known as the Real-Time Imaging System. The reconstruction algorithm, executed by a commercially available coprocessor board that resides in a 386-based personal computer, is a modification of the Newton's One Step Error Reconstructor (NOSER) that minimizes algorithm execution time by precomputing many quantities. The image display algorithm, also executed by the coprocessor board, maps the output of the reconstruction algorithm into an image which is displayed using a video graphics board. The architecture of the system and execution times of algorithms implemented by the system are discussed. Using the continuous data acquisition mode of the Real-Time Imaging System, data from the thorax of a normal human subject were collected. Admittivity changes in the chest, as a result of respiration and the cardiac cycle, are presented. Data that were collected from the leg of a normal subject are shown which demonstrate capabilities of the triggered data acquisition mode of the system, allowing data acquisition synchronization with an electrocardiogram     

Reconfigurable receiver approach for future wireless terminals

An overview on RF-front-end architectures and technologies for future reconfigurable mobile communication is given. A favourable solution for fourth mobile generation is an extension of traditional cellular parameters by OFDM-based systems like WLAN. Therefore, an approach for widely reconfigurable receivers considering a variety of different standards, with the example of combining WCDMA and WLAN front-end into one architecture, is presented in this paper. RF-front-end key components like low noise amplifiers, mixers, and frequency synthesizers, as well as baseband variable gain amplifiers and filters are treated, particularly with regard to reconfigurable systems.     

Market and Technology Drivers for Cellular Infrastructure Modem Development

Cellular Infrastructure seems to be a fertile ground for new and sometimes not so new architectural ideas. Start ups as well as mature companies propose variants on software defined radio, reconfigurable architectures and dedicated chip sets. However the bulk of modems today have remained a combination of digital signal processors and ASICs. The demise of the DSP has been predicted many times over the last decade and yet it remains a strong part of cellular infrastructure. So what changes are really happening? In this paper we take a methodical approach to this question by first identifying the forces that are driving the industry today, and then deducing the architecture evolution implied by these forces. We discover that software defined radio and reconfigurability do indeed play a role but perhaps not in the way many suspect.     

Hardware-software architecture of the SWAN Wireless ATM network

The SWAN (Seamless Wireless ATM Network) system provides end-to-end ATM connectivity to mobile end-points equipped with RF transceivers for wireless access. Users carrying laptops and multimedia terminals can seamlessly access multimedia data over a backbone wired network while roaming among room-sized cells that are equipped with basestations. The research focus on how to make ATM mobile and wireless distinguishes SWAN from present day mobile-IP based wireless LANs. This paper describes the design and implementation of the ATM-based wireless last-hop, the primary components of which are the air-interface control, the medium access control, and the low-level ATM transport and signalling.The design is made interesting by its interplay with ATM; in particular, by the need to meaningfully extend over the wireless last-hop the service quality guarantees made by the higher level ATM layers. The implementation, on the other hand, is an example of hardware-software co-design and partitioning. A key component of the wireless hop implementation is a custom designed reconfigurable wireless adapter card called FAWN (Flexible Adapter for Wireless Networking) which is used at the mobiles as well as at the basestations. The functionality is partitioned three-way amongst dedicated reconfigurable hardware on FAWN, embedded firmware on FAWN, and device driver software on a host processor. Using an off-the-shelf 625 Kbps per channel radio, several of which can be supported by a single FAWN adapter to provide multiple channels, per-channel unidirectional TCP data throughput of 227 Kbps (or, 454 Kbps bidirectional) and per-channel unidirectional native ATM data throughput of 210 Kbps (or, 420 Kbps bidirectional) have been obtained.     

一种基于数字信号处理器的媒体处理器结构及设计

设计了一种针对图像、音频、视频等多媒体数据的处理新型结构的媒体处理器。该媒体处理器由一个通用数字信号处理器及多媒体协处理器构成,其指令集包含了通用的数字信号处理指令及扩展的多媒体处理指令。多媒体协处理器中包含了多个专用于多媒体处理的功能模块,可以加速多媒体处理的进行。该媒体处理器具有强大的多媒体处理能力,可实现对JPEG压缩图像、MP3音频流或MPEG2的MP@ML级别的压缩视频流的实时解码。