电场调制效应对氧化层电流弛豫谱的影响

本文用单陷阱电荷俘获模型研究了电场调制效应对氧化层电流弛豫谱(Oxide CurtentRelaxation Spectroscopy)——简称 OCRS的影响.给出了精确的 OCRS谱函数及其各级近似表述式;给出了确定陷阱参数(俘获截面,荷心及面密度)的精确公式及各类简化式;给出了各类近似成立的直观实验判据式.对实验结果进行了电场修正,得到了更为满意的结果.     

差值取样数对氧化层电流弛豫谱分辨率与灵敏度的影响＊

本文讨论了差值取样数对氧化层电流弛豫谱(OCRS)分辨率与灵敏度的影响,给出了差值取样数七在实际分析过程中的最佳选择原则,研究了用计算机技术改善氧化层电流弛豫谱的灵敏度问题。     

超薄栅MOS结构恒压应力下的直接隧穿弛豫谱

随着器件尺寸的迅速减小,直接隧穿电流将代替FN电流而成为影响器件可靠性的主要因素.根据比例差值算符理论和弛豫谱技术,针对直接隧穿应力下超薄栅MOS结构提出了一种新的弛豫谱--恒压应力下的直接隧穿弛豫谱(DTRS).该弛豫谱保持了原有弛豫谱技术直接、快速和方便的优点,能够分离和表征超薄栅MOS结构不同氧化层陷阱,提取氧化层陷阱的产生/俘获截面、陷阱密度等陷阱参数.直接隧穿弛豫谱主要用于研究直接隧穿注入的情况下超薄栅MOS结构中陷阱的产生和复合,为超薄栅MOS结构的可靠性研究提供了一强有力工具.     

超薄栅MOS结构恒压应力下的直接隧穿弛豫谱

随着器件尺寸的迅速减小 ,直接隧穿电流将代替 FN电流而成为影响器件可靠性的主要因素 .根据比例差值算符理论和弛豫谱技术 ,针对直接隧穿应力下超薄栅 MOS结构提出了一种新的弛豫谱——恒压应力下的直接隧穿弛豫谱 (DTRS) .该弛豫谱保持了原有弛豫谱技术直接、快速和方便的优点 ,能够分离和表征超薄栅 MOS结构不同氧化层陷阱 ,提取氧化层陷阱的产生 /俘获截面、陷阱密度等陷阱参数 .直接隧穿弛豫谱主要用于研究直接隧穿注入的情况下超薄栅 MOS结构中陷阱的产生和复合 ,为超薄栅 MOS结构的可靠性研究提供了一强有力工具 .     

关于薄SiO_2的高场弛豫电导与击穿机制的研究

薄SiO_2的早期高场弛豫电导与原生电子陷阱的俘获及新生正电荷的产生密切相关;中、后期的电导弛豫与新生电子陷阱的产生-俘获过程相关,新生电子陷阱遵从单分子产生规律.一个“新生电子陷阱-新生SiO_2/Si_2O,界面陷阱相关击穿”模型,用以解释薄SiO_2的后期弛豫电导突变失控和不可逆转的失效——脉冲热击穿.     

利用弛豫谱技术对界面陷阱密度和其能量分布的研究

基于界面陷阱的定义 ,通过分别对亚阈值摆幅漂移和亚阈区栅电压漂移采用弛豫谱技术有效地提取了1.9nm MOS结构中的界面陷阱密度和它的能量分布 .发现这两种方法提取的界面陷阱密度的能量分布是自洽的 ,同时也与文献报道的 DCIV等方法的结果是一致的 .与其它的提取方法相比 ,采用弛豫谱技术的这两种方法更加简单和方便 .     

利用弛豫谱技术对界面陷阱密度和其能量分布的研究

基于界面陷阱的定义,通过分别对亚阈值摆幅漂移和亚阈区栅电压漂移采用弛豫谱技术有效地提取了1.9nm MOS结构中的界面陷阱密度和它的能量分布.发现这两种方法提取的界面陷阱密度的能量分布是自洽的,同时也与文献报道的DCIV等方法的结果是一致的.与其它的提取方法相比,采用弛豫谱技术的这两种方法更加简单和方便.     

GaN HFET加应力后的虚栅和亚稳态能带

使用双曲函数拟合描绘出从应力偏置转换到测试偏置后，不同时刻的表面电势、电场强度和电场梯度的动态弛豫过程。计算出这一偏置转换引发的亚稳态能带。亚稳态能带的弛豫过程描绘出沟道夹断后的异质结充电过程。亚稳态能带计算证明外沟道中的强场峰、电场梯度峰、能带谷和能带峰都由局域电子气电荷引起，局域电子气的慢输运行为延缓了异质结充电过程，拉长了偏置转换中的亚稳态能带转换弛豫。当负应力栅压向空间电荷区注入电子给陷阱充电时，陷阱电荷叠加在局域电子气电荷上，强化了能带畸变和电流崩塌。由此提出涉及异质结能带转换的新虚栅模型。在新虚栅模型下异质结能带变化引发的电子气状态变化比旧虚栅模型中的电子耗尽作用强得多，据此能够解释从漏控DLTS测得的外沟道陷阱密度比栅控DLTS测得的内沟道陷阱密度大1～2个数量级的实验结果。使用涉及能带转换的新虚栅模型讨论了GaN HFET研究中的电流崩塌、3 mm场效应管及可靠性难题。提出二维异质结构用异质结鳍来研制场效应管的新课题。     

差值取样谱函数定理及其在研究MOS陷阱弛豫效应方面的应用

本文利用Rolle定理证明了一个差值取样谱函数定理.阐明了,只要陷阱弛豫原函数满足这个定理的必要条件,则其差值取样转换函数——弛豫谱函数就一定具有谱峰特征.这个定理也为差分取样谱技术提供了相应的数学模型。给出了几个例证.     

聚合物光折变材料聚乙烯咔唑的陷阱态研究

利用热激电流(TSC)技术测量了聚合物光折变材料聚乙烯咔唑(PVK)的退极化电流曲线,获得了热激弛豫过程的活化能。发现聚乙烯咔唑材料的热激退极化电流曲线共有两个峰,低温峰位于338 K,对应的活化能约0.6 eV,高温峰位于417 K,对应的活化能范围在0.53~1.00 eV,在0.77 eV处呈现最大值,陷阱密度极大值为5.7×1013cm-3。同时证明了低温峰是源于偶极子退取向弛豫,高温峰则来自于陷阱中空穴的热释放。     

Breakdown voltage improvement for thin-film SOI power MOSFET's by aburied oxide step structure

Numerical simulations are performed to demonstrate that a new SOI power MOSFET structure, namely buried oxide step structure (BOSS), introduces a high electric field peak near the buried oxide step and that this peak reduces the height of the other electric field peaks within thin silicon layer. The relaxation of these peaks results in higher breakdown voltages at much higher impurity concentrations than those in the conventional structure     

利用直接隧穿弛豫谱技术对超薄栅MOS结构中栅缺陷的研究

给出了超薄栅MOS结构中直接隧穿弛豫谱(DTRS)技术的细节描述,同时在超薄栅氧化层(＜3nm)中给出了该技术的具体应用.通过该技术,超薄栅氧化层中明显的双峰现象被发现,这意味着在栅氧化层退化过程中存在着两种陷阱.更进一步的研究发现,直接隧穿应力下超薄栅氧化层(＜3nm)中的界面/氧化层陷阱的密度以及俘获截面小于FN 应力下厚氧化层(＞4nm)中界面/氧化层陷阱的密度和俘获截面,同时发现超薄氧化层中氧化层陷阱的矩心更靠近阳极界面.     

利用直接隧穿弛豫谱技术对超薄栅MOS结构中栅缺陷的研究

给出了超薄栅MOS结构中直接隧穿弛豫谱(DTRS)技术的细节描述,同时在超薄栅氧化层(＜3nm)中给出了该技术的具体应用.通过该技术,超薄栅氧化层中明显的双峰现象被发现,这意味着在栅氧化层退化过程中存在着两种陷阱.更进一步的研究发现,直接隧穿应力下超薄栅氧化层(＜3nm)中的界面/氧化层陷阱的密度以及俘获截面小于FN 应力下厚氧化层(＞4nm)中界面/氧化层陷阱的密度和俘获截面,同时发现超薄氧化层中氧化层陷阱的矩心更靠近阳极界面.     

金属—氮氧化硅—硅电容在本征击穿前的漏电特性

本文的实验结果表明，从６ＭＶ／ｃｍ到１４ＭＶ／ｃｍ的外加电场范围内，在氮氧化硅膜的漏电机理与常规方法生长的氧化硅的不同，氮氧化硅膜漏电机理可分为三种，当电小于８ＭＶ／ｃｍ时，漏电是由于注入电子的直接隧穿填充绝缘体中的浅陷阱而引起的。在高场范围（＞１０ＭＶ／ｃｍ）Ｆｏｗｌｅｒ－Ｎｏｒｄｈｅｉｍ（ＦＮ）效应占支配地位。这些机理与介质膜的制备条件有关。在中等电场区域，注入电子能通过ＦＮ电流和直接隧穿到达     

Temperature and voltage dependences of the capture and emission times of individual traps in high-k dielectrics

Quantized threshold voltage (VTH) relaxation transients are observed in nano-scaled field effect transistors (FETs) after bias temperature stress. The abrupt steps are due to trapping/detrapping of individual defects in the gate oxide and indicate their characteristic emission/capture times. Individual traps are studied in n-channel SiO₂/HfSiO FETs after positive gate stress to complement previous studies performed on SiO(N). Similarly to single SiO(N) traps, strong thermal and bias dependences of the emission and capture times are demonstrated. The high-k traps have a higher density but a reduced impact on VTH due to their separation from the channel.     

Lateral distribution of hot-carrier-induced interface traps inMOSFETs

The spatial profiles of hot-carrier-induced interface traps in MOSFETs with abrupt arsenic junctions and oxide thickness of 10-38 nm are determined using charge pumping both in the conventional manner and with a modified constant-field approach. For the thinnest oxides the damage is highly localized in a very sharp peak that is located inside the drain at the point of maximum lateral electric field. In thicker oxides, the damage peak is broader and is shifted toward the edge of the drain junction. Two-dimensional device simulations using the measured profiles are in qualitative agreement with measured I-V characteristics after degradation. However, the magnitude of the predicted degradation is underestimated, suggesting that significant electron trapping occurs also     

Analysis of CMOS transistor instabilities

A method for separation and calculation of gate oxide and surface state charges in CMOS transistors have been developed, leading to a significant improvement of the analysis of CMOS integrated circuit instabilities. In order to demonstrate the usefulness of the method, an analysis of instabilities in transistors subject to high electric field and high temperature-bias stress has been carried out. Four instability mechanisms associated with high electric field stress are observed. Successively we consider a positive gate oxide charge increase due to hole tunneling from the silicon valence band into oxide hole traps (in case of negative gate bias), electron tunneling from oxide electron traps into the oxide conduction band (in case of positive gate bias), and a surface state charge increase due to tunneling of electrons from the metal to the silicon (in case of negative gate bias) or from the silicon to the metal (in case of positive gate bias). In addition instabilities associated with high temperature-bias stress are observed: drift of mobile ions in the gate oxide, increase of positive trapped charge in the gate oxide and simultaneous increase of the surface state and negative gate oxide charges.     

Relaxation effects in NMOS transistors after hot-carrier stressing

Aging studies on NMOS transistors with dry oxides at room temperature have revealed that the creation of interface traps and the trapping of positive charge in the oxide associated with hot-electron effects are not permanent, but can be reversed to some extent if the transistor drain is grounded and left for some time. The relaxation is a substantial fraction of the original degradation at low degradation values and suggests that there is an annealing of some of the traps created by stressing. This annealing follows first-order kinetics for both created interface traps and trapped oxide charge, and is characterized by relaxation times τrof 600-900 s.     

Base current relaxation transient in reverse emitter-base biasstressed silicon bipolar junction transistors

The base current relaxation transient following reverse emitter-base (EB) bias stress and its effect on time-to-failure (TTF) determination are examined in self-aligned and nonself-aligned silicon bipolar junction transistors (BJTs) with thermal and deposited base oxide. A quantitative model indicates that the transient is due to a reduction of the stress-generated positive charge trapped in the oxide layer near the emitter-base junction due to holes tunneling from oxide hole traps to silicon band states or SiO₂/Si interface traps. The neutral oxide hole traps may be quickly recharged through hole tunneling or hole injection into the oxide during further reverse-bias stress. A delay time of ~10^-3 s was observed after the termination of stress before base current relaxation begins, which affects the extraction of the ac operation TTF from dc stress measurements