Implementation of Side Effects in Thermal Characterization of RGB Full-Color LEDs

This letter presents a useful thermal-characterization method for RGB full-color light-emitting diodes (LEDs). The superposition method was employed to calculate thermal resistances of a high-power RGB full-color LED package to implement the side effect. Independent driving of a single chip in the RGB package clearly exhibited a side effect on the other two chips. It was shown that driving a red chip at 350 mA, current induced 4.8degC temperature rise for the green and blue chips, which is about 30% of the temperature rise in the red chip itself. A thermal-resistance-coupling matrix was structured and used for the calculation of the junction temperatures of the chips. It was demonstrated that the superposition method can be employed for an accurate prediction of the junction temperature rises for the RGB full-color LED package.     

具有微米/纳米复合粗化ITO的GaN基LED

Three types of textured indium-tin-oxide （ITO） surface, including nano-texturing and hybrid micro/nano-texturing with micro-holes （concave-hybrid-pattem） or micro-pillars （convex-hybrid-pattern）, were applied to GaN-based light-emitting diodes （LEDs）. The nano-texturing was realized by maskless wet-etching, and the micro-texturing was achieved by standard photolithography and wet-etching. Compared to LED chips with flat ITO surface, those with nano-pattern, concave-hybrid-pattern, and convex-hybrid-pattern exhibit enhancement of 11.3%, 15.8%, and 17.9%, respectively, for the light-output powers at 20 mA. The electrical performance has no degradation. Moreover, the convex-hybrid-pattern show higher light-output efficiency under small injection current, while the concave-hybrid-pattern exhibit better light-output efficiency at large injection current. The light- extraction efficiency is simulated by use of two-dimensional finite difference time domain method, and the numer- ical results are consistent with the experiments.     

A novel robust and low cost chips package and its thermalperformance

In an attempt to provide a high density memory solution, especially for workstation and PC servers, a stack chips package (SCP) has been developed. The major characteristics of SCP are as follows: (1) SCP contains a plurality of both memory chips and lead frames within a molded plastic package; (2) chip selection is made through the wire bonding option, resulting in the package with a memory capacity twice or four times that of monolithic chip; (3) plural lead frames are electrically interconnected all at once, using metal solders electroplated on the lead frame surface; and (4) SCP is found reliable and cost competitive when compared to other stack packages because it basically adopts the molded plastic packaging technology as well as the metal solder interconnection method. As electrical interconnection methods, both a fluxless soldering joint of Ag/Sn and a high-pressure mechanical joint of Ag were evaluated extensively and they successfully provided a reliable electrical conduction path without any signal degradation. Temperature cycle test and pressure cooker test were proved not to produce any micro cracks across the joint. The thermal performance of SCP was simulated by a thermal model based on finite element method (FEM) and also experimentally verified, showing good agreement within 10% deviation from simulated value. 128M SCP showed better thermal performance than stacked two TSOP's because one chip could serve as a heat sink while the other chip is activated and thermal conduction path through the lead frame is short     

Failure and degradation mechanisms of high-power white light emitting diodes

The investigation explores the factors that influence the long-term performance of high-power 1 W white light emitting diodes (LEDs). LEDs underwent an aging test in which they were exposed to various temperatures and electrical currents, to identify both their degradation mechanisms and the limitations of the LED chip and package materials. The degradation rates of luminous flux increased with electrical and thermal stresses. High electric stress induced surface and bulk defects in the LED chip during short-term aging, which rapidly increased the leakage current. Yellowing and cracking of the encapsulating lens were also important in package degradation at 0.7 A/85 °C and 0.7 A/55 °C. This degradation reduced the light extraction efficiency to an extent that is strongly related to junction temperature and the period of aging. Junction temperatures were measured at various stresses to determine the thermal contribution and the degradation mechanisms. The results provided a complete understanding of the degradation mechanisms of both chip and package, which is useful in designing highly reliable and long-lifetime LEDs.     

Improvement of emission efficiency and color rendering of high-power LED by controlling size of phosphor particles and utilization of different phosphors

White light can be produced by a combination of red, green and blue emitting diode chips or by the combination of a single diode chip with phosphors. Presently, more single chip white light-emitting diodes (LEDs) than multi-chip one are used because of their low cost, easily controlled circuitry, ease of maintenance and favorable luminescence efficiency. Since phosphors must be used as light converting materials in a single diode chip to obtain the desired emission, this study considers the problems encountered in using phosphors in LEDs. The proper application of phosphors in the package of LED can improve its efficiency, color rendering and thermal stability of luminescence. For example, a uniform size distribution of phosphors with red, green and blue emission helps to improve luminescence efficiency by preventing cascade excitation; the change in color with temperature can be overcome by counter-balancing red-shifting and blue-shifting phosphors; larger particles help to ensure the high efficiency of high-power LEDs, and costs can be reduced by using small particles size in low-power LED packaging because allows less phosphor to be used to obtain a particular efficiency.     

功率型LED芯片的热超声倒装技术

结合功率型GaN基蓝光LED芯片的电极分布,在硅载体上电镀制作了金凸点,然后通过热超声倒装焊接技术将LED芯片焊接到载体硅片上.结果表明,在合适的热超声参数范围内,焊接后的功率型LED光电特性和出光一致性较好,证明了热超声倒装焊接技术是一种可靠有效的功率型光电子器件互连技术.     

Chip package interaction for LED packages

Solid-state lightings (SSL) rapidly penetrate the global illumination market because of the energy efficiency and the reliability. The energy efficiency can be easily evaluated but the reliability is not convenient to be estimated. Among several reliability issues, a LED chip level's reliability could be a difficult problem because chip failures related to electromigration phenomenon are hard to be detected in the early stages. In order to remove potential leakage LEDs in modules, additional screening method is necessary to be performed occasionally. In this study, chip package interaction (CPI) for LED packages was investigated in order to estimate stresses of the LED chip in the module level. This methodology would help LED manufacturers to perform a robust design of LED packages in terms of the LED chip reliability. The electromigration is related to metal diffusion, which belongs to a creep phenomenon. As the creep strain is a function of temperature, stress and time, quantifying stresses in the metal layers of the LED die can be useful information for LED manufacturers to make an engineering decision in the early stages of manufacturing.     

Thermal/luminescence characterization and degradation mechanism analysis on phosphor-converted white LED chip scale packages

According to the requirements on minimizing the package size, guaranteeing the performance uniformity and improving the manufacturing efficiency in LEDs, a Chip Scale Packaging (CSP) technology has been developed to produce white LED chips by impressing a thin phosphor film on LED blue chips. In this paper, we prepared two types of phosphor-converted white LED CSPs with high color rendering index (CRI > 80, CCT ~ 3000 K and 5000 K) by using two mixed multicolor phosphor materials. Then, a series of testing and simulations were conducted to characterize both short- and long-term performance of prepared samples. A thermal analysis through both IR thermometry and electrical measurements and thermal simulation were conducted first to evaluate chip-on-board heat dissipation performance. Next, the luminescence mechanism of multicolor phosphor mixtures was studied with the spectral power distribution (SPD) simulation and near-field optical measurement. Finally, the extracted features of SPDs and electrical current-output power (I-P) curves measured before and after a long-term high temperature accelerated aging test were applied to analyze the degradation mechanisms. The results of this study show that: 1) The thermal management for prepared CSP samples provides a safe usage condition for packaging materials at ambient temperature; 2) The Mie theory with Monte-Carlo ray-tracing simulation can be used to simulate the SPD of Pc-white LEDs with mixed multicolor phosphors; 3) The degradation mechanisms of Pc-white LEDs can be determined by analyzing the extracted features of SPDs collected after aging.     

Degradation mechanisms of high-power white LEDs activated by current and temperature

This paper presents a study of the degradation mechanisms that limit the reliability of commercially-available white LEDs. Purely thermal stress and biased iso-thermal stress were carried out for several thousands hours on 1W-power LEDs, produced by a leading manufacturer. Results reveal that temperature and operating current have different roles in determining the optical degradation of these devices: (i) pure thermal stress induces a short-term optical power decay, strictly correlated to the decrease in the reflectivity of the package/reflector system and with no effects on the electrical characteristics of the blue chip; the activation energy of thermally-induced degradation is equal to 1.8 eV; (ii) constant current stress induces a long-term degradation process, with a degradation rate which is strongly dependent on the stress current level. In this latter case, optical degradation is ascribed to the degradation of the blue semiconductor chip: details are provided through the analysis of forward voltage and wavelength shift during stress time.     

具有纳米级结构出光面的AlGaInP基发光二极管

研究了一种利用金属自组装纳米掩膜和ICP刻蚀对AlGaInP基发光二极管(LED)表面进行粗化的技术,使光输出得到了提高.粗化了的AlGaInP基LED比常规的AlGaInP基LED,光强提高了27%,光功率提高了12.6%,实验结果具有可重复性.可以进一步优化Au颗粒的周期和分散程度,提高AlGaInP基LED的提取效率.     

Thermal characteristics and fabrication of silicon sub-mount based LED package

In this paper, the cost of a light emitting diode (LED) package is lowered by using a silicon substrate as the base attached to the chip, in contrast to the conventional chip-on-board (COB) package. In addition we proposed an LED package with a new structure to promote reliability and lifespan by maximizing heat dissipation from the chip. We designed an LED package combining the advantages of COB based on conventional metal printed circuit board (PCB) and the merits of a silicon sub-mount as a substrate. When an input current 500–1000 mA was applied, the fabricated LED exhibited the light output of approximately 112 lm/W at 29 W. We also measured and compared the thermal resistance of the sub-mount package and conventional COB package. The measured thermal resistance of the sub-mount package with a reflective film of Ag and the COB package were 0.625 K/W and 1.352 K/W, respectively.     

Degradation of silicone in white LEDs during device operation: a finite element approach to product reliability prediction

Silicone, which is a very common material for Light Emitting Diode (LED) packaging components like lens, casting and housing, undergoes degradation during high temperature and current operation. Indeed, electrical and optical losses cause material shrinkage and hardening, inducing mechanical stress within the LED assembly, which can end up into crack formation in silicone. In order to evaluate the reliability of LED package regarding the silicone crack, a degradation material model is developed, which is based on the experimental investigation of the mechanical properties of silicone during degradation. A thermo-optical model is used for the calculation of the temperature distribution in the device during steady-state operation. The crack reliability model, which is build combining the stress simulation results based on finite element approach and the visual inspection of the corresponding LED package during steady-state operation, is used to estimate the package lifetime depending on the operation conditions.     

LED芯片损坏和缺陷识别

对LED芯片生产过程中出现的缺陷和损坏现象进行了分析和归类.提取芯片图像暗点数、边缘点数、块数、面积和亮点数5种与芯片位置无关的图像特征,通过建立正态分布模型,并基于最小风险贝叶斯决策构建分类器对各种缺陷和损坏芯片进行识别.实验表明该方法具有较高的精度和效率,能够满足LED芯片外观检测的需要.

Abstract：

The defective and damaged LED chips appearing in the production process were analyzed and classified. The five kinds of image features: dark pixel number, edge pixel number, blocks number, area and bright pixel number which are irrelevant to the chip position were extracted from the chip image. The minimum risk Bayesian classifier which can recognize various kinds of defective and damaged chips was established based on normal distribution model. Experimental results show that this method has high accuracy and efficiency and can meet the requirements of the appearance detection of LED chips.     

A Packaging Solution for Optically Testing Wire-Bonded Chips

In this paper, we describe the design and the experimental characterization of a packaging technique for backside optical testing of chips requiring wirebonding. Optical testing methods, based either on the collection of spontaneous hot-carrier photoemission or on laser stimulation, require an optical access to the active area of the circuit through the backside of the chip, while still providing mechanical support to the thinned die (very fragile), heat sinking capability, power and electrical signals. The proposed package fulfils all these requirements and it can hence be used for picosecond imaging for circuit analysis/time resolved emission measurements, emission microscopy investigations, laser voltage probe, thermal laser stimulation, photoelectric laser stimulation, and other failure analysis methods that require optical access to the transistor level through the silicon backside. The advantages of the new package are its versatility (it can fit different chip sizes), easy handling, low cost, and the fact that it is designed for optical testing and not just for electrical testing. We successfully used the proposed package for optically test chips in advanced complementary metal–oxide–semiconductor technologies (65 nm): measurements at low voltage are possible thanks to the proposed package.      

大功率集成封装白光LED模组的散热研究

采用有限元分析软件ANSYS,分别对基于均温基板和金属芯印刷电路板结合太阳花散热器的100 W的大功率集成封装白光LED进行了热分析。结果发现:(1)相比金属芯印刷电路板,均温基板提高了LED芯片的均温性,可使每个LED芯片的温度分布一致,且每个芯片的最高温度比最低温度仅高1.1℃,避免了局部热点,从而提高了大功率集成封装白光LED的可靠性,保证了它的寿命。(2)太阳花散热器非常适合大功率集成封装白光LED模组的散热。因此对于大功率集成封装白光LED模组而言,均温基板结合太阳花散热器是一种有效的散热方式。     

基于MEMS的LED芯片封装光学特性分析

本文提出了一种基于MEMS的LED芯片封装技术,利用体硅工艺在硅基上形成的凹槽作为封装LED芯片的反射腔.分析了反射腔对LED的发光强度和光束性能的影响,分析结果表明该反射腔可以提高芯片的发光效率和光束性能;讨论了反射腔的结构参数与芯片发光效率之间的关系.最后设计了封装的工艺流程.利用该封装结构可以降低芯片的封装尺寸,提高器件的发光效率和散热特性.     

LED典型失效机理

鉴于LED芯片尺寸较小,散热和成本的压力,LED封装难度很大,暴露出来的可靠性问题也最多。LED失效后,往往能够通过电参数测试、内部形貌分析、剖面检查、SEM检查等方法暴露失效现象、分析出失效机理,最终提出改进意见,提高器件的良品率。根据失效分析实例剖析了LED典型失效机理:LED芯片缺陷和腐蚀;LED芯片粘结用导电胶腐蚀、使用不当导致开路或短路;LED芯片金丝键合损伤;LED封装结构设计不当,导致机械应力集中损伤芯片;LED器件使用不当——过流烧毁、ESD损伤、焊接不良或焊料迁移。并分别提出了相应的改进建议。     

大功率集成LED光转换光源的研制

介绍了一种应用远程激发技术的大功率集成LED光转换光源,通过使用固晶区无绝缘层的镜面铝基板进行集成封装蓝光LED光源,即COB光源。所制蓝光光源与远程激发荧光粉模块结合制成LED光转换光源。利用镜面铝基板的高导热系数,解决多种LED封装形式下芯片点亮温度过高、光源衰减快的问题。采用LED荧光高分子模块与蓝光芯片分离结合的远程激发技术制成白光光源,解决荧光粉分布不均、热老化、色偏移问题。通过与传统粉胶封装方式制得的大功率集成LED器件比较测试,该种光源具有防眩光、光色均匀度高、长寿命、节能和环保的优点,从而具有更广泛的用途。     

Early experience with in situ chip-to-chip alignment characterization of Proximity Communication flip-chip package

Proximity Communication (PxC) facilitates the integration of VLSI chips in a package using near-field capacitive coupling between chips, eliminating the need for solder or wires for I/O at the chip-to-chip interface. PxC provides chip-to-chip interconnect with bandwidth density and energy per bit similar to on-chip I/O, enabling system on a chip performance within a package. We have built early packages to explore assembly concepts and developed test methods for verification of the PxC design space. This package started with an adhesively-bonded three-chip subassembly of two Island chips and one Bridge chip. The two outer Island chips were reflowed to an alumina ceramic substrate. In the resulting package, communication between chips was achieved using PxC from Island to Bridge and then from the Bridge to the other Island. We demonstrated the ability to detect the X, Y, and Z chip-to-chip relative location and the ability to steer PxC data to optimize signal integrity within the package. This paper describes the first demonstration of active monitoring of chip-to-chip alignment during thermal cycling, in a PxC-enabled package. Leveraging this work, future packages will better exploit PxC benefits such as free-space electrical interconnect and re-workability of multi-chip modules.     

高亮度LED芯片的反射型电流阻挡层设计与实现

基于光学传输理论矩阵,设计制作SiO2和Ti3O5交替生长的分布式布拉格反射(DBR)结构作为LED芯片的电流阻挡层,并采用电感耦合等离子体(ICP)刻蚀技术在电流阻挡层处形成沟槽结构,以解决困扰LED器件效率提高的电流扩散及金属电极降低出光效率的问题。实验结果表明,采用这种结构的LED芯片能将亮度提高5%以上,而LED芯片的正向电压基本维持不变。这种反射型电流阻挡层结构能够很好地改善大尺寸LED芯片的电流扩散,有效地提高LED芯片的出光效率。