线性容差电路的K故障模糊屏蔽定位

研究了线性电路的等输入／等输出Ｋ故障屏蔽方法在容差情况下的应用，提出了故障隶属函数，用以定位故障元件或模糊故障集，从而大幅度地降低了故障与容差之间的模糊性，提高了Ｋ故障屏蔽法的实用性。对算法进行了详尽的研究，测后计算量小。     

容差模拟电路故障模糊诊断方法及其实现

提出了基于SOFM神经网络的容差模拟电路故障模糊诊断方法及其实现。该方法将网络撕裂法和SOFM神经网络相结合进行故障测试．并运用所设计的模糊逻辑神经网络系统判断测试条件，定位容差模拟电路的子网络级故障。仿真试验表明该方法故障定位精确度高。撕裂迅速，有利于大规模容差模拟电路故障诊断的实现。     

电子电路故障诊断的一种新方法

本文在文献[1,2]的基础上提出了一种诊断大规模容差子网络级故障的新方法－交叉撕裂诊断法。文中首先论叙f≤3的撕裂准则，然后，应用区间分布法对容差子网进行故障定位，这种方法可以用于通信网络中的电子电路故障诊断。     

容差网络故障诊断中的误差分析

在用双向能量正交法对网络进行故障诊断时，网络的空差会影响结果的准确性。本文分析了由网络容差所造成的误差，给出容差所造成的能量误差的一个上界。在容差统计特性已知的情况下，对判别其偏差是否由故障引起的一个概率上的估计。     

k故障的ζ可诊性

本文利用摄动理论和流形距离，首次提出了容差电路ｋ故障可诊条件。该条件定量地描述了容差电路可诊性是如何依赖于电路标称数据和可测得信号的。文章还指出了该可诊条件为合理使用定位故障的极值法提供了理论基础。     

模拟电路故障诊断的新故障字典法

基于节点电压灵敏度,将文献[1]中的线性无容差电路的故障字典法推广到可以诊断容差模拟电路和非线性电路软故障的新故障字典法。讨论了该方法的原理和字典的建立方法,给出了仿真实例。     

容差电路的K故障屏蔽方法研究

本文对线性电路的等输入／输出K故障屏蔽方法在容差情况下的应用进行了详尽的研究，所提两种K故障模糊屏蔽算法，计算量小，诊断速度快，故障与容差之间的模糊性低，可信度高。     

一种诊断故障的新的测试节点选择法：混叠集分析法

本文根据存在容差时电路的特点,对现有的故障字典法作了改进。提出了一种能有效地解决有容差情况下最佳测试节点选取问题的新方法——混叠集分析法。对这种新方法进行了理论分析,提出了相应的算法,并在计算机上对实例进行仿真验证,证明该法是有效的。与基本的故障字典法相比,在很大程度上提高了诊断效率。     

非线性容差电路的故障诊断

文章着重讨论如何根据容差电路有限可及点上的电压测量，诊断其线性和（或）非线性元件故障，文章利用Ｇｒａｓｓｍａｎｎ流形中的子空间距离证明了ε－故障锥的存在，并由此导出容差干扰下的可诊性条件。为了区别非线性元件的自身故障与似故障。本文仔细分析了可及点电压变化阵的方向能量椭球，并提出了相对方向能量准则。仿真表明，该准则对容差影响是鲁棒的。     

κ故障的ξ可诊性

本文利用摄动理论和流形距离,首次提出了容差电路k故障可诊条件,该条件定量地描述了容差电路可诊性是如何依赖于电路标称数据和可测得信号的。文章还指出了该可诊条件为合理使用定位故障的极值法提供了理论基础。     

普遍故障下神经网络隐层冗余容错的分析与应用

隐层神经元冗余是提高神经网络容错性的一个有效的方法,在神经网络分类器的容错设计中,这一方法得到了良好的效果,对单故障可以做到完全容错.但是这一应用仅仅只能应用于输出层为硬限幅函数的前向网络,并且只证明了对网络中单故障有效.在实际应用中,网络中的各个节点和权值的故障往往是普遍存在的,因此本文提出了一种隐层冗余结构,对普遍故障存在下隐层神经元冗余容错方法做以评估,得出的结论是应用这种隐层神经元冗余结构可以减小网络的全局故障率;并提出了针对一般前向神经网络的实用的隐层神经元容错方法,这种方法可以有效地提高网络在普遍故障下的容错能力.     

基于遗传算法的容差模拟电路故障诊断

给出了用于模拟电路元件参数识别的多频传递函数法的过程,并对故障诊断方程的可解度进行了分析,在此基础上,将诊断方程的求解转化为非线性函数的优化问题,并运用改进的遗传算法来解决这个问题,算法实例表明该方法简化了故障诊断方程的求解过程,加速了容差电路故障元件的定位,有一定的应用价值。     

Performance analysis and fault tolerance of randomized routing on Clos networks

Beside universality and very low latency, Youssef's randomized self-routing algorithms [25] have high tolerance for multiple faults and more strikingly have the potential for fault tolerance without diagnosis. In this paper we study the performance of Youssef's routing algorithms for faulty Clos networks in the presence of multiple faults in multiple columns with and without fault detection. We show that with fault detection and diagnosis, randomized routing algorithms provide scalable, very efficient and fault tolerant routing mechanisms. Without fault detection and diagnosis, randomized routing provides good fault tolerance for faulty switches in either the first or the second column. The delays become large for faults in the third column or for faults in more than one column. In conclusion, randomized routing enables the system to run without periodic fault detection/diagnosis, and if and when the performance degrades beyond a certain threshold, diagnosis can be performed to improve the routing performance. This revised version was published online in June 2006 with corrections to the Cover Date.     

基于FPGA的功能域隔离电路设计

静态随机存储器(Static Random Access Memory, SRAM)型现场可编程门阵列（Field Programmable Gate Array, FPGA）广泛应用于航空航天系统中,但是高空中FPGA易受高能粒子影响造成配置出错,互联资源上发生的单点错误可能导致跨域故障,使芯片内多个模块同时失效。跨域故障可能导致电路中的工作模块与检错模块同时故障,使设备中存在不能被检测到的隐蔽故障。针对上述问题,提出在芯片上将不同功能的模块相互隔离,并通过约束实现模块间可信通信的故障隔离方法,将故障限定在单一模块内,防止多个模块同时失效,提高电路的容错能力。通过故障注入评估隔离设计前后的航空电子全双工交换式以太网（Avionics Full Duplex Switched Ethernet, AFDX）电路的各类故障发生率。实验结果证明隔离设计可以与电路原有的检错容错机制结合,将隐蔽故障的发生率降为原来的3%。     

Fault diagnosis and its prediction in wireless sensor networks using regressional learning to achieve fault tolerance

Due to the wide range of critical applications and resource constraints, sensor node gives unexpected responses, which leads to various kind of faults in sensor node and failure in wireless sensor networks. Many research studies focus only on fault diagnosis, and comparatively limited studies have been conducted on fault diagnosis along with fault tolerance in sensor networks. This paper reports a complete study on both 2 aspects and presents a fault tolerance approach using regressional learning with fault diagnosis in wireless sensor networks. The proposed method diagnose the different types of faulty nodes such as hard permanent, soft permanent, intermittent, and transient faults with better detection accuracy. The proposed method follows a fault tolerance phase where faulty sensor node values would be predicted by using the data sensed by the fault free neighbors. The experimental evaluation of the fault tolerance module shows promising results with R² of more than 0.99. For the periodic fault such as intermittent fault, the proposed method also predict the possible occurrence time and its duration of the faulty node, so that fault tolerance can be achieved at that particular time period for better performance of the network.     

三维片上网络故障及拥塞感知的容错路由器设计

 三维片上网络中路由器的输入端口和交叉开关出现故障,将严重影响整个网络的性能,因此文章提出了一种故障及拥塞感知的容错路由器.通过增加一个冗余的输入端口和旁路总线,不仅能实现对输入端口和交叉开关容错的目的,而且还能在没有端口故障的情况下使用冗余端口有效地解决拥塞问题.实验表明此容错机制能够使得网络在故障路由器多、拥塞严重的情况下,仍然保持良好的性能.     

Detecting, diagnosing, and tolerating faults in SRAM-based field programmable gate arrays: a survey

Topics related to the faults in SRAM-based field programmable gate arrays (FPGAs) have been intensively studied in recent research studies. These topics include FPGA fault detection, FPGA fault diagnosis, FPGA defect tolerance, and FPGA fault tolerance. This paper provides a guided tour to the approaches related to these topics. These include techniques, which are applied to the FPGA and others which have been recently introduced and can be applied to today's FPGAs.     

Online Fault Tolerance for FPGA Logic Blocks

Most adaptive computing systems use reconfigurable hardware in the form of field programmable gate arrays (FPGAs). For these systems to be fielded in harsh environments where high reliability and availability are a must, the applications running on the FPGAs must tolerate hardware faults that may occur during the lifetime of the system. In this paper, we present new fault-tolerant techniques for FPGA logic blocks, developed as part of the roving self-test areas (STARs) approach to online testing, diagnosis, and reconfiguration . Our techniques can handle large numbers of faults (we show tolerance of over 100 logic faults via actual implementation on an FPGA consisting of a 20 times 20 array of logic blocks). A key novel feature is the reuse of defective logic blocks to increase the number of effective spares and extend the mission life. To increase fault tolerance, we not only use nonfaulty parts of defective or partially faulty logic blocks, but we also use faulty parts of defective logic blocks in nonfaulty modes. By using and reusing faulty resources, our multilevel approach extends the number of tolerable faults beyond the number of currently available spare logic resources. Unlike many column, row, or tile-based methods, our multilevel approach can tolerate not only faults that are evenly distributed over the logic area, but also clusters of faults in the same local area. Furthermore, system operation is not interrupted for fault diagnosis or for computing fault-bypassing configurations. Our fault tolerance techniques have been implemented using ORCA 2C series FPGAs which feature incremental dynamic runtime reconfiguration     

Performance analysis of minimal path fault tolerant routing in NoC

Occurrence of faults in Network on Chip (NoC) is inevitable as the feature size is continuously decreasing and processing elements are increasing in numbers. Faults can be revocable if it is transient. Transient fault may occur inside router, or in the core or in communication wires. Examples of transient faults are overflow of buffers in router, clock skew, cross talk, etc.. Revocation of transient faults can be done by retransmission of faulty packets using oblivious or adaptive routing algorithms. Irrevocable faults causes non-functionality of segment and mainly occurs during fabrication process. NoC reliability increases with the efficient routing algorithms, which can handle the maximum faults without deadlock in network. As transient faults are temporary and can be easily revoked using retransmission of packet, permanent faults require efficient routing to route the packet by bypassing the nonfunctional segments. Thus, our focus is on the analysis of adaptive minimal path fault tolerant routing to handle the permanent faults. Comparative analysis between partial adaptive fault tolerance routing West-First, North-Last, Negative-First, Odd Even, and Minimal path Fault Tolerant routing (MinFT) algorithms with the nodes and links failure is performed using NoC Interconnect RoutinG and Application Modeling simulator (NIRGAM) for the 2D Mesh topology. Result suggests that MinFT ensures data transmission under worst conditions as compared to other adaptive routing algorithms.     

Fault Tolerance Analysis for Switched Systems Via Global Passivity

In this brief, we introduce the passivity theory into the fault tolerance analysis for switched systems. We propose a “global passivity” concept which means that the total energy stored by the switched system is less than the total energy supplied from the outside. The individual passivity of each mode is not required, and the stability of the system can be achieved via the global energy dissipativity in the presence of faults. We further provide a “periodic fault tolerant passivity” to check the fault tolerance easily. The obtained results are extended to feedback interconnected systems. A switched RLC circuit example is taken to illustrate the efficiency of the proposed results.