On chip–package stress interaction

In this paper, the interaction between chip and package is investigated. A series of experiments are conducted to investigate the effect of the package type on occurrence of passivation cracks in IC structures. Virtual prototyping is used to generate more accurate and efficient stress design rules for IC backend structures, in combination with packaging processes and geometry. The addressed failure mode of passivation cracks is found to depend on the package type or family: for exposed pad packages this failure mode is easier to occur. It is demonstrated that for successful development of IC backend structures and processes, it is essential to take into account the influence of the package in the earlier phase of IC backend development. The so-called integral design rules, accounting for all the major loading sources and history of the complete product creation process has to be used for the development of new generation semiconductors devices.     

Impact life prediction modeling of TFBGA packages under board level drop test

Reliability performance of IC packages during drop impact is critical, especially for handheld electronic products. Currently, there is no model that provides good correlation with experimental measurements of acceleration and impact life. In this paper, detailed drop tests and simulations are performed on TFBGA (thin-profile fine-pitch BGA) and VFBGA (very-thin-profile fine-pitch BGA) packages at board level using testing procedures developed in-house. The packages are susceptible to solder joint failures, induced by a combination of PCB bending and mechanical shock during impact. The critical solder ball is observed to occur at the outermost corner solder joint, and fails along the solder and PCB pad interface. Various testing parameters are studied experimentally and analytically, to understand the effects of drop height, drop orientation, number of PCB mounting screws to fixture, position of component on board, PCB bending, solder material, etc. Drop height, felt thickness, and contact conditions are used to fine-tune the shape and level of shock pulse required. Board level drop test can be better controlled, compared with system or product level test such as impact of mobile phone, which sometimes has rather unpredictable results due to higher complexity and variations in drop orientation. At the same time, dynamic simulation is performed to compare with experimental results. The model established has close values of peak acceleration and impact duration as measured in actual drop test. The failure mode and critical solder ball location predicted by modeling correlate well with testing. For the first time, an accurate life prediction model is proposed for board level drop test to estimate the number of drops to failure for a package. For the correlation cases studied, the maximum normal peeling stresses of critical solder joints correlate well with the mean impact lives measured during the drop test. The uncertainty of impact life prediction is within ±4 drops, for a typical test of 50 drops. With this new model, a failure-free state can be determined, and drop test performance of new package design can be quantified, and further enhanced through modeling. This quantitative approach is different from traditional qualitative modeling, as it provides both accurate relative and absolute impact life prediction. The relative performance of package may be different under board level drop test and thermal cycling test. Different design guidelines should be considered, depending on application and area of concern.     

Advances in Vapor Pressure Modeling for Electronic Packaging

Two advanced techniques have been developed for modeling vapor pressure within the plastic IC packages during solder reflow. The first involves the extension of the "wetness" technique to delamination along multimaterial interface and during dynamic solder reflow. Despite its simplicity, this technique is capable of offering reliable and accurate prediction for packages with high flexural rigidity. For packages with low flexural rigidity, the new "decoupling" technique that integrates thermodynamics, moisture diffusion, and structural analysis into a unified procedure has been shown to be more useful. The rigorous technique has been validated on both leadframe-based as well as laminate-based packages. With high accuracy and computational efficiency, these dynamic modeling tools will be valuable for optimization of package construction, materials, and solder reflow profile against popcorn cracking for both SnPb and Pb-free solders     

Prediction of interfacial delamination in stacked IC structures using combined experimental and simulation methods

Interfacial delamination is an often-observed failure mode in multi-layered IC packaging structures, which will not only influence the yield of wafer processes, but also have direct impact on the packaging reliability. The difference in coefficient of thermal expansion, together with thermal and thermal–mechanical loading are the main driving forces for interfacial delamination. First of all, this type of delamination is considered as a mixed mode of failure at the material interfaces. Hence, at least two stress components are needed to predict its occurrence. However, due to the singular stress field at the interface, one could hardly obtain the correct stresses at the interface. Therefore, a combined experimental–numerical method is used to investigate the initiation and propagation of the interface delamination. The purpose of the experimental shear and tensile tests is to measure the critical loads, at which delamination initiates. Then, a Finite Element (FE) model is constructed to convert the critical load into critical failure data for further numerical investigation. The FE model is so constructed that it reproduces the geometrical configurations of the tests. Due to the singular stress distribution at the interface, the calculated local stresses will be both mesh and residual-stiffness dependent. The influences of the FE parameters on the interface stresses are studied. After that, a progressive failure approach is, in combination with a group of failure criteria and the estimated local critical stresses, applied to predict the initiation and propagation of the delamination between epoxy mould compound and the passivation layer in the Integrated Circuit (IC) for three different package structures. The present method and the obtained results are valuable to determine design rules for IC packaging structures.     

LQFP和eLQFP热机械可靠性的有限元分析

封装形式的差异性对产品可靠性具有重要影响。基于有限元法,对比分析了薄型四方扁平封装(LQFP)和载体外露薄型四方扁平封装(eLQFP)在室温和回流焊温度下的翘曲、芯片和粘片胶的应力水平以及各材料界面应力分布。研究表明,LQFP的翘曲比eLQFP的大,但芯片和粘片胶上的最大应力无明显差别;eLQFP在塑封材料与芯片有源面界面的应力水平比LQFP的大;eLQFP在芯片与粘片胶界面、粘片胶与芯片载体界面的剪切应力比LQFP的大,但eLQFP在芯片与粘片胶界面、粘片胶与芯片载体界面的剥离应力比LQFP的小;eLQFP在塑封材料与芯片载体镀银区界面的应力水平高于LQFP的应力水平,由于塑封材料与镀银芯片载体的结合强度弱,eLQFP更易发生界面分层。     

基于方向场DFT和角点检测的指纹奇异点定位

提出了一种新的基于方向场离散傅里叶变换（DFT, Discrete Fourier transform）和角点检测的指纹奇异点定位算法。对方向场做DFT变换到频域处理能更好的压制噪声。通过角点提取、基于目标标注的聚类方法来定位指纹图像的奇异点。从方向场的极/零点模型出发,导出了若干新颖的性质,说明了奇异点和角点之间的关系。实验结果表明,奇异点定位精度有所提高,处理时间更短。     

Influence of temperature, humidity, and defect location ondelamination in plastic IC packages

The modified J-integral and the stress intensity factor based on linear elastic fracture mechanics can be applied to predict the growth of interfacial delamination in integrated circuit (IC) packages. One of the key parameters required is the interfacial fracture toughness. This paper describes the measurement of the interfacial fracture toughness as a function of temperature and relative humidity using a three-point bending test. The interfacial fracture toughness was found to decrease with temperature and relative humidity. It is proposed that delaminations propagate from very small voids or defects present at the interface. The effect of the location of these interfacial defects or cracks on delamination was studied. The IC package evaluated in this paper was an 80-pin quad flat package with a 0.2 mm defect or crack at the edge or at the center of the interface. It was found that as the temperature of the package was increased, the stress intensity factor of the edge crack was higher than that of the center crack. However, whether the edge crack will propagate first as temperature is increased depends on the ratio of mode II interface toughness to that of the mode I interface toughness. For the package under investigation, it was established that when this ratio is less than 2.69 the edge crack would propagate first, otherwise the center crack would. For small defects, it was found that the water vapor pressure developed at the interface did not have a significant effect on the value of the crack-tip stress intensity factor     

PBGA器件层间界面裂纹J积分分析

塑封电子器件在湿热环境下容易产生界面层裂失效已经得到广泛认同.针对PBGA塑封器件,采用J积分的方法,运用有限元分析软件计算和分析了模塑封材料(EMC)和硅芯片界面层间的裂纹.分析结果表明,当初始裂纹出现在硅芯片、芯片下材料层面和EMC材料交界处时,比较容易发生裂纹扩展.     

Predicting the process induced warpage of electronic packages using the P–V–T–C equation and the Taguchi method

A critical issue in the manufacturing of electronic packages is the warpage induced during the molding process as a result of differences in the shrinkage of the constituent materials. Package warpage causes serious problems such as the quality degradation of devices and yield loss in manufacturing processes. Loss of lead coplanarity happens due to package warpage and causes difficulty in device testing and surface mount assembly. Internal stresses associated with package warpage can also cause device failures such as die cracking, broken circuits and package cracking.Warpage in IC package has drawn intensive attention in the past. Although the effects of thermal shrinkage were extensively investigated in the literatures, the influence of the cure shrinkage on package warpage had received less attention. Accordingly, this study develops a numerical approach for generating more accurate predictions of the package warpage by taking the effects of both thermal shrinkage and cure shrinkage into account. A three-dimensional finite element model of the small outline package (TSOP) DBS-27P is constructed and the proposed numerical approach, which is based on the P–V–T–C (pressure–volume–temperature–conversion) equation and the CTEs (coefficients of thermal expansion) of the package materials, is employed to predict the warpage at each of its corners under various packaging processing conditions. Using the Taguchi method, the relative influences of the transfer pressure, the packing pressure, the mold temperature and the curing time on the degree of package warpage are identified and the optimal processing conditions are established. A series of experimental packaging trials are performed using the optimal processing conditions. It is found that the warpage of the actual package is in good agreement with that predicted numerically. Therefore, the accuracy of the proposed numerical approach is confirmed. Moreover, the results also demonstrate the capability of the Taguchi method to identify the optimal packaging processing parameters on the basis of a limited number of simulation runs.     

A compact multilayer IC package model for efficient simulation, analysis, and design of high-performance VLSI circuits

A multilayered integrated circuit (IC) package structure is composed of many signal layers, power layers, and ground layers. Particularly, the whole planes are assigned for the power and ground of the system. Accordingly, the generic circuit representation of such a complicated multilayer IC package becomes too complicated to efficiently evaluate its electrical performance. In this work, a novel compact package circuit model for the efficient simulation and analysis of such complicated IC packages is presented. Unlike the conventional models, current distributions within the package are modeled by introducing a compact partial plane circuit model. Thus, the proposed package model is much simpler than the conventional generic circuit models, while its accuracy is preserved. Thereby, today's complicated IC packages can be efficiently evaluated and analyzed. Its accuracy and efficiency are verified by benchmarking it with a conventional generic package circuit model; this conventional model may not be practical to use for package evaluation and analysis. It is then shown that the proposed model can be efficiently applied for the signal integrity verification of complicated IC packages and high-performance VLSI circuits.     

Electronic packaging solder joint reliablity assessment with a mechanics-based StrainGage methodology

It is essential to understand solder joint strains to improve package reliability. However, it is often difficult to measure the true solder joint strains directly. Strain gages have been increasingly used by component suppliers and original equipment manufacturers (OEMs) to indicate package mechanical stress levels. One of the most used strain gage locations is on the component side, right next to the package corner. A concern with this location alone is that the strain gages mounted close to the package pick up the local stress concentration near the package edges or corners. In this paper, appropriate strain gage locations are suggested based on mechanics principles and finite element simulation results. An analytical methodology is developed to determine the solder joint deformations from strain gage readings at various locations. This paper also proposes a new strain matching criterion. Most OEMs have been using maximum principal strain to match stress levels and define critical strain limits. A problem with maximum principal strain is that it does not indicate the direction along which the maximum bending occurs. Experimental data demonstrates that the new strain criterion has much better correlation to solder joint failure than maximum principal strains in various bend modes. The conclusions apply to any strain gage mounting metrology on packages attached to printed circuit boards.     

IC封装的声学检查技术

本文简要叙述了依赖于封装构造,可在引线框架下也能发现诸如爆米花裂纹等缺陷的IC声学检测技术。     

Crack Development in a Low-Stress PBGA Package due to Continuous Recrystallization Leading to Formation of Orientations with [001] Parallel to the Interface

Thermal cycling was imposed on plastic ball grid array (PBGA) packages with a small die, a package design that does not impose a large strain on solder joints. Less cracking was observed after 2500 cycles from 0°C to 100°C (with 10 min dwell times and 10 min ramps) than in a prior study with a higher-stress package design, so these samples were thermally cycled (TC) to 6400 cycles to investigate the relationship between cracks, microstructure, and grain crystal orientation. Cracked joint locations within the package were identified using the dye and pry method, indicating that cracks were most often found in joints near the perimeter of the die. Using orientation imaging microscopy (OIM), cracks were observed in many joints having a variety of dominant crystal orientations where the c-axis was between 0° and ∼50° from the package interface. Continuous recrystallization processes occurred and caused gradual rotations of initial orientations that reduced the angle between the c-axis and the package interface. While cracks were observed in joints with a variety of orientations, cracks were highly correlated with recrystallized grains having the [001] c-axis nearly parallel to the interface (“red” orientations) in those joints that did not initially have this orientation.     

New non-destructive laser ablation based backside sample preparation method

A new ultra-short pulse laser ablation based backside sample preparation method has been developed. This technique is contact-less, non-thermal, precise, repetitive and adapted to each type of material present in IC packages. Backside preparation examples are presented on a conventional DIL plastic package, a TSOP plastic package with an oversized silicon die and on a DIL ceramic package.     

Evaluation of solder joint reliability in flip-chip packages during accelerated testing

The microstructural investigation and thermomechanical reliability evaluation of the Sn-3.0Ag-0.5Cu solder bumped flip-chip package were carried out during the thermal shock test of the package. In the initial reaction, the reaction product between the solder and Cu mini bump of chip side was Cu₆Sn₅ intermetallic compound (IMC) layer, while the two phases which were (Cu,Ni)₆Sn₅ and (Ni,Cu)₃Sn₄ were formed between the solder and electroless Ni-P layer of the package side. The cracks occurred at the corner solder joints after the thermal shocks of 400 cycles. The primary failure mechanism of the solder joints in this type of package was confirmed to be thermally-activated solder fatigue failure. The premature brittle interfacial failure sometimes occurred in the package side, but nearly all of the failed packages showed the occurrence of the typical fatigue cracks. The finite-element analyses were conducted to interpret the failure mechanisms of the packages, and revealed that the cracks were induced by the accumulation of the plastic work and viscoplastic shear strains.     

An investigation into warpages,stresses and keep-out zone in 3D through-silicon-via DRAM packages

This paper aims to measure and simulate the warpages of 3D through-silicon via (TSV) die-stacked dynamic-random-access-memory (DRAM) packages during the manufacturing process. The related die stresses and keep-out zone (KOZ) for the stacked dies in the packages at room temperature are further calculated with the validated simulation model. The out-of-plane deformations (or warpages) of the packages from the full-field shadow moiré are documented under temperature loading and found consistent with those from finite-element method (FEM). The results of the stresses and KOZs at the proximity of a single TSV for each die in the package at room temperature are presented. It is found that the sizes of KOZs in four-die stacked DRAM packages with and without epoxy molding compound (EMC) at room temperature are dominated by the horizontal pMOS transistors and more than double the size in wafer-level die. The sizes of KOZs at each die are similar in this four-die stacked DRAM package, even though the stresses at each die are apparently different.     

A design technique for a high-gain, 10-GHz class-bandwidth GaAsMESFET amplifier IC module

A design procedure is proposed for a high-gain and wideband IC module, using stability analysis and a unified design methodology for ICs and packages. A multichip structure is developed using stability analysis and the requirements for stable operation are determined for each IC chip, package, and interface condition between them. Furthermore, to reduce the parasitic influences, several improvements in the interface and package design are clarified, such as wideband matching and LC resonance damping. IC design using effective feedback techniques for enlarging the bandwidth are also presented. The ICs are fabricated using 0.2-μm GaAs MESFET IC technology. To verify the validity of these techniques, an equalizer IC module for 10-Gb/s optical communication systems was fabricated, achieving a gain of 36 dB and a bandwidth of 9 GHz     

FCOB器件在热循环载荷下的界面层裂研究

界面层裂是塑封半导体器件的主要失效模式之一。采用通用有限元软件MSC.MARC,研究了FCOB(基板倒装焊)器件在热循环(–55~+125℃)载荷作用下,底充胶与芯片界面的层裂问题。结果表明:底充胶与芯片界面最易出现分层,分层扩展的位置都在该界面的边缘拐角处;如果分层导致底充胶开裂,开裂的方向大约是35°。     

一种新的Harris多尺度角点检测

Harris角点检测是一种经典的角点检测算法,但不具有尺度变化特性。该文把多分辨分析的思想引入到该算法中,构造了基于小波变换的灰度强度变化公式,并得到了具有尺度变换特性的自相关矩阵,从而构建了一种新的基于小波变换的Harris多尺度角点检测算法。这样,使得新的角点检测可以在不同的尺度下获取角点,并克服了单一尺度的Harris角点检测可能存在的角点信息丢失、角点位置偏移和易受噪而提取出伪角点等问题。通过对比实验,新算法明显地提高了图像角点检测性能。     

基于非线性复扩散及全局和局部特性的医学图像角点检测

常规的角点检测方法通常只考虑曲率极大值的局部特性,且在单一尺度下进行,易受噪声的影响,造成角点的漏检。为了克服这些缺陷,本文采用将多尺度分析的非线性复扩散处理方法与边缘点曲率极值的局部和全局特性相结合进行角点检测的方法。首先对图像进行保护边缘的非线性复扩散,以获取不同尺度的图像信息;然后针对不同尺度下图像的实部和虚部,进行基于全局和局部特性的角点检测,除考虑角点曲率极值的局部特性外,还将其与邻近点曲率的关系作为全局特性加以比较,最终确定角点。实验结果表明,本文方法可以有效地去除噪声的干扰,提取的角点数目多,避免漏检,位置准确。