Sub-1-V swing internal bus architecture for future low-power ULSIs

A bus architecture is proposed for reducing the operating power of future ULSIs. It uses new types of bus driver circuits and bus receiver circuits to reduce the bus signal swing while maintaining a low standby current. The bus driver circuit has a source offset configuration, achieved by the use of low-V_T MOSFETs and an internal supply voltage corresponding to the reduced signal swing. The bus receiver circuit has a symmetric configuration with two-level conversion circuits, each of which consists of a transmission gate and a cross-coupled latch circuit. Fast level conversion is achieved without increasing the standby current. The combination of the new bus driver and receiver enables the bus swing to be reduced to one-third that of the conventional architecture while maintaining high-speed data transmission and a low standby current. A test circuit designed and fabricated using 0.3-μm processes verifies the operation of the proposed architecture. Further improvements in the speed performance are possible with device optimization     

Reduced clock swing domino logic

A reduced clock swing domino logic gate for 50% reduction in power consumption in clock networks is presented. The original full swing gate works properly at reduced swing with a better noise tolerance and small loss of performance while simple resizing allows the same speed, power and noise figures     

Double-island single-electron devices. A useful unit device forsingle-electron logic LSI's

We fabricated a single-electron device that is useful as a unit device for single-electron logic circuits. The device is a three-current-terminal device fabricated on a silicon-on-insulator (SOI) wafer, which includes two Si islands whose electric potential can be controlled by gates. Sub-50-nm Si islands were integrated in an area smaller than 0.02 μm² through self-aligned formation of the islands by pattern-dependent oxidation (PADOX) of a T-shaped wire. By PADOX, each island was embedded in one branch of the T-shaped wire. We show two electrical characteristics which demonstrate the usefulness of this device as a circuit element. First, current switching between two branches was performed at 30 K by using gate voltage to control the Coulomb blockade in each island. Second, a correlation between the two currents was observed because the two islands were integrated close to each other. The latter indicates a capacitive coupling between the islands, which opens up the possibility of one-by-one transfer of electrons in this device. These findings show that the proposed island-integration technique is applicable to making ultra-low-power and highly integrated single-electron circuits     

Nanoelectronic architecture for Boolean logic

A nanoelectronic implementation of Boolean logic circuits is described where logic functionality is realized through charge interactions between metallic dots self-assembled on the surface of a double-barrier resonant tunneling diode (RTD) structure. The primitive computational cell in this architecture consists of a number of dots with nearest neighbor (resistive) interconnections. Specific logic functionality is provided by appropriate rectifying connections between cells. We show how basic logic gates, leading to combinational and sequential circuits, can be realized in this architecture. Additionally, architectural issues including directionality, fault tolerance, and power dissipation are discussed. Estimates based on the current-voltage characteristics of RTD's and the capacitance and resistance values of the interdot connections indicate that static power dissipation as small as 0.1 nW/gate and switching delay as small as a few picoseconds can be expected. We also present a strategy for fabricating/synthesizing such systems using chemical self-organizing/self-assembly phenomena. The proposed synthesis procedure utilizes several chemical self-assembly techniques which have been demonstrated recently, including self-assembly of uniform arrays of close-packed metallic dots with nanometer diameters, controlled resistive linking of nearest neighbor dots with conjugated organic molecules and organic rectifiers     

FABSYN: floorplan-aware bus architecture synthesis

As system-on-chip (SoC) designs become more complex, it is becoming harder to design communication architectures to handle the ever increasing volumes of inter-component communication. Manual traversal of the vast communication design space to synthesize a communication architecture that meets performance requirements becomes infeasible. In this paper, we address this problem by proposing an automated approach for floorplan-aware bus architecture synthesis (FABSYN) to synthesize cost-effective, bus-based communication architectures that satisfy the performance constraints in a design. Our synthesis approach incorporates a high-level floorplanning and wire delay estimation engine to evaluate the feasibility of the synthesized bus architecture and detect bus cycle time violations early in the design How, at the system level. We present case studies of network communication SoC subsystems for which we synthesized bus architectures, detected and eliminated timing violations, and generated core placements in a matter of hours instead of several days for a manual effort.     

如何选择48V电源母线架构

如何为电源系统选择最合适的架构和产品是工程师面临的一个困难选择     

Effective synthesis algorithm for partitioned bus architecture

An effective synthesis algorithm is proposed for partitioned bus architecture when the number of buses is constrained. In the proposed algorithm, the probability of bus conflict is reduced, leading to a performance improvement. Experimental results show ~10-50% performance improvement over the conventional method     

Design of a fault-tolerant COTS-based bus architecture

This paper describes the authors' approach to using commercial-off-the-shelf (COTS) products in highly reliable systems. The methodology calls for multilevel fault-protection. The methodology realizes that COTS products are often not developed with high reliability in mind. Nevertheless, by using multi-level fault protection, the same level of reliability as the traditional full-custom fault tolerance approach can be achieved. This methodology allows more freedom for design trade-offs among the fault-protection levels, which can result in less complicated designs than the traditional strictly-enforced fault-containment policy. This paper covers the authors' experiences and findings on the design of a fault-tolerant avionics bus architecture comprised of two COTS buses, the IEEE 1394, and the I²C, for the avionics system of X2000 program at the Jet Propulsion Laboratory. The X2000 design is judicious about ensuring the fault-tolerance provisions do not cause the bus design to deviate from commercial standard specifications, so that the economic attractiveness of using COTS is preserved. The hardware and software designs of the X2000 fault-tolerant bus are being implemented, and flight hardware will be delivered to the Europa Orbiter missions. This work provides an example of how to construct a highly reliable system with low-cost COTS interfaces     

A high-speed, low-power bipolar digital circuit for Gb/s LSI's:current mirror control logic

A novel low-power bipolar circuit for Gb/s LSIs, current mirror control logic (CMCL), is described. To reduce supply voltage and currents, the current sources of emitter-coupled-logic (ECL) series gate circuits are removed and the lower differential pairs are controlled by current mirror circuits. This enables circuits with the same function as two-stacked ECL circuits to operate at supply voltage of -2.0 V and reduces the current drawn through the driving circuits for the differential pairs to 50% of the conventional level shift circuits (emitter followers) in ECL. This CMCL circuit achieves 3.1-Gb/s (D-FF) and 4.3-GHz (T-FF) operation with a power supply voltage of -2.0 V and power dissipation of only 1.8 mW/(FF)     

Stateful-NOR based reconfigurable architecture for logic implementation

Most commercial Field Programmable Gate Arrays (FPGAs) have limitations in terms of density, speed, configuration overhead and power consumption mostly due to the use of SRAM cells in Look-Up Tables (LUTs), configuration memory and programmable interconnects. Also, hardwired Application Specific Integrated Circuit (ASIC) blocks designed for high performance arithmetic circuits in FPGA reduce the area available for reconfiguration. In this paper, we propose a novel generalized hybrid CMOS-memristor based architecture using stateful-NOR gates as basic building blocks for implementation of logic functions. These logic functions are implemented on memristor nanocrossbar layers, while the CMOS layer is used for selection and connection of memristors. The proposed pipelined architecture combines the features of ASIC, FPGA and microprocessor based designs. It has high density due to the use of nanocrossbar layer and high throughput especially for arithmetic circuits. The proposed architecture for three input one output logic block is compared with conventional LUT based Configurable Logic Block (CLB) having the same number of inputs and outputs; which shows 1.82×area saving, 1.57×speedup and 3.63×less power consumption. The automation algorithm to implement any logic function using proposed architecture is also presented.     

消息基VXI总线接口逻辑的模块化实现

VXI总线是一种在自动测试领域及其他多机互连系统中广泛应用的消息总线协议。文中分析了VXI总线协议的特点,根据该协议提供的通讯规范的可裁剪特征提出了模块化的VXI总线接口逻辑实现方法。并以此为基础在FPGA中实现了模块化的消息基VXI总线接口逻辑。通过模块化设计大大提高了设计的可继承性。为检验设计的可靠性和有效性,给出了FPGA设计生成的模拟时序,并将该设计应用于一种多DSP实时图像处理系统,使之能满足系统资源管理和各模块问的简单消息传递的需要。最后给出了实际测量的总线时序图,结果表明提出的设计方法和实现使VXI接口逻辑在模块化设计的同时也实现了协议所提供的总线带宽。     

The effect of logic block architecture on FPGA performance

This authors explore the effect of logic block architecture on the speed of a field-programmable gate array (FPGA). Four classes of logic block architecture are investigated: NAND gates, multiplexer configurations, lookup tables, and wide-input AND-OR gates. An experimental approach is taken, in which each of a set of benchmark logic circuits is synthesized into FPGAs that use different logic blocks. The speed of the resulting FPGA implementations using each logic block is measured. While the results depend on the delay of the programmable routing, experiments indicate that five- and six-input lookup tables and certain multiplexer configurations produce the lowest total delay over realistic values of routing delay. The fine grain blocks, such as the two-input NAND gate, exhibit poor performance because these gates require many levels of logic block to implement the circuits and hence require a large routing delay     

A cellular computing architecture for parallel memristive stateful logic

We present a cellular memristive stateful logic computing architecture and demonstrate its operation with computational examples such as vectorized XOR, circular shift, and content-addressable memory. The considered architecture can perform parallel elementary memristor programming and stateful logic operations, namely implication and converse nonimplication. The topology of the crossbar structure used for computing can be dynamically reconfigured, enabling combinations of local and global operations with varying granularity. In the CMOS cells used for controlling the memristors, we apply a new type of capacitive keeper circuit, which allows for energy efficient implementation of logic operations. The correct operation of this architecture is verified by detailed HSPICE simulations for a structure containing eight memristive crossbars. This work presents a hardware platform which enables future work on parallel stateful computing.     

Register insertion bus architecture for fibre optic local area networks

A protocol for fibre optic local area networks, the register insertion bus (RIB), is proposed. RIB uses a folded-bus topology with an access scheme which includes the existence of two buffers in each station to hold packets that would conflict. Simulations have shown the access scheme to efficiently utilise the network with a minimum of overhead. RIB implements a fair access scheme at normal network loads but at high loads a priority scheme is implemented. An enhancement technique is discussed that will implement a fair access scheme by altering the time between transmissions based on the measured network load.<>     

A new local area network architecture using a centralized bus

LOCAL AREA NETWORKS are currently enjoying tremendous popularity as a means for providing wideband interconnection and communications among data terminals, host computers and other types of digital equipment located throughout a single building or a campus of buildings. Such networks are typically based on bus, ring, or star architectures, each of which manifests its own set of advantages and disadvantages. In this paper, an architectural approach is described that draws upon and integrates the advantages found separately in these three different architectures, while avoiding the major disadvantages found in any one. This new architecture employs a centrally located short bus that provides an extremely efficient packet-switching service to the devices attached to the network. Bandwidth on the short bus is dynamically allocated in response to instantaneous demands by means of a highly efficient but flexible prioritybased bus contention scheme. The approach permits multiple priority classes with fair allocation of bandwidth within each class, along with a capability for integrated circuit and packet switching. The architecture can also make use of existing twisted-pair building wiring, and at the same time take advantage of emerging optical-fiber technology. In addition, the architecture provides a means to expand the network beyond a local area, resulting in a wide-area network capability.     

An adaptive fuzzy logic controller: its VLSI architecture andapplications

Most previous work about the hardware design of a fuzzy logic controller (FLC) intended to either improve its inference performance for real-time applications or to reduce its hardware cost. To our knowledge, there has been no attempt to design a hardware FLC that can perform an adaptive fuzzy inference for the applications of on-line adaptation. The purpose of this paper is to present such an adaptive memory-efficient FLC and its applications. Taking advantage of the adaptability provided by a symbolic fuzzy rule format and the dynamic membership function generator, as well as the high-speed integration capability afforded by VLSI, the proposed adaptive fuzzy logic controller (AFLC) can perform an adaptive fuzzy inference process using various inference parameters, such as the shape and location of a membership function, dynamically and quickly. Three examples are used to illustrate its applications, and the experimental results show the excellent adaptability provided by AFLC     

Experimental multiuser quantum key distribution network using a wavelength-addressed bus architecture

A six-user quantum key distribution network implemented on a bus topology is experimentally demonstrated. The network employs the BB84 protocol to transmit cryptographic keys encoded unto the phase states of highly attenuated laser light to distances of up to 31 km in a standard telecommunication-grade fiber. Each user on the network is assigned a unique wavelength for communication with the network server at a time. The measured quantum bit error rate and sifted key rate compare favorably with theoretical results.     

Low-voltage swing logic circuits for a Pentium/spl reg/ 4 processor integer core

The Pentium/spl reg/ 4 processor architecture uses a 2/spl times/ frequency core clock to implement low latency integer operations. Low-voltage-swing (LVS) logic circuits implemented in 90-nm technology meet the frequency demands of a third-generation integer-core design.     

Race logic architecture (RALA): a novel logic concept using therace scheme of input variables

A novel logic concept, Race Logic Architecture (RALA), is proposed. RALA is a new logic operation architecture in that the racing between input variables along the interconnection lines functions as an active logic element instead of logic gates, while the logic gates play a simple passive role. Logic operations of RALA are based on wired-OR that utilizes shared space and serial-AND that utilizes the triggering sequence of input variables. With these two concepts, RALA can implement arbitrary Boolean operations. Various kinds of combinational circuits are simulated and compared with RALAs. RALA shows the best performance in delay time, area, and power product results. A 64-bit carry-look-ahead adder with RALA is fabricated by 0.25-μm CMOS technology to verify its feasibility and functionality. The area of the adder is 800 μm×150 μm, and the delay time from the clock to Sum31 measured 0.9 ns     

An 8-b slice GaAs bus logic LSI for a high-speed parallelprocessing system

An 8-b slice GaAs bus logic LSI (BL) has been developed for a high-speed interconnection network in a multiple-instruction multiple-data stream (MIMD) parallel processing system. The BL has been designed using a novel standard-cell approach called the building-cell methodology, which leads to a high integrated density of 25000 devices in a 7×7-mm² chip. The BL consists of 3376 logic gates and a 76-b dual-port register file (RF), which has as a new function a multi-address read/write operation for efficient data transfer. The BL was fabricated by a 0.8-μm WN_x gate LDD (lightly doped drain) MESFET process, and fully functionally tested with an average yield of 20%. A 10-ns cycle time operation was achieved with a power dissipation of 5.5 W. This result reveals that a network with 256 GaAs BLs and 64 processor units can realize a maximum data transfer rate of 2.56 Gbyte/s