Hummingbird加密算法的硬件架构设计

Hummingbird加密算法是针对RFID标签等硬件受限系统的轻型加密算法。其已在不同平台上得到了验证。文中提出了一种针对Hummingbird算法的硬件架构,与目前其他方法相比,在响应时间基本相同的情况下,该硬件架构所需的硬件资源更少。其采用Xilinx的低端Spartan-3系列FPGA芯片作为验证平台。实验结果表明,该硬件架构可较好地嵌入到硬件受限系统中,尤其是嵌入式系统。     

嵌入式可重构系统芯片的硬件验证平台设计

提出一种新的基于嵌入武可重构系统芯片的视频解码方案,采用了软硬件协同验证的方法.设计了相应的硬件验证平台,验证了H.264解码算法在可重构处理器上的可实现性.     

一种可重构体系结构用于高速实现DES、3DES和AES

可重构密码芯片提高了密码芯片的安全性和灵活性,具有良好的应用前景.然而目前的可重构密码芯片吞吐率均大大低于专用芯片,因此,如何提高处理速度是可重构密码芯片设计的关键问题.本文分析了常用对称密码算法DES、3DES和AES的可重构性,利用流水线、并行处理和可重构技术,提出了一种可重构体系结构.基于该体系结构实现的DES、3DES和AES吞吐率在110MHz工作频率下分别可达到7Gbps、2.3Gbps和1.4Gbps.与其他同类设计相比,本文设计在处理速度上有较大优势,可以很好地应用到可重构密码芯片设计中.     

可配置的2D空域滤波操作VLSI架构研究

提出了一种可配置的支持红外自动目标识别应用中不同窗口操作的2D空域滤波类操作VLSI架构,从SoC角度考虑能够更好地满足不同的图像处理应用．该架构与已报道的对于该类操作的其他结构解决方案进行比较,新结构具有较高的处理速率．新结构在SIMC0．18μmCMOS工艺下实现,其时钟频率为135Mhz,功耗为52mW,面积约为128．2KGates,峰值处理性能达到6．6GOPs．     

面向密码算法的异步可重构结构设计

针对FPGA和ASIC在实现密码算法时的不足之处，本文介绍了一种面向密码算法的异步可重构结构。该结构的运算功能由一个可重构单元阵列提供，数据通路由可重构单元之间的相互连接实现，异步通信采用握手信号完成。在分析握手信号传输延时对可重构结构的影响后，文章提出了一种适合该结构的单元信号传输握手控制电路。同时在单元结构中，使用改进的DSDCVS逻辑来设计其运算电路，减小了单元的面积，提高了单元的工作速度。应用实例表明，在实现密码算法时，面向密码算法的异步可重构结构表现出了比FPGA更好的性能。     

Reconfigurable Filter Coprocessor Architecture for DSP Applications

Digital Signal Processing (DSP) is widely used in high-performance media processing and communication systems. In majority of these applications, critical DSP functions are realized as embedded cores to meet the low-power budget and high computational complexity. Usually these cores are ASICs that cannot be easily retargeted for other similar applications that share certain commonalities. This stretches the design cycle that affects time-to-market constraints. In this paper, we present a reconfigurable high-performance low-power filter coprocessor architecture for DSP applications. The coprocessor architecture, apart from having the performance and power advantage of its ASIC counterpart, can be reconfigured to support a wide variety of filtering computations. Since filtering computations abound in DSP applications, the implementation of this coprocessor architecture can serve as an important embedded hardware IP.     

可重构基础网络体系研究与探索

随着网络规模的急剧扩大和新业务的不断涌现,现有互联网在业务适应、传输能力、安全可管可控等方面的弊端日益凸显.为此,业界关于新型互联网体系结构的研究正蓬勃兴起.在此背景下,利用可重构技术在灵活性、可扩展性、适应性等方面的优势探索网络发展新的思路和途径.研究表明,该项目成果为解决网络发展面临的根本问题提供了有效解决途径,并且在国内外相关领域产生了重要影响.     

Domain Specific Reconfigurable Processing Core Architecture for Digital Filtering Applications

This paper presents a reconfigurable processing core architecture targeted for digital filtering applications. The architecture can be configured to execute linear phase FIR filter, DLMS adaptive FIR filter, (I)FFT, and 2D-(I)DCT with high performance and low energy consumption by reducing heavy routing resources used extensively in other reconfigurable architectures. The pipeline depth of the multipliers in the processing core is locally controlled so that power consumption is reduced by minimizing unnecessary register switching is saved. We have shown that the proposed processing core consumes less energy and has better or comparable performance than that of the existing reconfigurable architectures proposed in academia and industry, that have been tailored for these applications. The circuit is designed in 0.35-m CMOS processing technology with 3.3 V supply voltage.Sangjin Hong received the B.S. and M.S. degrees in EECS from the University of California, Berkeley and his Ph.D in EECS from the University of Michigan, Ann Arbor. He is currently with the department of Electrical and Computer Engineering at Stony Brook University - State University of New York. Before joining SUNY, he has worked at Ford Aerospace Corp. Computer Systems Division as a systems engineer. He also worked at Samsung Electronics in Korea as a technical consultant. His current research interests are in the areas of low power reconfigurable SoC design and optimization for DSP and wireless communication systems. He has served as a member of technical committee and track chair for numerous IEEE technical conferences.Shu-Shin Chin was born in Kaohsiung, Taiwan, ROC, in 1974. He received his M.S. and Ph.D degrees in electrical and computer engineering from Stony Brook University—State University of New Yorkin 1999 and 2004, respectively. His research interests include low-power digital circuits, and coarse-grained reconfigurable architectures for high-performance DSP systems.     

一种新型高速低成本可重构FFT处理器结构

文中提出了一种基于FPGA的高速可重构FFT处理器结构.该结构采用精简控制算法[1]可针对从32点到1024点等不同点数数字信号进行FFT处理,并且在Xilinx公司Virtex2p系列FPGA上进行了综合及后仿真.结果表明该可重构结构相比Xilinx IP core而言资源占用减少16%~21%(slice),最高时钟频率提高了10%~30%,输入输出延时减少了56~116个时钟周期,运算效率明显提高,而功耗相当.可适用于低成本高速数字信号处理系统.     

Reconfigurable Computing for Digital Signal Processing: A Survey

Steady advances in VLSI technology and design tools have extensively expanded the application domain of digital signal processing over the past decade. While application-specific integrated circuits (ASICs) and programmable digital signal processors (PDSPs) remain the implementation mechanisms of choice for many DSP applications, increasingly new system implementations based on reconfigurable computing are being considered. These flexible platforms, which offer the functional efficiency of hardware and the programmability of software, are quickly maturing as the logic capacity of programmable devices follows Moore's Law and advanced automated design techniques become available. As initial reconfigurable technologies have emerged, new academic and commercial efforts have been initiated to support power optimization, cost reduction, and enhanced run-time performance.This paper presents a survey of academic research and commercial development in reconfigurable computing for DSP systems over the past fifteen years. This work is placed in the context of other available DSP implementation media including ASICs and PDSPs to fully document the range of design choices available to system engineers. It is shown that while contemporary reconfigurable computing can be applied to a variety of DSP applications including video, audio, speech, and control, much work remains to realize its full potential. While individual implementations of PDSP, ASIC, and reconfigurable resources each offer distinct advantages, it is likely that integrated combinations of these technologies will provide more complete solutions.     

Application of Reconfigurable Computing to a High Performance Front-End Radar Signal Processor

Many radar sensor systems demand high performance front-end signal processing. The high processing throughput is driven by the fast analog-to-digital conversion sampling rate, the large number of sensor channels, and stringent requirements on the filter design leading to a large number of filter taps. The computational demands range from tens to hundreds of billion operations per second (GOPS). Fortunately, this processing is very regular, highly parallel, and well suited to VLSI hardware. We recently fielded a system consisting of 100 GOPS designed using custom VLSI chips. The system can adapt to different filter coefficients as a function of changes in the transmitted radar pulse. Although the computation is performed on custom VLSI chips, there are important reasons to attempt to solve this problem using adaptive computing devices. As feature size shrinks and field programmable gate arrays become more capable, the same filtering operation will be feasible using reconfigurable electronics. In this paper we describe the hardware architecture of this high performance radar signal processor, technology trends in reconfigurable computing, and present an alternate implementation using emerging reconfigurable technologies. We investigate the suitability of a Xilinx Virtex chip (XCV1000) to this application. Results of simulating and implementing the application on the Xilinx chip is also discussed.     

高效可配置浮点FFT处理器设计

为了克服高精度浮点FFT处理器具有较大资源开销的设计瓶颈,采用基于单口存储器的FIFO构建共享蝶形结构的R2/22SDF流水可配置结构.采用适合浮点设计的基2/22算法实现流水结构,不仅有利于可配置电路的实现,还能够有效减少复数乘法次数,提高复数乘法器的计算效率.采用双倍数据位宽的单口存储器实现FIFO存储器,有效避免了双口存储器面积和功耗较大的问题.改进的蝶形共享结构实现两级蝶形的合并,解决了单路径延迟反馈流水线结构蝶形单元利用率低的问题.与传统流水线结构FFT处理器设计相比,有效降低了浮点设计中的资源开销,提高了计算单元的利用效率.     

基于可重构核的FPGA电路设计

电路系统的自适应性、紧凑性和低成本 ,促进了在嵌入式系统中软硬件的协同设计。在线可重构FPGA不仅可以满足这一要求 ,而且在可编程专用电路系统设计的验证及可靠性等方面有着良好的应用 ,文中介绍了可重构 FPGA的实现结构及评估方法 ,提出以线性矢量表征可重构 FPGA及其可重构核的研究模型 ,以及基于可重构核的模块化设计 ,认为面向分类的专用类可重构 FPGA应当是现阶段可重构 FPGA的研究主题。     

全搜索运动估计算法的高效VLSI结构设计

提出了一种具有可重构寄存器阵列的高效树型运算结构。该结构具有100%的PE利用率。同传统的全树型结构相比,在具有相近处理能力的情况下,它的输入数据带宽得到了大幅度降低。采用该设计思想实现了一个具有256个PE的电路,用于处理16×16的宏块。该电路在工作频率为55 MH z时就可以满足搜索区域是[-16,16]、帧率为30 fps和帧尺寸为720×576的视频序列的实时压缩处理要求。此时,该结构的处理能力比相近硬件规模的AB 2结构提高了31%,输入数据带宽仅为全树型的1/16。     

针对粗粒度可配置结构芯片的蚁群路由系统设计

以最大-最小蚁群系统为基础,为蚁群采用增加了嗅觉分辨能力,应用于粗粒度可配置结构芯片的路由问题。以开发的粗粒度可重构芯片CTaiJi为对象,通过几个算例的比较,可以看到此方法找到最优解的能力优于目前常用的谈判阻塞算法。     

FPGA中通用互连结构的设计与优化

介绍了一款基于SRAM技术的FPGA电路的通用互连结构.在对其通用互连线的延时模型进行分析的基础上,提出了一种改进的互连结构.基于CSMC 0.6 μm工艺下的SPICE仿真及流片结果表明,改进后的互连结构性能提高了约10%.     

A method for partitioning applications in hybrid reconfigurable architectures

In this paper, we propose a methodology for accelerating application segments by partitioning them between reconfigurable hardware blocks of different granularity. Critical parts are speeded-up on the coarse-grain reconfigurable hardware for meeting the timing requirements of application code mapped on the reconfigurable logic. The reconfigurable processing units are embedded in a generic hybrid system architecture which can model a large number of existing heterogeneous reconfigurable platforms. The fine-grain reconfigurable logic is realized by an FPGA unit, while the coarse-grain reconfigurable hardware by our developed high-performance data-path. The methodology mainly consists of three stages; the analysis, the mapping of the application parts onto fine and coarse-grain reconfigurable hardware, and the partitioning engine. A prototype software framework realizes the partitioning flow. In this work, the methodology is validated using five real-life applications. Analytical partitioning experiments show that the speedup relative to the all-FPGA mapping solution ranges from 1.5 to 4.0, while the specified timing constraints are satisfied for all the applications.     

演化硬件及面向演化的VLSI可重构体系结构设计

演化硬件在环境适应性和可靠性设计上具有潜在的巨大优势。文章介绍了数字和模拟电路演化综合的原理和步骤，几类典型的演化硬件平台及其局限性，重点讨论了面向演化的VLSI可重构体系结构，最后提出了这一新兴研究领域面临的一些问题及解决方法。     

可重构柔性网络架构与节能机制研究

随着计算机网络业务的不断发展和网络规模的急剧膨胀,目前网络在服务能力可扩展性和低功耗方面存在不足。提出一种可支撑服务能力重构和绿色节能的可重构柔性网络架构,给出了可重构柔性网络的松耦合分层模型、组网架构和组网技术。通过在服务能力与资源之间建立或变更映射关系,灵活支持未来上层业务演进,并在网络设备制造产业、网络级和节点级实现网络绿色节能。结果表明,可重构柔性网络作为一种新型的未来网络架构,为未来构建可重构服务网络和绿色网络提供了可行的思路和方法。