A 4-mW monolithic CMOS LNA at 5.7GHz with the gate resistance used for input matching

Design and measured results of a fully integrated 5.7-GHz CMOS low-noise amplifier (LNA) is presented. To design this LNA, the parasitic input resistance of a metal-oxide-semiconductor field-effect transistor (MOSFET) is converted to 50/spl Omega/ by a simple L-C network, hence eliminating the need for source degeneration. It is shown, by means of compact expressions, that this matching method enhances the effective transconductance of the LNA by a factor that is inversely proportional to a MOSFET's input resistance. The effect of our proposed method on the noise figure (NF) of the LNA is also discussed. With an 11.45-dB power gain and a 3.4-dB NF at 4mW of dc power, the presented LNA achieves the best overall performance when compared with the most recently published LNAs.     

Noise modeling and SiGe profile design tradeoffs for RFapplications [HBTs]

This paper investigates SiGe profile design tradeoffs for low-noise RF applications at a given technology generation (i.e., fixed minimum feature size and thermal cycle). An intuitive model relating structural parameters and biases to noise parameters is used to identify the noise limiting factors in a given technology. The noise performance can be improved by pushing more Ge into the base and creating a larger Ge gradient in the base. To maintain the SiGe film stability, the retrograding of the Ge into the collector has to be reduced, leading to a stronger f_T-I_C roll-off at high injection. Two low-noise profiles were designed and fabricated explicitly for improving minimum noise figure (NF_min) without sacrificing gain, linearity, frequency response, or the stability of the SiGe strained layer. A 0.2 dB NF_min was achieved at 2.0 GHz with an associated gain (G_assoc) of 13 dB     

A new high-dynamic range dual-loop power-to-current amplifier

The design and performance of a balanced amplifier with a dual differential feedback loop in a high-frequency BiFET (bipolar-field effect transistor) process (f_T=3 GHz) is presented. By means of this dual feedback loop, a linear, accurately known input impedance is obtained, combined with a high-output impedance. The noise figure of the realized amplifier is lower than 3 dB. The amplifier is especially intended for low-noise, low-distortion termination of antennas, cables, or filters and for driving bipolar switching mixers up to frequencies well above 100 MHz     

High-frequency four noise parameters of silicon-on-insulator-basedtechnology MOSFET for the design of low-noise RF integratedcircuits

An exhaustive experimental study of the high-frequency noise properties of MOSFET in silicon-on-insulator (SOI) technology is presented. Various gate geometries are fabricated to study the influence of effective channel length, gate finger width, and gate sheet resistivity on the four noise parameters. The high level of MOSFET sensitivity to the minimum noise matching condition is demonstrated. From experimental results, optimal ways to realize ultra low noise amplifiers are discussed. The capability of the fully depleted standard SOI CMOS process for realizing low-noise amplifiers for multigigahertz portable communication systems is shown     

A simple and analytical parameter-extraction method of a microwaveMOSFET

A simple and accurate parameter-extraction method of a high-frequency small-signal MOSFET model including the substrate-related parameters and nonreciprocal capacitors is proposed. Direct extraction of each parameter using a linear regression approach is performed by Y-parameter analysis on the proposed equivalent circuit of the MOSFET for high-frequency operation. The extracted results are physically meaningful and good agreement has been obtained between the simulation results of the equivalent circuit and measured data without any optimization. Also, the extracted parameters, such as g_m and g_ds, match very well with those obtained by DC measurement     

Linearity and low-noise performance of SOI MOSFETs for RFapplications

The MOSFET parameters important for RF application at GHz frequencies: a) transition frequency, b) noise figure, and c) linearity are analyzed and correlated with substrate type. This work demonstrates that, without process changes, high-resistivity silicon-on-insulator (high-ρ SOI) substrates can successfully enhance the RF performance of on-chip inductors and fully depleted (FD)-SOI devices in terms of reducing substrate losses and parasitics. The linearity limitations of the SOI low-breakdown voltage and "kink" effect are addressed by judicious device and circuit design. Criteria for device optimization are derived. A NF = 1.7 dB at 2.5 GHz for a 0.25 μm FD-SOI low-noise amplifier (LNA) on high-ρ SOI substrate obtained the lowest noise figure for applications in the L and S-bands     

A Compact, ESD-Protected, SiGe BiCMOS LNA for Ultra-Wideband Applications

Two 3.65-mW, ESD-protected, BiCMOS ultra-wideband low-noise amplifiers (LNAs) for operation up to 10 GHz are presented. These common-base LNAs achieve significant savings in die area over more widely used cascoded common-emitter LNAs because they do not use an LC input matching network. A design with a shunt peaked load achieves a high S₂₁ (17-19 dB) and low noise figure (NF) (4-5 dB) across the band. A resistively loaded design exhibits a lower S₂₁ (15-16 dB) and higher NF (4.5-6 dB), but also utilizes 20% less silicon area. Both LNAs achieve a 1.5 kV ESD protection level and an acceptable S₁₁ (<-10 dB) across the band. Current source noise reduction is critical in common base topologies. Therefore, detailed noise analyses of MOS- and HBT-based current sources are provided     

Wide-band CMOS cascode low-noise amplifier design based on source degeneration topology

A design methodology for a wide-band CMOS low noise amplifier (LNA) with source degeneration is presented. By allowing an arbitrary source degeneration and employing a general input matching network, the proposed wide-band CMOS LNA can be shown for any choice of transistor width to achieve the minimum noise figure at all frequencies of interest. The transistor width simply affects the gain of the LNA at the cost of power dissipation. These results apply uniquely to CMOS LNAs, as they are derived from a quasi-static MOSFET model. To validate these design concepts, a wide-band LNA was realized in 0.25-/spl mu/m CMOS technology. The measured noise figure ranges from 2.7 to 3.7 dB over 3.2-4.8 GHz with power consumption of 20 mW. A close agreement with the theoretical results is observed.     

A noise optimization technique for integrated low-noise amplifiers

Based on measured four-noise parameters and two-port noise theory, considerations for noise optimization of integrated low-noise amplifier (LNA) designs are presented. If arbitrary values of source impedance are allowed, optimal noise performance of the LNA is obtained by adjusting the source degeneration inductance. Even for a fixed source impedance, the integrated LNA can achieve near NF/sub min/ by choosing an appropriate device geometry along with an optimal bias condition. An 800 MHz LNA has been implemented in a standard 0.24 /spl mu/m CMOS technology. The amplifier possesses a 0.9 dB noise figure with a 7.1 dBm third-order input intercept point, while drawing 7.5 mW from a 2.0 V power supply, demonstrating that the proposed methodology can accurately predict noise performance of integrated LNA designs.     

Design of Ultra-Low-Voltage RF Frontends With Complementary Current-Reused Architectures

In this paper, ultra-low-voltage circuit techniques are presented for CMOS RF frontends. By employing a complementary current-reused architecture, the RF building blocks including a low-noise amplifier (LNA) and a single-balanced down-conversion mixer can operate at a reduced supply voltage with microwatt power consumption while maintaining reasonable circuit performance at multigigahertz frequencies. Based on the MOSFET model in moderate and weak inversion, theoretical analysis and design considerations of the proposed circuit techniques are described in detail. Using a standard 0.18-mum CMOS process, prototype frontend circuits are implemented at the 5-GHz frequency band for demonstration. From the measurement results, the fully integrated LNA exhibits a gain of 9.2 dB and a noise figure of 4.5 dB at 5 GHz, while the mixer has a conversion gain of 3.2 dB and an IIP₃ of -8 dBm. Operated at a supply voltage of 0.6 V, the power consumptions of the LNA and the mixer are 900 and 792 muW, respectively.     

Modified derivative superposition method for linearizing FET low-noise amplifiers

Intermodulation distortion in field-effect transistors (FETs) at RF frequencies is analyzed using the Volterra-series analysis. The degrading effect of the circuit reactances on the maximum IIP₃ in the conventional derivative-superposition (DS) method is explained. The noise performance of this method is also analyzed and the effect of the subthreshold biasing of one of the FETs on the noise figure (NF) is shown. A modified DS method is proposed to increase the maximum IIP₃ at RF. It was used in a 0.25-mum Si CMOS low-noise amplifier (LNA) designed for cellular code-division multiple-access receivers. The LNA achieved +22-dBm IIP₃ with 15.5-dB gain, 1.65-dB NF, and 9.3 mA@2.6-V power consumption     

A 7-GHz 1.8-dB NF CMOS low-noise amplifier

A 7-GHz low-noise amplifier (LNA) was designed and fabricated using 0.25-μm CMOS technology. A cascode configuration with a dual-gate MOSFET and shielded pads were adopted to improve the gain and the noise performance. The effects of the dual-gate MOSFET and the shielded pads are discussed quantitatively. An associated gain of 8.9 dB, a minimum noise figure of 1.8 dB, and an input-referred third-order intercept point of +8.4 dBm were obtained at 7 GHz. The LNA consumes 6.9 mA from a 2.0-V supply voltage. These measured results indicate the feasibility of a CMOS LNA employing these techniques for low-noise and high-linearity applications at over 5 GHz     

Effect of forward and reverse substrate biasing on low-frequencynoise in silicon PMOSFETs

Forward body biasing improves the low-frequency noise performance of p-channel metal-oxide semiconductor (PMOS) transistors by about 8 dB/V. Therefore, for analog design, forward body biasing may be preferred if noise is a concern. This is in agreement with the improvement of other MOSFET parameters such as the decrease of the threshold voltage (V_T) or the increase of unity current-gain frequency (f_T) on forward substrate- (or body)-source biasing (V_BS). Also, forward V_BS is very attractive for low voltage supply (V_DD<0.6 V) and low-power, low-noise circuits. A detailed analysis of the dependence of the noise level on VBS and on the gate-source (V_GS) biasing showed that the dependence on V_BS seems to be smaller in weak inversion, and it increases in strong inversion. The dependence on V_GS has a turning point at V_GS≈0.8 V, independent of body bias, which it seems is due to the activation of oxide traps, as the noise waveform showed a random telegraph signal (RTS) component at V_GS >0.8 V. Generally, it is confirmed that the spectral density S _I of the total low-frequency noise of the drain current I_D is proportional to the square of I_D, i.e., S _I∝I_D², but it cannot be clearly ascribed to either number fluctuation or mobility fluctuation models. In addition, both models cannot accurately describe the dependence of the noise level on the body bias     

Design and calculation procedures for low-noise traveling-wave tubes

A step-by-step procedure for designing low-noise traveling-wave tubes is presented in this paper. The procedure permits the rapid calculation of the significant design parameters corresponding to the conditions for minimum noise figure. The procedure includes the use of a special transmission-line type chart which facilitates the calculations and aids in understanding the principles involved in achieving low-noise behavior. By using the chart in connection with a second procedure, noise figure variation with frequency and with the tube parameters can be predicted for arbitrary electron gun design. Measured noise figures for two X-band low-noise tubes designed essentially by these procedures agree with the theoretically predicted noise figures to within 1.5 db.     

Desensitized CMOS Low-Noise Amplifiers

The minimum attainable noise figure for scaled- CMOS low-noise amplifiers (LNAs) is limited by impedance mismatches such as the well-known noise/power tradeoff. In this paper, we show that a power-constrained optimization of the device noise resistance parameter, R_n, significantly reduces the impact of mismatches and variations and leads to an almost simultaneous noise and power match. This process, called desensitization, makes the design largely immune to measurement and modeling errors and manufacturing variations, and significantly reduces frequency-dependent noise mismatches in wide-band LNAs. Measured data from devices and desensitized LNAs designed on 180-nm and 90-nm CMOS processes shows that: (1) a device size selected for optimum R_nmiddot is less sensitive to source impedance mismatches and provides a wide-band noise match; and (2) LNAs approach a simultaneous input and noise match, and exhibit significant improvements (ges 2x) in their wide-band noise performance.     

Investigation of Thermal Noise in UTB GOI and SOI Devices

The thermal-noise performances of ultrathin-body silicon-on-insulator (SOI) and germanium-on-insulator (GOI) devices are investigated and compared through simulation in this paper. The figures-of-merit for noise characteristics are considered in terms of the minimum of noise figure (NF_min)and equivalent noise resistance (R_n). GOI devices exhibit better noise performance over SOI counterparts. The reduction in the supply voltage brings more distinct improvements of the noise performance of GOI devices. The dependence of noise parameters on the film thickness and spacer length is also analyzed. The results demonstrate that GOI devices are more suitable for RF and low-noise applications.     

RFCMOS Unit Width Optimization Technique

In this paper, we demonstrate a unit width ( W_f) optimization technique based on their unity short-circuit current gain frequency (f_T) unilateral power gain frequency (f_MAX)? and high-frequency (HF) noise for RFCMOS transistors. Our results show that the trend for the above figures-of-merit (FOMs) with respect to the W_f change is different; hence, some tradeoff is required to obtain the optimum W_f value. During the HF noise analysis, a new FOM is proposed to study the W_f effect on the HF noise performance. In our experiment, the flicker noise of the transistor is also measured and the result shows that the change in W_f does not affect the noise spectral density at the low-frequency range. This technique enables RF engineers to optimize the transistor's layout and helps to select the optimum Wf for transistors used in specific circuit design such as the low-noise amplifier, voltage-controlled oscillator, and mixer. Furthermore, by using layout optimized transistors in the RF circuit, the optimal circuit's performance can be easily achieved and, thus, greatly reduced the circuit development time. In the aspect of RF device modeling, by knowing the optimum W_f for a particular process or technology, the number of transistors to model is reduced and, hence, greatly shortens the RF modeling development time for existing and future technologies.     

A Low-Power Wideband CMOS LNA for WiMAX

In this brief, the design of a low-power inductorless wideband low-noise amplifier (LNA) for worldwide interoperability for microwave access covering the frequency range from 0.1 to 3.8 GHz using 0.13-mum CMOS is described. The core consumes 1.9 mW from a 1.2-V supply. The chip performance achieves S₁₁ below -10 dB across the entire band and a minimum noise figure of 2.55 dB. The simulated third-order input intercept point is -2.7 dBm. The voltage gain reaches a peak of 11.2 dB in-band with an upper 3-dB frequency of 3.8 GHz, which can be extended to reach 6.2 GHz using shunt inductive peaking. A figure of merit is devised to compare the proposed designs to recently published wideband CMOS LNAs     

Proposal of low-noise amplifier utilizing resonant tunnelingtransistors

A low-noise amplifier utilizing the negative input resistance of resonant tunneling transistors (RTT's) is proposed. Expected features of the RTT amplifiers are: 1) negligible effect of noise sources at the output, owing to their large power gain; 2) flat variation of noise figure (NF) versus frequency, due to white spectra of noise sources at the input; and 3) a high maximum oscillation frequency (f_max) (over several 100 GHz), Based on simulated DC characteristics, over 500 GHz f_max and 0.3 dB NF at 100 GHz are predicted for optimized AlGaAs/GaAs/AlGaAs resonant tunneling diodes (RTD's). In an RTT formed by coupling an FET to an optimized RTD, 0.55 dB minimum noise figure and 26 dB associated gain are predicted at 100 GHz. Also, a 1/w² spectrum of the input noise resistance is predicted at low frequencies     

Blanket LVD tungsten silicide technology for smart powerapplications

A high-frequency power MOSFET structure fabricated using blanket deposited LPCVD (low-pressure chemical vapor deposition) WSi₂ gate and selectively deposited LPCVD tungsten source contact metallurgy is reported. A high-density power MOSFET technology suitable for smart power applications which simultaneously lowers the gate sheet resistance and source contact resistance is discussed. This technology was used to fabricate 30-V and 50-V power FETs with excellent high-frequency performances. The measured specific on-resistance R_sp, specific input capacitance C_sp , and switching times are among the lowest reported in the literature for any power FET structure in this reverse blocking voltage range