SoC设计中的时钟低功耗技术

针对时钟网络在SoC芯片中的作用和时钟网络自身的特点,研究并实现3种时钟低功耗技术,包括在系统级采用动态时钟管理技术动态地关断和配置芯片内各模块的时钟,在逻辑综合时基于功耗优化工具Power Compiler插入门控时钟单元,在时钟树综合时以时钟树规模为目标进行低功耗时钟树综合。在音视频解码芯片的设计中采用以上3种技术,结果表明其功耗优化效果明显。     

基于时钟控制的低功耗电路设计

在低功耗芯片设计中,设计者已广泛采用了时钟停止的方法来解决CMOS电路动态功耗问题。为实现时钟停止功能,作者分析了多种传统时钟控制电路方案,并在此基础上提出了一种新型可综合可测试的时钟控制电路。相对于传统时钟控制电路,此种方案在降低芯片功耗的同时解决了传统时钟控制电路所带来的时钟不稳定及无法进行测试的问题。     

基于标准单元替换的功耗优化方法研究

集成电路设计工艺的不断提升在带来更高性能的同时也造成了功耗过高的问题,如何兼顾高性能与低功耗成为当前高性能超大规模集成电路设计需要解决的关键问题,标准单元替换是一种有效的降低功耗的方法.首先比较了2种不同的标准单元替换策略,然后通过实验分析了不同策略的功耗优化效果以及对性能的影响,最后提出了合适的标准单元替换策略来优化...     

应用输入向量控制技术降低漏电功耗的快速算法

随着工艺的发展,为保证电路的性能和噪声容限必须降低阈值电压,这将导致漏电流呈指数增长,漏电功耗因而将逐渐超过动态功耗占据主导地位. CMOS的堆栈效应导致电路在不同向量下的静态功耗不同,因此在电路进入睡眠状态时使用输入向量控制技术是一种低功耗设计的有效方法,如何快速找到一个可降低电路漏电功耗的向量就成了问题的关键.介绍了一种在给定向量集合中查找低功耗向量的快速算法——基于概率传递的标记算法,并为此开发了一个事件驱动的门级组合电路仿真器.通过对ISCAS和龙芯处理器电路的实验结果表明,该算法同传统方法比较可以提高性能3.4倍,误差率仅约0.14%.     

SoC总线的低功耗分支编码方案

为了降低SoC总线功耗,提出一种总线低功耗分支编码。该编码的基本思想为:对于地址总线,当地址连续时将地址总线死锁,当地址不连续时动态地调整窗口大小对其进行翻转编码;对于数据总线,对不同数据位宽分别设置两个汉明距阈值,当汉明距落在两个阈值之间则查找有效数据通道翻转密集区并对该区取反,两个阈值之外则采用翻转编码。该方法的编解码电路在32位AHB总线系统上实现,实验证明该方法与未编码之前相比将地址总线跳变率降低了51.2%,数据总线跳变率降低了22.4%,系统总功耗降低了28.9%。将T0编码、BI编码等方法在相同系统下实现后与所提方法作比较,证明分支编码方法在降低跳变率和功耗上有明显的优势。     

时钟芯片的低功耗设计

在时钟芯片设计的各个层次上深入探讨了影响时钟芯片功耗的主要因素,确定了电路功耗主要来源与振荡电路和分频电路。在电路实现过程中,通过采用不同工作电压和对主要功耗电路的结构和参数进行优化设计等多种手段来控制功耗。通过1.2滋m工艺流片验证,在工作电压为5V时,芯片工作电流为0.17mA,实现了低功耗时钟芯片的设计。     

液晶显示控制器的低功耗体系结构设计

随着液晶显示系统在手持设备中的广泛应用,低功耗已经成为液晶显示控制器芯片设计的重要目标。本文从体系结构层次讨论了液晶显示控制器的低功耗设计方案,主要包括系统时钟分配和显示数据压缩两个方面。功耗分析结果表明,这两种设计技术极大降低了芯片的功耗。     

一种超低输入共模电压的动态比较器电路设计

为了适应物联网低功耗的应用场景,并满足低电源电压和低输入共模电压的工作要求,提出了一种适用于超低输入共模电压的双正反馈回路动态比较器。该比较器采用时序开关控制输入输出,解决了传统动态比较器在输入电压低于阈值电压时无法正常工作的问题,增大了输入动态范围;电源到地之间仅堆叠两级MOS管,降低了最小电源电压;引入两个正反馈回路,提高了分辨率。采用TSMC 180 nm CMOS工艺设计和验证,仿真结果表明,在电源电压为900 mV,差模电压为1 mV情况下,提出的比较器最低共模电压为51 m V,与传统StrongARM动态比较器和DoubleTail动态比较器相比,分别降低了374 mV和264 m V;当输入共模电压低于阈值电压时,在中等的功耗下实现了最低的延时。     

面向控制流密集型电路的高层次低功耗方法*

通过对控制流密集型电路的分析和研究,提出一种面向控制流密集型电路的高层次低功耗综合方法。在调度过程中,应用分支控制和多电压两种方法对设计电路功耗进行双重优化。实验结果表明,在相同的时间和资源约束下,该方法比单独应用分支控制的调度方法功耗平均降低19.04%,比单独应用多电压的调度方法功耗平均降低5.74%。     

软件无线电架构的导航接收机模拟前端设计

针对基于超外差或低中频的传统导航接收机模拟前端电路功能复杂、功耗高、不利于单片集成等问题,基于模拟最小化,数字最大化的思想,通过芯片内部集成高增益射频放大器、低功耗的高速模数转换器、低抖动的时钟锁相环,创新性地设计并实现了一款基于软件无线电架构的接收机模拟前端电路。通过55 nm CMOS工艺电路设计、版图设计、仿真及硅流片验证,测试结果表明该接收机前端电路各模块功能正常,实现了单个模拟接收通道处理多模导航信号,极大地降低了模拟电路的规模及功耗并成功应用于一款多模导航SoC芯片中。     

Dual threshold voltage and sleep switch dual threshold voltage DOIND approach for leakage reduction in domino logic circuits

Subthreshold leakage current becomes the major component of total power dissipation as scaling down the feature size. In this paper, two new circuit techniques are proposed for reducing the subthreshold leakage power consumption in domino logic circuit. Dual threshold voltage DOIND (Domino logic with clock and input dependent transistors) and NMOS sleep switch dual threshold voltage DOIND circuits for low leakage domino logic circuits are presented. High threshold voltage transistors are utilized to reduce the leakage current and a sleep transistor is added to the dynamic node that strongly turnoff all the high threshold voltage transistor and significantly reduce the subthreshold leakage power. The proposed circuit techniques, dual threshold voltage DOIND logic and sleep switch dual threshold voltage DOIND logic reduces the leakage current by 71.46 and 74.86% respectively as compared to standard domino logic circuit. Simulation results also shows that both the circuits are less affected by supply and temperature variations. The proposed sleep switch dual threshold voltage DOIND exhibits 19.95% less power consumption with 24% die area overhead for the buffer circuit as compared to standard domino logic circuit. The proposed sleep switch dual threshold voltage DOIND logic has improved normalized figure of merit of 1.17 as compared to standard domino logic circuit.

     

深亚微米CMOS电路漏电流快速模拟器

随着工艺的发展 ,功耗成为大规模集成电路设计领域中一个关键性问题 降低电源电压是减少电路动态功耗的一种十分有效的方法 ,但为了保证系统性能 ,必须相应地降低电路器件的阈值电压 ,而这样又将导致静态功耗呈指数形式增长 ,进入深亚微米工艺后 ,漏电功耗已经能和动态功耗相抗衡 ,因此 ,漏电功耗快速模拟器和低功耗低漏电技术一样变得十分紧迫 诸如HSPICE的精确模拟器可以准确估计漏电功耗 ,但仅仅适合于小规模电路 首先证实了CMOS晶体管和基本逻辑门都存在堆栈效应 ,然后提出了快速模拟器的漏电模型 ,最后通过对ISCAS85& 89基准电路的实验 ,说明了在精度许可 (误差不超过 3% )的前提下 ,模拟器获得了成百倍的加速 ,同时也解决了精确模拟器的内存爆炸问题     

Exploiting dynamic micro-architecture usage in gate sizing

Modern high performance microprocessors incorporate an abundance of replicated structural components. Many of these components often experience substantially lower utilization while executing a diverse pool of applications. To recover energy efficiency from the lower utilization, system architects resort to dynamic voltage frequency scaling (DVFS). In this paper, we demonstrate that dynamic adaptations using DVFS are markedly energy inefficient than techniques that design circuits ground up for lower performance. We propose a novel microarchitecture aware gate sizing and threshold voltage assignment algorithm to mitigate this current limitation. Our technique is the first of its kind that exploits architectural slack in gate sizing, and leverages on-chip redundancy and slack. We evaluate this circuit-architectural co-optimization framework in a superscalar processor by combining standard cell based gate sizing flows with state-of-the-art architectural simulation. Our results show 17-46% improvement in the datapath energy efficiency over traditional circuit designs incorporating DVFS schemes.     

动态电压调节技术在高性能计算领域的能效研究

功耗问题是未来高性能计算机系统性能提高面临的最突出问题之一,本文调查典型的低功耗技术动态电压调节应用于高性能计算机系统的有效性。建立了动态电压调节技术在高性能计算领域的能耗模型,提出了程序运行时钟能耗和真实能耗的概念。在三种典型的计算机系统上,使用智能功率仪表测试使用动态电压调节技术后的系统能耗,说明了动态电压调节技术在高性能计算领域节能降耗的有效性。     

Low power high-speed multithreshold voltage CMOS bus architectures

Low power, high-speed bus architectures, based on low swing voltage technique, using multithreshold voltage transistors are proposed in this paper. Three different classes of driver/repeater/receiver circuits are introduced. The driver circuits are comprised of high threshold voltage MOSFET transistors, in order to reduce their output swing level voltage. For re-pulling up the low swing voltage to full swing, innovated high-speed, cross-coupled latch, voltage receiver circuits are used. In applications having high load capacitance due to long interconnections, novel repeater circuits based also on multithreshold voltage technology are introduced. Using 0.5 μm multithreshold voltage process technology and 1 V supply voltage, SPICE measurements showed up to 45% improvement in the power delay product.     

Toward low CPU usage and efficient DPDK communication in a cluster

In recent years, DPDK (Data Plane Development Kit, a data plane development tool set provided by Intel, focusing on high-performance processing of data packets in network applications), one of the high-performance packet I/O frameworks, is widely used to improve the efficiency of data transmission in the cluster. But, the busy polling used in DPDK will not only waste a lot of CPU cycles and cause certain power consumption, but also the high CPU usage will have a great impact on the performance of other applications in the host. Although some technologies, such as DVFS (dynamic voltage and frequency scaling, which is to dynamically adjust the operating frequency and voltage of the chip according to the different needs of the computing power of the application running on the chip, so as to achieve the purpose of energy saving) and LPI (low power idle, a technology that saves power by turning off the power of certain supporting circuits when the CPU core is idle), can reduce power consumption by adjusting CPU voltage and frequency, they can also cause performance degradation in other applications. Using thread sleep technology is a promising method to reduce the CPU usage and power consumption. However, it is challenging because the appropriate thread sleep duration cannot be obtained accurately. In this paper, we propose a model that finds the optimal thread sleep duration to solve the above challenges. From the model, we can balance the thread CPU usage and transmission efficiency to obtain the optimal sleep duration called the transmission performance threshold. Experiments show that the proposed models can significantly reduce the thread CPU usage. Generally, while the communication performance is slightly reduced, the CPU utilization is reduced by about 80%.

     

Comparing system level power management policies

Reducing power consumption is a challenge to system designers. Portable systems, such as laptop computers and personal digital assistants (PDAs), draw power from batteries, so reducing power consumption extends their operating times. For desktop computers or servers, high power consumption raises temperature and deteriorates performance and reliability. Soaring energy prices and rising concern about the environmental impact of electronics systems further highlight the importance of low power consumption. Power reduction techniques can be classified as static and dynamic. Static techniques, such as synthesis and compilation for low power, are applied at design time. In contrast, dynamic techniques use runtime behavior to reduce power when systems are serving light workloads or are idle. These techniques are known as dynamic power management (DPM). DPM can be achieved in different ways; for example, dynamic voltage scaling (DVS) changes supply voltage at runtime as a method of power management. Here, we use DPM specifically for shutting down unused I/O devices. We built an experimental environment on a laptop computer running Microsoft Windows. We implemented existing power management policies and quantitatively compared their effects on power saving and performance degradation     

Improved optical feedback for OLED differential ageing correction

Abstract— To compete with LCDs and to meet standard display product specifications, OLED displays must have a high degree of tolerance to differential ageing or “burn‐in.” A new optical feedback pixel circuit is presented that enables accurate differential ageing correction, can have low power consumption, and enables a high degree of non‐uniformity correction. The circuit can be implemented in LTPS, and a‐Si:H TFT technologies and circuits for both cases are shown. The a‐Si:H approach is low cost and enables correction of both TFT threshold voltage drift and OLED degradation at the same time. The circuit analysis, operation, and technology will be described and results presented.     

Power-aware fixed priority scheduling for sporadic tasks in hard real-time systems

In this paper, we consider the generalized power model in which the focus is the dynamic power and the static power, and we study the problem of the canonical sporadic task scheduling based on the rate-monotonic (RM) scheme. Moreover, we combine with the dynamic voltage scaling (DVS) and dynamic power management (DPM). We present a static low power sporadic tasks scheduling algorithm (SSTLPSA), assuming that each task presents its worst-case work-load to the processor at every instance. In addition, a more energy efficient approach called a dynamic low power sporadic tasks scheduling algorithm (DSTLPSA) is proposed, based on reclaiming the dynamic slack and adjusting the speed of other tasks on-the-fly in order to reduce energy consumption while still meeting the deadlines. The experimental results show that the SSTLPSA algorithm consumes 26.55–38.67% less energy than that of the RM algorithm and the DSTLPSA algorithm reduces the energy consumption up to 18.38–30.51% over the existing DVS algorithm.     

Energy aware fixed priority scheduling in mixed-criticality systems

Most of studies about energy management for MC systems are based on dynamic priority scheme. The disadvantages of dynamic priority scheme are high system overhead and poor predictability. Unlike previous studies, we focus on the problem of scheduling mixed-criticality (MC) periodic tasks with minimizing energy consumption in MC systems based on fixed priority scheme. Firstly, we explain a criticality rate monotonic scheduling (CRMS) and propose the sufficient schedulability condition of CRMS. Secondly, we compute the energy minimization uniform scaled speed and present an optimal static solution algorithm based on CRMS. The extra workload of the high criticality level (HI) task executes with the maximum processor speed in the high criticality mode (HI-mode). But this algorithm does not exploit the slack time generated from the HI task in the low criticality mode (LO-mode). For energy efficiency, we propose a dynamic fixed priority energy minimization algorithm which exploits the slack time generated from the HI task in LO-mode to save energy. In addition, it combines a dynamic voltage and frequency scaling technique and a dynamic power management technique to reduce energy consumption. Finally, the experiments are applied to evaluate the performance of the proposed algorithm and the experimental results show that the proposed algorithm can save up 23.89% energy compared with other existing algorithms.