A 2.4GHz Low Power ASK Transmitter for Wireless Capsule Endoscope Applications

提出了一种应用于无线内窥镜系统的2.4GHz低功耗ASK发射机.为了获得高的数据传输速率,采用了基于混频器的直接上变换发射机结构.为了节省功耗,提出了一种基于电流复用技术的伪差分堆栈结构的A类功放.低功耗发射机由两部分组成:基于恒幅度锁相环(PLL)的20MHz的ASK基带调制器和直接上变换的射频电路.该设计已经采用TSMC 0.25μm CMOS工艺实现并进行了验证.测试结果表明,发射数据速率为1Mbps时,发射机的输出功率为-23.217dBm.采用单2.5V的电源供电下,低功耗发射机消耗的电流约为3.17mA.     

A Novel Rate Control Method for Low Delay Applications

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A High Linearity and Low Power 3.1–10.6GHz CMOS Up-Conversion Mixer for UWB Applications

This paper proposed a full band up-mixer implemented in 0.18μm COMS process for UWB wireless systems. The linearity, noise figure and other performance are improved by using current bleeding technique and inserting a LC network on common source nodes of the switches stage. The inductance peaking technique is adopted to flatten conversion gain over the 14 sub-bands of UWB system. The up-converting mixer converts an input of 264MHz intermediate frequency to an output of 3.1–10.6GHz radio frequency signal. From the post simulation results, the proposed up-mixer achieves conversion gain of 10±1dB and the IIP3 of 7.19dBm and power consumption of 2.4mW at 1.2V power supply.     

Optimization and Design of a Low Power Switched Current A/D-ΣΔ-Modulator for Voice Band Applications

This paper presents a third order switched current -modulator. The modulator is optimized at the system level for minimum power consumption by careful design of the noise transfer function. A thorough noise analysis of the cascode type current copiers used to implement the modulator, together with a new methodology for evaluating the nonlinear settling behavior is presented. This leads to a new optimization methodology that minimize the power consumption in switched current circuits for given design parameters. The optimization methodology takes process variations into account. The modulator is implemented in a standard 2.4 m CMOS process only using MOS capacitors. For a power supply of 3.3 V the power consumption is approximately 2.5 mW when operating at a sampling rate of 600 kHz. Under these condition the peak SNR it measured to 74.5 dB with a signal band width of 5.5 kHz. Due to internal clamping in the integrators and proper scaling the modulator shows excellent stability properties. In order to compare the performance of the modulator presented in this paper to other -modulators two figure-of-merits (FOMs) are proposed. From these figure-of-merits it is found that the performance of the modulator presented in this paper is significantely higher than the perforamce of other switched current -modulators reported. Also, the figure-of-merits show that the performance is comparable to the performance of reported switched capacitor -modulators.     

A Low Power SRAM/SOI Memory Cell Design

提出一种改进4管自体偏压结构SRAM/SOI单元. 基于TSUPREM4和MEDICI软件的模拟和结构性能的分析，设计单元结构并选取结构参数. 该结构采用nMOS栅下的含p+埋沟的衬底体电阻代替传统6管CMOS SRAM单元中的pMOS元件，具有面积小、工艺简单的优点. 该结构可以在0.5V的电源电压下正常工作，与6管单元相比，该单元瞬态响应正常，功耗只有6管单元的1/10，满足低压低功耗的要求.     

A Maintenance Inspection Model for a Single Machine

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A HistogramBased Static Error Correction Technique for Flash ADCs： Implementation

In this paper, we focus on practical issues in implementing a calibration technique for medium-resolution, high-speed flash analog-to-digital converters (ADCs). In [1], we theoretically describ the calibration technique and perform a behavioral-level simulation to test its functionality [1]. In this work, we discuss some issues in transistor-level implementation. The predominant factors that contribute to static errors such as reference generator mismatch and track-and-hold (T/H) gain error can be treated as input-referred offsets of each comparator. Using the proposed calibration technique, these errors can be calibrated with minimal detriment to the dynamic performance of the converter. We simulate a transistor-level implementation of a 5-bit, 1 GHz ADC in a 1.2 V, 65 nm CMOS process. The results show that DNL can be improved from 2.5 LSB to below 0.7 LSB after calibration, and INL can be improved from 1.6 LSB to below 0.6 LSB after calibration.     

Optical Fiber Instrument for Single—point Multi—parameter Measurement

A novel kind of optical fiber instrument for two-channel measurement of temperature and displacement was developed.Four-channel quartz fiber optics were emplotyed to measure two-channel signals of temperature and displacement simultaneously, and the operating efficiency of this instrument was greatly improved.     

A Wide-Band Low Noise Amplifier for Terrestrial and Cable Receptions

提出并设计了一种用于数字电视接收调谐芯片的宽带低噪声放大器.该设计采用0.35μm SiGe BiCMOS工艺,器件的主要性能为:增益等于18.8dB,增益平坦度小于1.4dB,噪声系数小于5dB,1dB压缩点为-2dBm,输入三阶交调为8dBm.在5V供电的情况下,直流功耗为120mW.     

An Improved Single Stage Phase Shifted Control Based AC–DC PFC Converter for Wireless Applications

Recently, many researchers has more attention in a single stage AC to DC converter features and DC to DC regulator are extensively used into low power applications. When compared with the two stage conventional method over the Single stage converter has a simple design and utilize only less components. Therefore, this task has been used in this paper as a prposed work of AC–DC single stage converters combine a converter front end with DC–DC back end converter. This proposed work has been improved single stage power factor correction (PFC) converter based on phase-shifted controller for wireless Power applications. The proposed technique employed to develop the improved converter for task of an extensive series of voltage outputs with rippleless outcomes in low frequency, that shows the high essential in battery application and the PFC duty ratio restriction is eradicated. Similarly, DC–DC stage operation are designed in a related way of conventional full bridge phase shifted converter. Accordingly, the proposed technique of improved converter of this paper will achieves better efficiency compared with other conventional techniques and it has been prove more efficient for many Industrial applications, it has been discussed in result section clearly. The experimental results of proposed improved converter proves that it is potential to extend high power single stage converter with good power factor, conversion characteristics and efficiency.

     

A Novel Offset-Cancellation Technique for Low Voltage CMOS Differential Amplifiers

基于对CMOS差分放大器的非线性和元件失配理解的基础上,提出了一种应用于低电压CMOS差分放大器的失调取消技术.这种技术在不需要增加功耗的基础上,通过把输出端的失调电压转移到差分放大器的其他节点,从而达到减小输入参考的失调电压的目的.为了验证这种技术,设计了一个工作电压为1.8V的低失调的CMOS差分放大器.仿真结果表明,在负载晶体管的失配为20%,输入放大管的失配为10%时,利用这种失调转移技术,输入参考的失调可以减少40%.同已发表的失调取消技术相比,利用这种技术可以达到更低的功耗和更高的集成度.     

Digital Homes — For Richer for Poorer, Who are They for?

Networked homes which support and use high technology services are usually seen as the domain of top-of-the-range, executive properties. However, there is growing evidence that this is not necessarily the case and that technology can be used to bring cost-effective benefits to a wide range of people. This paper looks at the digital home from a customer viewpoint, where the customers are home builders or developers, housing associations or local authorities, home owners or tenants. Their individual requirements and expectations are explored, along with a framework for identifying and delivering the advantages of the digital home.     

A Micropower Pulsewidth-Modulation?Pulse-Position-Modulation Two-Channel Telemetry System for Biomedical Applications

A novel micropower, two-channel telemetry system, which has been used to transmit the occurrence of the QRS complex of the heart waveform and temperature information, is described. The system employs pulsewidth-modulation (PWM) and pulse-position-modulation (PPM) methods plus a few unique circuits and system-design techniques so that it has the following desirable features. 1) The transmitting unit consumes extremely low power due to low duty cycle and yet delivers high peak power for better receiving. In addition, the unit is compensated (not regulated) for battery voltage variation. 2) By means of adaptive threshold, pulse-width-discrimination and pulse-rate-discrimination networks, the receiving unit is relatively noise free in signal identification. Information in analog and digital form are available at the output for convenience. A prototype system was designed and fabricated. Test results are presented. Due to the availability of the integrated circuits on the market, medical doctors and biologists will be able to duplicate the system if the system-size problem is not severe. Although the design was not trivial, the implementation is quite straightforward. Hence it is believed that device or integrated-circuit manufacturers would be able to implement it in a much more compact form.     

Design and Fabrication of Power Si1-xGex/Si Heterojunction Bipolar Transistor for Wireless Power Amplifier Applications

采用简单的双台面工艺制作了完全平面结构的2个单元4个发射极指的SiGe HBT.在没有扣除测试结构的影响下,当直流偏置IC=10mA,VCE=2.5V时,FT和fmax分别为1.8和10.1GHz.增益β为144.25,BVCBO为9V.     

A Stable Low Power Dissipating 9 T SRAM for Implementation of 4 × 4 Memory Array with High Frequency Analysis

Wireless Personal Communications - Today’s high speed data processing and memory storage operations demand immediate data write and retrieval to meet up to benchmark. To act as a volatile or...     

A Low Complexity Decoding Algorithm for STBC under Non-Constant Module Modulation

This paper presents a low complexity algorithm for the decoding of space-time block codes （STBC） under non-constant module modulation. Simulation results show that in most cases of non-constant module modulation the new algorithm results in more than 50% reduction in computation complexity comparing to the original maximum likelihood algorithm without any loss of BER performance.     

Electrical Power Vision 2040 for Europe—a EUREL study

A special task force of EUREL, the European organisation of electrical engineers, has recently published the study “Power Vision 2040 for Europe”. The study investigates the actual status of the power supply of the EU27+, estimates the future electricity demand and identifies future applicable technologies. As part of the study scenarios for the future European power supply were developed.     

A 0.8 μm BiCMOS Gate Driver for IGBT Power Switch

This paper discusses the design and implementation of a monolithic gate driver for an Insulated Gate Bipolar Transistor (IGBT). The objective is to implement a high voltage (25 V) monolithic gate driver with a novel protection circuit in a conventional low-voltage (5 V) high-density (0.8 m) BiCMOS process. Extended drain MOS-FETs are used to implement the high-voltage capability in this design.