全耗尽SOI MOSFETs阈值电压和电势分布的温度模型

提出了一个全耗尽SOI MOSFETs器件阈值电压和电势分布的温度模型.基于近似的抛物线电势分布模型,利用适当的边界条件对二维的泊松方程进行求解.同时利用阈值电压的定义得到了阈值电压的模型.该温度模型详细地研究了电势分布和阈值电压跟温度之间的变化关系,同时还近似地探讨了短沟道效应.为了进一步验证模型的正确性,利用SILVACO ATAS软件进行了相应的模拟.结果表明,模型计算与软件模拟吻合较好.     

一种非均匀掺杂的全耗尽SOI-MOSFET阈值电压模型(英文)

对垂直于沟道的二维电势分布函数提出了一种新的近似,给出了基于这种近似的杂质浓度呈高斯分布的非均匀掺杂全耗尽SOI-MOSFET的阈值电压解析模型.模型结果与MEDICI数值模拟结果符合得很好,表明了模型的准确性,这为实践中分析与控制非均匀掺杂的全耗尽SOI-MOSFET的阈值电压提供了一种新的途径.     

一种非均匀掺杂的全耗尽SOI-MOSFET阈值电压模型

对垂直于沟道的二维电势分布函数提出了一种新的近似,给出了基于这种近似的杂质浓度呈高斯分布的非均匀掺杂全耗尽SOI-MOSFET的阈值电压解析模型.模型结果与MEDICI数值模拟结果符合得很好,表明了模型的准确性,这为实践中分析与控制非均匀掺杂的全耗尽SOI-MOSFET的阈值电压提供了一种新的途径.     

一种非均匀掺杂的全耗尽SOI-MOSFET阈值电压模型

对垂直于沟道的二维电势分布函数提出了一种新的近似,给出了基于这种近似的杂质浓度呈高斯分布的非均匀掺杂全耗尽SOI-MOSFET的阈值电压解析模型.模型结果与MEDICI数值模拟结果符合得很好,表明了模型的准确性,这为实践中分析与控制非均匀掺杂的全耗尽SOI-MOSFET的阈值电压提供了一种新的途径.     

双栅无结晶体管阈值电压模型

无结晶体管是近年来纳米SOI MOS器件领域的研究热点,相对于传统晶体管具有明显的优势。本文针对全耗尽型无结晶体管,基于二维泊松方程,建立了电势分布解析模型。根据该模型可以得到阈值电压模型。利用建立的解析模型和半导体器件仿真软件MEDICI,探讨了栅压和器件结构参数对电势分布和阈值电压的影响。该模型简单且与仿真结果吻合良好。     

全耗尽SOI LDMOS阈值电压的解析模型

通过准二维的方法,求出了全耗尽SOILDMOS晶体管沟道耗尽区电势分布的表达式,并建立了相应的阈值电压模型。将计算结果与二维半导体器件模拟软件MEDICI的模拟结果相比较,两者误差较小,证明了本模型的正确性。从模型中可以容易地分析阈值电压与沟道浓度、长度、SOI硅膜层厚度以及栅氧化层厚度的关系,并且发现ΔVth与背栅压的大小无关。     

2D Threshold-Voltage Model for High-k Gate-Dielectric MOSFETs

给出包括栅电介质与耗尽层区域的边界条件和二维沟道电势分布.根据这个电势分布,得出高k栅介质MOSFET的阈值电压模型,模型中考虑短沟道效应和高k栅介质的边缘场效应.模型模拟结果和实验结果能够很好地符合.通过和一个准二维模型的结果相比较,表明该模型更准确.另外,还详细讨论了影响高k栅电介质MOSFET阈值电压的一些因素.     

高k栅介质MOSFETs的二维阈值电压模型

给出包括栅电介质与耗尽层区域的边界条件和二维沟道电势分布.根据这个电势分布,得出高k栅介质MOSFET的阈值电压模型,模型中考虑短沟道效应和高k栅介质的边缘场效应.模型模拟结果和实验结果能够很好地符合.通过和一个准二维模型的结果相比较,表明该模型更准确.另外,还详细讨论了影响高k栅电介质MOSFET阈值电压的一些因素.     

An Analytical Threshold Voltage Model for Fully Depleted SOI MOSFETs

提出了一种新的全耗尽SOI MOSFETs阈值电压二维解析模型.通过求解二维泊松方程得到器件有源层的二维电势分布函数,氧化层-硅界面处的电势最小值用于监测SOI MOSFETs的阈值电压.通过对不同栅长、栅氧厚度、硅膜厚度和沟道掺杂浓度的SOI MOSFETs的MEDICI模拟结果的比较,验证了该模型,并取得了很好的一致性.     

全耗尽SOI MOSFETs阈值电压解析模型

提出了一种新的全耗尽SOI MOSFETs阈值电压二维解析模型.通过求解二维泊松方程得到器件有源层的二维电势分布函数,氧化层-硅界面处的电势最小值用于监测SOI MOSFETs的阈值电压.通过对不同栅长、栅氧厚度、硅膜厚度和沟道掺杂浓度的SOI MOSFETs的MEDICI模拟结果的比较,验证了该模型,并取得了很好的一致性.     

双离子注入短沟道MOS FET的阈值电压解析模型

本文对短沟道MOSFET沟道区的硼、砷离子注入分布采用二次函数及指数函数的分段函数分布近似,并利用格林函数法求解二维泊松方程,从而导出非均匀分布短沟道MOS FET的表面势和阈值电压的解析模型.它计及注入能量、剂量、退火温度、退火时间等工艺参数的影响,也包含了漏极电压V_D和栅氧化层厚度等因素的影响.本解析模型的结果与用MINI-MOS数值模拟的结果符合得很好,具有简单、实用的特点.适用于改进有关电路分析程序例如SPICE中的模型.     

异质栅单Halo沟道SOI中隐埋层对器件特性的影响

研究异质栅单Halo沟道SOI MOS器件的隐埋层中二维效应对器件特性,如电势分布、阈值电压等的影响,仿真结果表明,隐埋层中的二维效应会引起更明显的SCE及DIBL效应.在考虑隐埋层二维效应的基础上,提出了一个新的二维阈值电压模型,能较好地吻合二维器件数值模拟软件Medici的仿真结果.     

Modelling the threshold voltage of short-channel silicon-on-insulator MOSFETs

A simple analytical model for the threshold voltage of short-channel, thin-film, fully-depleted silicon-on-insulator MOSFETs is presented. The model is based on the analytical solution for the two-dimensional potential distribution in the silicon film, which is taken as the sum of the long-channel solution to the Poisson equation and the short-channel solution to the Laplace equation. The model shows close agreement with numerical PISCES simulation results. The equivalence between the proposed model and the parabolic model of Young (1989) is also proven.<>     

Threshold voltage model for deep-submicron fully depleted SOI MOSFETs with back gate substrate induced surface potential effects

A simple analytical threshold voltage model for short-channel fully depleted SOI MOSFETs has been derived. The model is based on the analytical solution of the two-dimensional potential distribution in the silicon film (front silicon), which is taken as the sum of the long-channel solution to the Poisson's equation and the short-channel solution to the Laplace equation, and the solution of the Poisson's equation in the silicon substrate (back silicon). The proposed model accounts for the effects of the back gate substrate induced surface potential at the buried oxide-substrate interface which contributed an additional 15–30% reduction in the threshold voltage for the devices used in this work. Conditions on the back gate supply voltage range are determined upon which the surface potential at the buried oxide-substrate interface is accumulated, depleted, or inverted. The short-channel associated drain induced barrier lowering effects are also included in the model. The model predications are in close agreement with PISCES simulation results. The equivalence between the present model and previously reported models is proven. The proposed model is suitable for use in circuit simulation tools such as Spice.     

An analytical threshold voltage model of NMOSFETs with hot-carrier induced interface charge effect

An analytical threshold voltage model of NMOSFETs including the effect of hot-carrier-induced interface charges is presented. A step function describing the interface charge distribution along the channel is used to account for the hot carrier induced damage, and a pseudo-2D method is applied to derive the surface potential. The threshold voltage model is then developed by solving the gate-to-source voltage at the onset of surface inversion where the minimum surface potential equals the channel potential. Both the drain-induced barrier lowering (DIBL) and body effects are included in the present model as well. The present threshold voltage model is validated for both fresh and damaged devices. The results show that the threshold voltage shifts upward and approaches a maximum value with negative interface charges and shifts downward and reaches a minimum value with positive interface charges as the interface charge region length is increased from zero to the channel length. Model is successfully verified using simulation data obtained from TCAD (technology-based computer-aided design).