共查询到19条相似文献,搜索用时 156 毫秒
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探讨了高速图像采集系统中高速采样缓存的重要性和实现途径,阐述了基于框架式结构的32通道图像数据采集系统中的高速缓存的设计与电路结构,给出了采用FPGA实现通道复用和采集数据预处理,并结合计算机数据采集和显示技术完成对多路图像的显示方案. 相似文献
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设计电路时,在满足电路性能和可靠性要求的情况下,要尽量降低电路的成本.文中介绍了阻容耦合放大电路板可靠性设计的4个步骤:失效率估计、元器件筛选、减额设计、失效率分配与统计.首先对系统的总失效率进行了估计,介绍了元器件的筛选方法,然后计算出了电路各元件的电应力,根据电应力和失效率分配选择元器件,设计出符合要求的电路板. 相似文献
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为适应目前无线通信领域对高速A/D转换器的要求,采用在Cadence Spectre环境下进行仿真验证的方法,对高速A/D前端采样保持电路进行了研究.提出的高速采样保持电路(SH)采用SiGe BiCMOS工艺设计,该工艺提供了0.35 μm的CMOS和46 GHz TT的SiGe HBT.基于BiCMOS开关射极跟随器(SEF)的SH,旨在比二极管桥SH消耗更少的电流和面积.在SH核心,电源电压3.3 V,功耗44 mW.在相干采样模式下,时钟频率为800 MHz时,其无杂波动态范围(SFDR)为-52.8 dB,总谐波失真(THD)为-50.4 dB,满足8 bit精度要求.结果显示设计的电路可以用于中精度、高速A/D转换器. 相似文献
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用通用运算放大器构成的用于线阵 CCD 输出信号处理的相关双σ取样电路,其取样速率可达250kHz。电路简单实用。本文着重讨论了有关元器件参数的选取原则,这对于设计高速双σ采样/保持电路有一定参考价值。 相似文献
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介绍了一种能完成高速采样保持功能的电路,与一般的准高速采样保持电路相比,后者采样时间长,不能满足激光窄脉冲信号的采样要求。国外高速采样保持集成电路器件价格昂贵、体积较大、使用不便,难以普及应用。准高速采样保持电路响应时间短、电路简单、成本低、能较好地满足峰值存贮的要求。通过电路试验和整机试验证明电路是可行的。 相似文献
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介绍了一种采用CPLD和SRAM设计的高速数据缓存队列(FIFO)电路.采用双缓冲输入结构,并且当后级电路空闲时,能主动向外部推送数据.因为设计有总线仲裁逻辑,所以可以用较低的时钟频率进行高速的数据缓存与传输.不仅具有电路简单,成本低的优点,而且可靠性高,已经成功应用在广播电视CPCI监测仪中,用统一的接口电路实现了对有线、无线数字广播电视以及模拟广播电视全兼容. 相似文献
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在高速图像采集中,需要对采集的大量数据进行实时存储。介绍了一种基于FPGA控制的高速图像实时存储系统,该系统能在脱机方式下由FPGA直接控制IDE硬盘,实现高速图像的实时存储,并通过PCI接口对硬盘进行事后访问。目前,采用单硬盘时的记录速度可达到24 MB/s。 相似文献
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Iboun Taimiya Sylla Mustapha Slamani Bozena Kaminska 《Journal of Electronic Testing》2001,17(1):53-61
The availability of faster electronic components allows the design of more effective and efficient test equipments. However in high-speed applications, the effect of interconnects between the tester and the device under test DUT introduces ringing, overshoot and timing delay problems. In this paper we present an output high speed buffer which helps to cancel the overshoot, undershoot, and ringing. The buffer which has a unity gain, presents a high output current and introduces small delay. It is able to drive the comparator of the tester through the transmission line with minimum distortion of the signal. Compared with other approaches, the use of this output buffer provides good improvement of the signal. This output buffer which is designed for the interface between tester and DUT can be considered for communication between high speed devices in printed circuits boards. The calibration procedure is explained in order to determine the delay introduced by the buffer and to measure low and high voltage levels of the digital output signal of the buffer. 相似文献
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Modern switches and routers require massive storage space to buffer packets. This becomes more significant as link speed increases and switch size grows. From the memory technology perspective, while DRAM is a good choice to meet capacity requirement, the access time causes problems for high‐speed applications. On the other hand, though SRAM is faster, it is more costly and does not have high storage density. The SRAM/DRAM hybrid architecture provides a good solution to meet both capacity and speed requirements. From the switch design and network traffic perspective, to minimize packet loss, the buffering space allocated for each switch port is normally based on the worst‐case scenario, which is usually huge. However, under normal traffic load conditions, the buffer utilization for such configuration is very low. Therefore, we propose a reconfigurable buffer‐sharing scheme that can dynamically adjust the buffering space for each port according to the traffic patterns and buffer saturation status. The target is to achieve high performance and improve buffer utilization, while not posing much constraint on the buffer speed. In this paper, we study the performance of the proposed buffer‐sharing scheme by both a numerical model and extensive simulations under uniform and non‐uniform traffic conditions. We also present the architecture design and VLSI implementation of the proposed reconfigurable shared buffer using the 0.18 µm CMOS technology. Our results manifest that the proposed architecture can always achieve high performance and provide much flexibility for the high‐speed packet switches to adapt to various traffic patterns. Furthermore, it can be easily integrated into the functionality of port controllers of modern switches and routers. Copyright © 2008 John Wiley & Sons, Ltd. 相似文献
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