An analytical transient model for a 1.5 V BiCMOS dynamic logiccircuit for low-voltage deep submicrometer BiCMOS VLSI

This paper presents an analytical transient model for the 1.5 V BiCMOS dynamic logic circuit using Gummel-Poon charge control model for deep submicrometer BiCMOS VLSI. Based on the analysis, the switching time of the 1.5 V BiCMOS dynamic circuit is sensitive to the forward transit time with a large load capacitance. With a small load capacitance, its switching time is related to the threshold voltage     

An analytical approach for physical modeling of hot-carrier induced degradation

We develop an analytical model for hot-carrier degradation based on a rigorous physics-based TCAD model. The model employs an analytical approximation of the carrier acceleration integral (calculated with our TCAD approach) by a fitting formula. The essential features of hot-carrier degradation such as the interplay between single-and multiple-electron components of Si–H bond dissociation, mobility degradation during interface state build-up, as well as saturation of degradation at long stress times are inherited. As a result, the change of the linear drain current can be represented by the analytical expression over a wide range of stress conditions. The analytical model can be used to study the impact of device geometric parameters on hot-carrier degradation.     

Testability analysis and fault modeling of BiCMOS circuits

Defect models have been used for testability analysis of BiCMOS circuits and the results have been compared with an analysis of CMOS circuits. Using a nominal point approach, faults generated are classified as logical or performance degradation faults. It is found that logical fault testing can only cover a small percentage of the total fault set, 54% for BiCMOS, versus 69% for equivalent CMOS gates. Delay faults and current faults are analyzed as applied to BiCMOS and CMOS gates. It is shown that logical fault testing in conjunction with either delay fault testing or current fault testing promises the highest fault coverage for BiCMOS logic gates, around 95%.This research was partially supported by the Department of National Defence of Canada, Academic Research Program, grant # 3705-921.     

The time-frequency distributions of nonstationary signals based ona Bessel kernel

A kernel based on the first kind Bessel function of order one is proposed to compute the time-frequency distributions of nonstationary signals. This kernel can suppress the cross terms of the distribution effectively. It is shown that the Bessel distribution (the time-frequency distribution using Bessel kernel) meets most of the desirable properties with high time-frequency resolution. A numerical alias-free implementation of the distribution is presented. Examples of applications in time-frequency analysis of the heart's sound and Doppler blood flow signals are given to show that the Bessel distribution can be easily adapted to two very different signals for cardiovascular signal processing. By controlling a kernel parameter, this distribution can be used to compute the time-frequency representations of transient deterministic and random signals. The study confirms the potentials of the proposed distribution in nonstationary signal analysis     

FinFET design considerations based on 3-D simulation and analytical modeling

Design considerations of the FinFET have been investigated by three-dimensional (3-D) simulation and analytical modeling in this paper. Short-channel effects (SCE) of the FinFET can be reasonably controlled by reducing either silicon fin height or fin thickness. Analytical solution of 3-D Laplace's equation is employed to establish the design equations for the subthreshold behavior in the fully depleted silicon fins. Based on the 3-D analytical electrostatic potential in the subthreshold region, the threshold voltage (V/sub th/) roll-off and the subthreshold swing (S) are estimated by considering the source barrier changes in the most leaky channel path. V/sub th/ roll-off is an exponential function of the ratio of effective channel length to drain potential decay length, which can then be expressed as a function of the fin thickness, the fin height and the gate oxide thickness. The drain-potential decay lengths of single-gate fully depleted SOI MOSFET (FDFET), double-gate MOSFET (DGFET), rectangular surrounding-gate MOSFET (SGFET), and FinFET are compared. The drain potential scaling length and V/sub th/ roll-off can be included into a universal relation for convenient comparison.     

Evaluation of LDD MOSFET's based on hot-electron-induced degradation

Hot-electron-induced device degradation in LDD MOSFET's is thoroughly studied. Conventional ways to characterize device degradation, i.e., threshold shift and transconductance reduction, are not suitable for LDD MOSFET's due to the nature of degradation in such devices. Using a current-drive degradation criterion, it is shown that LDD MOSFET's have little net advantage over conventional MOSFET's in terms of hot-electron-induced long-term degradation.     

Sensorless field orientation control of induction machines based ona mutual MRAS scheme

A mutual model reference adaptive system (MRAS) is proposed to implement a position sensorless field-orientation control (FOC) of an induction machine. The reference model and adjustable model used in the mutual MRAS scheme are interchangeable. Therefore, it can be used to identify both rotor speed and the stator resistance of an induction machine. For the rotor speed estimation, one model is used as a reference model and another is the adjustable model. Pure integration and stator leakage inductance are removed from the reference model, resulting in robust performance in low and high speed ranges. For the stator resistance identification, the two models switch their roles. To further improve estimation accuracy of the rotor speed and stator resistance, a simple on-line rotor time constant identification is included. Computer simulations and experimental results are given to show its effectiveness     

Evaluation of three-level rectifiers for low-voltage utility applications

This paper evaluates the benefits of three-level topologies as alternatives to two-level topologies in low-voltage converters primarily operated in rectifier mode. The main evaluation aspects are input filter size, semiconductor losses, maximum switching frequency, part count, initial cost, and life cycle cost. Semiconductor loss characteristics of various three-level topologies are discussed. A detailed converter comparison is based on a 100-kW 400-V/sub rms/ rectifier using commercially available Si insulated gate bipolar transistor modules.     

SOI flash memory scaling limit and design consideration based on 2-D analytical modeling

In this paper, the short-channel effect in ultrathin body (UTB) SOI Flash memory cell induced by the floating-gate is investigated by a newly developed two-dimensional analytical model. A concept of effective natural length (/spl lambda//sub eff/) is introduced as a measure of the impact of the floating-gate on the scaling limit. Even though scaling the channel thickness can significantly reduce SCE in UTB MOSFET, it becomes less effective in floating-gate device due to the floating polysilicon induced gate coupling. To minimize the floating-gate induced SCEs, the drain to floating-gate coupling has to be minimized.     

Retarding effect of surface base compensation on degradation of noise characteristics of BiCMOS BJTs

Hot carrier degradation of 1/f noise characteristics of bipolar junction transistors is found to be substantially reduced by arsenic surface compensation of the base region, in agreement with former reports on the improvement in reliability of such devices, inferred from their static characteristics studies.     

Improved analytical modeling of conductive losses in magneticcomponents

The one well-known one-dimensional method for calculating the AC resistance of multilayer transformer windings contains a built-in orthogonality which has not been reported previously. Orthogonality between skin effect and proximity effect makes a more generalized approach for the analytical solution of AC resistance in windings possible. This includes a method to calculate the AC resistance of round conductor windings which is not only convenient to use, but gives more accurate answers than the basic one-dimensional method because the exact analytical equations for round conductors can be used     

Two-dimensional analytical modeling of threshold voltages of short-channel MOSFET's

We present an analytical model of the threshold voltage of a short-channel MOSFET based on an explicit solution of two-dimensional Poisson's equation in the depletion region under the gate. This model predicts an exponential dependence on channel length (L), a linear dependence on drain voltage (VD), and an inverse dependence on oxide capacitance (εox/tox). An attractive feature of this model is that it provides an analytical closed-form expression for the threshold voltage as a function of material and device parameters (tox, VD, L, substrate bias, and substrate doping concentration) without making premature approximations. Also, this expression reduces to the corresponding expression for long-channel devices.     

On-state analytical modeling of IGBTs with local lifetime control

A two-dimensional on-state analytical model of the insulated gate bipolar transistor (IGBT) with local lifetime control is developed. The model accounts for the effect of local lifetime killing in particular the effective value of the lifetime and the position of the local lifetime control region on the excess carrier distribution in the IGBT during its on-state operation. It is shown that the local lifetime killing in the vicinity of the anode junction causes a reduction in the anode injection efficiency leading to improved on-state/turn-off behavior. The accuracy of the analytical model is verified through numerical simulations carried out using the MEDICI device simulator.     

A new modeling and optimization of gain-boosted cascode amplifier for high-speed and low-voltage applications

Because of limited output swing, the basic structure of a gain-boosted cascode amplifier (GBCA) cannot be used to design a low-voltage operational amplifier. In this paper, we investigate the design of a high-swing GBCA, and find the optimum bandwidth for the boosting or feedback amplifier. This bandwidth eliminates the slow-settling component in the step response, prevents the gain-boosting loop from being unstable, and results in the shortest settling time. Finally, we present a very high-speed and high-swing amplifier suitable for low-voltage applications.     

基于DS-OFDM的电力线通信抗干扰性能研究

近年来电力线通信得到了快速的发展,但由于低压电力线信道特性异常恶劣,在使用电力线进行通信的过程中存在着各种各样的干扰和衰减,这些干扰和衰减严重影响了低压电力线的通信质量。本文在研究扩频通信和正交频分复用技术的抗干扰性能基础上,提出了新的抗干扰方案,即DS-OFDM方案,并使用MATLAB对本方案的抗干扰性能进行了仿真验证。结果表明,扩频技术和OFDM相结合能较好地抑制低压电力线信道中的干扰和衰减,该方案可广泛应用于低压电力线通信中。     

A novel analytical framework compounding statistical traffic modeling and aggregate-level service curve disciplines: network performance and efficiency implications

This paper demonstrates that higher network resource efficiency can be achieved by using resource management protocols which consider service disciplines based on service curves together with statistical traffic modeling. To this end, an appropriate analytical framework is introduced which allows calculation of the performance statistically guaranteed to any flow out of an aggregate. This feature enables the analytical framework to be applied to the elements of the core network where aggregates of traffic are considered instead of single flows in order to avoid scalability problems. Given that flows are modeled in the analytical framework through switched batch Bernoulli processes (SBBPs), the whole queueing system is denoted as SBBP/Sc/1/K. The performance is calculated in terms of loss probability and delay distribution. The proposed framework is applied in a significant multinode case study.     

Investigation of degradation mechanisms in low-voltage p-channel power MOSFETs under High Temperature Gate Bias stress

In this work we investigate the degradation mechanisms occurring in a p-channel trench-gate power MOSFET under High Temperature Gate Bias (HTGB) stress. The impact of negative bias temperature stress is analysed by evaluating relevant figures of merit for the considered device: threshold voltage, transconductance and on-resistance. Temperatures and gate voltages as large as 175 °C and −24 V, respectively, are adopted to accelerate the degradation in the device. Moreover, in order to investigate the origin of degradation mechanisms we analyse the interface states generation and the charge trapping processes, the impact of a switching gate voltage during the stress phase and the recovery phase after HTGB stress.     

A physical-based analytical model for hot-carrier inducedsaturation current degradation of p-MOSFET's

The delay time of a CMOS inverter is directly related to the p-MOSFET saturation current. An accurate aging model for the saturation current is essential for the modeling of the CMOS inverter degradation. In this paper, we report that the saturation current degradation proceeds logarithmically in stress time. A physical analytical model, based on the pseudo-two-dimensional model, is derived for the first time to describe the saturation current degradation under various stress and measurement conditions. There are no empirical parameters in the model. Two physical parameters, the capture cross section and the density of states of electron traps, can be determined independently from the measured degradation characteristics. The simple expression is highly recommended for the modeling of the degradation of the digital CMOS circuits