FDSTDL: Low-power technique for FinFET domino circuits

Major issues in designing low-power high-speed VLSI circuits are propagation delay, power consumption, and noise tolerance. This paper describes fin field-effect transistor (FinFET) technology for the design of low-power VLSI circuits. FinFET uses two gates (front and back) in place of a single gate as in complementary metal-oxide–semiconductor (CMOS) technology for better control of the channel. A new technique foot driven stack transistor domino logic (FDSTDL) is proposed for designing domino logic circuits in order to reduce leakage power and propagation delay. In this paper, 2-, 4-, 8-, and 16-input domino OR gates are designed and simulated using existing and proposed techniques in CMOS and FinFET technology. Simulation is done on the 32 nm predictive technology model (PTM) node using HSPICE on a direct current (DC) supply voltage of 0.9 V. The proposed circuit is simulated in two modes of FinFET, short gate (SG) mode, and low power (LP) mode. The proposed technique shows maximum power reduction of 43.45% in SG mode in comparison with conditional stacked keeper domino logic (CSK-DL) technique and maximum delay reduction of 38.66% in LP mode in comparison with coarse-mesh finite difference (CMFD) technique at a frequency of 200 MHz.     

A 1-bit full adder using CNFET based dual chirality high speed domino logic

CNFET devices are preferred over CMOS devices for designing high-speed digital circuits. This paper introduces a new technique Dual Chirality High-speed Domino Logic (DCHSDL) for implementing low power and high-speed domino circuits in CNFET technology. Simulations are carried out for 32 nm Stanford CNFET model in HSPICE for 2, 4, 8 and 16 input domino OR gates at a clock frequency of 200 MHz on a DC supply voltage of 0.9 V. The proposed domino technique shows maximum power reduction of 82.55% and maximum delay reduction of 57.97% compared to CPVT technique in CNFET technology at a frequency of 200 MHz. The proposed circuit shows maximum power reduction of 97.90% compared to its analogous circuit in CMOS technology for a 2-input domino OR gate. The proposed technique shows maximum improvement of 1.05× to 1.63× in unity noise gain (UNG) compared to various existing techniques in CNFET technology at a frequency of 200 MHz. The 1-bit Full Adder designed using the proposed technique shows a power reduction of 16.91% and a delay reduction of 23.64% compared to standard FDL 1-bit Full Adder.     

Efficient multi‐threshold voltage techniques for minimum leakage current in nanoscale technology

The influence of multi‐threshold voltage technique on reducing the leakage power in CMOS circuits at transistor level based on Nanoscale SPICE parameters is investigated in this paper. Based on Artificial Intelligence search algorithms, three new algorithms are proposed to determine the exact threshold voltage for each transistor in order to minimize the leakage current at lowest value. These algorithms are: Slack Time Search Algorithm (STS), Leakage Power Search Algorithm (LPS), Leakage and Slack Time Search Algorithm (LSS). As a result, 70% of sub‐threshold leakage current is reduced without degrading the performance. Based on 22 nm predictive SPICE parameters proposed by BSIM4, simulation results verified the validity of the proposed algorithms. Copyright © 2010 John Wiley & Sons, Ltd.     

ONOFIC-based leakage reduction technique for FinFET domino circuits

A new technique ON/OFf logIC (ONOFIC) is proposed in this paper for designing domino logic circuits in fin-field effect transistor (FinFET) deep submicron technology. In this technique, a block named ONOFIC is inserted between pull-up network (PUN) and pull-down network (PDN) of domino circuits. The proposed technique is simulated in FinFET short gate (SG) and low power (LP) mode. The subthreshold current which plays a major role to determinate leakage power is very low in this technique. Two-, 4-, 8-, and 16-input OR gates are simulated with 32-nm node FinFET technology. In FinFET LP mode, the subthreshold leakage power of the proposed technique is reduced by 15% to 24.3% at 25°C and reduced by 8.71% to 23.4% at 110°C compared with standard domino circuits. The subthreshold leakage power of the proposed circuit is reduced by 19.2% to 57.3% at 25°C and reduced by 17.6% to 60.7% at 110°C compared with leakage control transistor (LECTOR)-based circuits. In FinFET SG mode, the subthreshold leakage power of the proposed technique is reduced by 7.69% to 17.7% at 25°C and reduced by 0 to 7.85% at 110°C compared with standard domino circuits. The subthreshold leakage power of the proposed circuit is reduced by 60.4% to 73.9% at 25°C and reduced by 45.1% to 65.5% at 110°C compared with LECTOR-based circuits. The proposed technique is also efficient to reduce subthreshold leakage power in deep nanometer technology nodes from 7 to 20 nm.     

Gate replacement with PMOS stacking for leakage reduction in VLSI circuits

Scaling down the circuits of complementary metal oxide semiconductor increases the leakage current. Input vector control is an extremely popular method for controlling leakage without using any technological modification. However, it is less effective for larger logic depth circuits. Our study proposes a Worst Leakage State (WLS) free‐node algorithm based on gate replacement technique, in which, when the logic gate of a given circuit goes into WLS, it is replaced by a suitable variant of the gate which in turn reduces the leakage current in an idle mode of the circuit at the same input vector. These variants minimize leakage under WLS conditions. For replacement purpose, four variants (V1–V4) of a two‐input NAND gate are proposed. This technique is applied on different circuits and some benchmark circuits such as ISCAS'85 (C17) and ITC'99 (B01, B02 and B06) (total of 10 circuits), according to the proposed algorithm with variants V1–V4. The average total power is reduced to 15.04%, 15.04%, 35.7% and 31.5%, and the leakage current is reduced to 42.96%, 42.96%, 84.25% and 84.52%, respectively, for variants V1–V4. The average delay is decreased by 16.03% in V1 and V2 variants and increased by 7.74% and 13.16% for variants V3 and V4, respectively, as compared with the results of conventional circuits at 45‐nm Berkeley Predictive Technology Model technology. Copyright © 2015 John Wiley & Sons, Ltd.     

A Wireless Capsule Endoscope System With Low-Power Controlling and Processing ASIC

This paper presents the design of a wireless capsule endoscope system. The proposed system is mainly composed of a CMOS image sensor, a RF transceiver and a low-power controlling and processing application specific integrated circuit (ASIC). Several design challenges involving system power reduction, system miniaturization and wireless wake-up method are resolved by employing optimized system architecture, integration of an area and power efficient image compression module, a power management unit (PMU) and a novel wireless wake-up subsystem with zero standby current in the ASIC design. The ASIC has been fabricated in 0.18-mum CMOS technology with a die area of 3.4 mm _* 3.3 mm. The digital baseband can work under a power supply down to 0.95 V with a power dissipation of 1.3 mW. The prototype capsule based on the ASIC and a data recorder has been developed. Test result shows that proposed system architecture with local image compression lead to an average of 45% energy reduction for transmitting an image frame.     

A flexible current‐mode classifier circuit and its applications

In this paper a new CMOS classifier circuit is presented, simulated, and compared with other recently introduced circuits. The proposed CMOS circuit operates in current‐mode and can classify several types of data. The architecture is designed using two threshold circuits and a subtraction circuit. Among many possible applications of the classifier circuit, template‐based pattern classification, namely template matching and character recognition with corruption, and in another direction its use as a quantizer are given. Using 0.35‐ µm AMS technology parameters, SPICE simulations as well as hard realization results for the classifier and application circuits are included; detailed Monte Carlo analyses to assess parameter mismatch effects are also performed. Copyright © 2010 John Wiley & Sons, Ltd.     

Low-power compact tunable quenching configuration for minimizing afterpulsing in single-photon avalanche diodes

This paper unveils two efficient free running (FR) quenching circuits with the aim of reducing quenching time (QT) to minimize avalanche charge. Likewise, one circuit is compactly designed with low power consumption, suitable for single-photon avalanche diode ( SPAD) with hold-off time below 10 ns. In second circuit, tunable hold-off and reset-time are provided within a wide range without decreasing QT, which are desirable in many applications. Proper operation and circuit uncertainty is assessed by Monte Carlo analysis in a standard 90-nm complementary metal-oxide semiconductor (CMOS) technology. In a bid to do a comparison between previously reported circuits and the proposed circuits, they are simulated with same SPAD model and parameters and results corroborate the proposed circuits guarantee active quenching time (AQT) of below 1 ns. Proposed circuits with current and area consumption of 0.74 μA, 32 μm² for 7-ns dead time and 16.2 μA, 93 μm² for 21-ns dead time are more efficient in terms of QT, area, and power consumption in comparison with other works.     

Gate and drain SEU sensitivity of sub-20-nm FinFET- and Junctionless FinFET-based 6T-SRAM circuits by 3D TCAD simulation

Scaling of metal–oxide–semiconductor field-effect transistors (MOSFETs) to below a few tens of nanometer has failed to make significant improvements. FinFETs were introduced to replace MOS devices in circuits, offering good performance improvement in the nanoscale regime. Memories occupy a major portion of chip area. Their reliability is a primary concern in harsh environments such as cosmic radiation. Also, in the nanoscale regime, reliability proves to be challenging. We present herein FinFET- and junctionless FinFET-based 6T-static random-access memories (SRAMs) for the 16-nm technology node. In the literature so far, either drain or gate strike has been considered. In this work, we studied irradiation in both the drain and the gate region. The FinFET-based 6T-SRAM showed higher hardness to single-event upset (SEU) radiation in both regions compared to junctionless FinFET-based 6T-SRAM.     

Noise‐immune dual‐rail dynamic circuit for wide fan‐in gates in asynchronous designs

Dual‐rail dynamic logic circuits can provide inverting and noninverting outputs, especially for asynchronous designs, to implement complicated gates at the cost of approximately doubling the area and power consumption. In this paper, a new dual‐rail dynamic circuit is proposed which has lower die area consumption and higher noise immunity without dramatic speed degradation for even wide fan‐in gates for asynchronous circuits. The main idea in the proposed circuit is that voltage due to the current of the pulldown network (PDN) is compared with the reference voltage to provide two complementary outputs. The reference voltage almost corresponds to the leakage current of the PDN with all transistors being off. The proposed circuit is compared with conventional dual‐rail circuits such as differential domino logic and differential cross‐coupled domino logic. Simulation results for 32‐bit‐wide OR gates designed using high‐performance 16‐nm predictive technology model demonstrate significant performance advantages such as 66% power reduction and at least 2.86× noise‐immunity improvement at the same delay compared to the differential domino circuits. © 2012 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A power‐performance tunable logic with adjustable threshold pseudo‐dynamic building blocks and CMOS compatibility

The continued downscaling of CMOS technology has resulted in very high performance devices, but power dissipation is a limiting factor on this way. Power and performance of a device are dependent on process, temperature, and workload variation that makes it impossible to find a single power optimal design. As a result, adaptive power and performance adjustment techniques emerged as attractive methods to improve the effective power efficiency of a device in modern design approaches. Focusing on this issue, in this paper, a novel logic family is proposed that enables tuning the transistor's effective threshold voltage after fabrication for higher speed or lower power. This method along with dynamic voltage scaling allows simultaneous optimization of static and dynamic power based on the workload requirement. The externally static topology of the proposed logic makes it possible to replace static circuits without requiring significant changes in the system. Experimental results obtained using 90‐nm CMOS standard technology show that the proposed logic improves the average power‐delay product by about 40% for the attempted benchmarks.     

Digitally programmable second generation current conveyor‐based FPAA

A novel fully differential digitally programmable current conveyor (DPCCII) is presented in this paper. The programmability of the proposed DPCCII is achieved using three‐bit MOS R‐2R ladder current division network. The DPCCII is used to realize a field programmable analog array (FPAA). The FPAA consists of seven configurable analog blocks arranged in a hexagonal form. The FPAA power consumption is 72.3 mW from 1 V voltage supply. A second‐order programmable universal filter is realized using the proposed FPAA as an application. All the circuits are realized and simulated using 90 nm IBM CMOS technology model under balanced supply voltage of ±0.5 V. Copyright © 2012 John Wiley & Sons, Ltd.     

适合于硬件高效执行的新型无乘法小波变换

消除小波变换中的乘法运算,能大大节省超大规模集成电路(very large-scale integration, VLSI)执行小波变换的时间,降低VLSI的复杂度。实现无乘法运算小波变换(multiplication-free wavelet transform, MFWT)的捷径是利用移位小波,即对应的小波滤波器是滤波系数为±1乘2的整数次幂的移位滤波器或移位滤波器序列。该文提出的实现MFWT的途径是：小波变换采用提升方式(lifting wavelet transform),小波滤波器在Lazy小波的基础上用提升法(liftingscheme)生成,每个提升滤波器都设计成简单的移位滤波器;这样,提升WT的每个预测(Predict)与改正(Update)步骤都只是计算当前数据与移位滤波器的相关系数的过程,可用移位加实现,避免了乘法运算。这种方案的关键是设计移位小波滤波器。该文详细研究了线性相位、非线性相位移位小波滤波器生成方法,内容包括如何根据对小波相频特性的要求选择提升滤波器形式,如何根据对小波幅频特性的要求确定提升滤波器参数等,并给出了一大批这样生成的移位小波滤波器的参数,以及部分这种小波的特性曲线。     

Crosstalk‐noise‐aware bus coding with low‐power ground‐gated repeaters

Crosstalk noise is one of the serious reliability concerns in nanoscale integrated circuits. Repeater insertion together with shielding wires is a typical method to suppress crosstalk noise associated with global data bus. A new crosstalk‐noise‐aware bus coding scheme with ground‐gated repeaters is proposed in this paper to minimize the routing overhead as well as power consumption of data bus systems. A subset of 4‐to‐6 crosstalk‐noise‐aware codes is selected to minimize the number of simultaneous data transitions. The routing overhead is reduced by 12.31% with the new bus coding scheme compared with the conventional data bus with shielding wires. Furthermore, the leakage power and worst‐case active power consumptions are reduced by 12.5% and 18.26%, respectively, with the new crosstalk‐noise‐aware data bus system as compared with the previously published bus coding system in an industrial 40‐nm CMOS technology.     

Dynamic mixed serial–parallel content addressable memory (DMSP CAM)

A novel dynamic mixed serial–parallel content addressable memory (DMSP CAM) is proposed to achieve both low‐power consumption and high performance. The replica circuits provide optimal timings to enable and disable the matchline charge transistor, which maximizes performance and minimizes leakage current, respectively. The DMSP CAM does not suffer from charge sharing in the serial stage and achieves high performance by removing the predischarge or precharge operation of the matchline before every comparison. To guarantee the robustness of the proposed scheme, a statistical design methodology is also applied. Using the 45‐nm technology, the DMSP CAM achieves both energy saving and performance improvement, and thus over 53% energy‐delay product reduction compared with the other serial–parallel mixed CAMs. Copyright © 2011 John Wiley & Sons, Ltd.     

Performance analysis and enhancement of 10-nm GAA CNTFET-based circuits in the presence of CNT-metal contact resistance

The gate-all-around (GAA) CNTFET is one of the most efficient types of CNTFETs which provides the conditions for scaling the technology to 10 nm and beyond, due to the extraordinary features of carbon nanotubes and the superior gate control through a high-k insulator over the CNT channel. However, the high CNT-metal contact resistance at the source/drain terminals can significantly degrade the device and circuit performance in CNTFET technology compared to what we have expected. In this study, first a comprehensive comparative assessment of performance and robustness of the gate-all-around CNTFET- and FinFET-based devices and circuits is performed. In the GAA CNTFET-based circuits the contact resistance can be defined as a series resistor at each contacted node of transistors. In addition, an effective circuit-level solution for improving the performance of GAA CNTFET-based circuits in the presence of contact resistance is proposed. In this approach, the contact lengths of the devices located on the critical path are increased to an effective value to reduce the contact resistance considerably and the other contact lengths remain minimum-sized. The results demonstrate that applying this solution significantly improves the speed, energy consumption and energy-delay product of GAA CNTFET-based circuits.     

ESD-Protection Design With Extra Low-Leakage-Current Diode String for RF Circuits in SiGe BiCMOS Process

Two low-leakage resistor-shunted diode strings are developed for use as power clamps in silicon-germanium (SiGe) BiCMOS technology. The resistors are used to bias the deep N-wells, significantly reducing the leakage current from the diode string. A methodology for selecting the values of the bias resistors is presented. For further reduction of the leakage current, an alternate design is presented: the resistor-shunted trigger bipolar power clamp. The power-clamp circuits presented herein may be used in cooperation with small double diodes at the I/O pins to achieve whole-chip electrostatic-discharge protection for RF ICs in SiGe processes     

Switched current circuit using fixed gate‐potential transistor and automatic tuning circuit

Clock feedthrough (CFT) error is one of the most important problems for switched current (SI) circuits. This paper proposes a SI circuit which can reduce CFT error drastically. The proposed circuit will theoretically reduce both signal‐dependent and independent errors by using CMOS switches under a fixed and appropriate bias. Although conventional circuits based on a similar idea need operational amplifiers or additional capacitors, our proposed circuit requires only MOSFETs. The proposed circuit can reduce CFT current with less power consumption and chip area compared to those of conventional circuits. An automatic tuning circuit, which controls the gate potential appropriately, is also proposed. Simulation results demonstrate the effectiveness of the proposed circuits. © 1999 Scripta Technica, Electr Eng Jpn, 126(3): 21–29, 1999     

Active‐terminated transmitter and receiver circuits for high‐speed low‐swing duobinary signaling

In this work, we propose transmitter and receiver circuits for high‐speed, low‐swing duobinary signaling over active‐terminated chip‐to‐chip interconnect. In active‐termination scheme port impedance of transmitter and receiver is matched with characteristic impedance of the interconnect. Elimination of the passive terminators helps in reducing the transmitted signal level without degrading the 0signal detectability of the receiver. High‐speed current‐mode receiver and transmitter circuits are designed, so that the input port impedance of the receiver and the output port impedance of the transmitter are matched with characteristic impedance of the link. These Tx–Rx pair is used to validate the proposed active‐termination scheme. We also propose a duobinary precoder architecture suitable for high‐speed operation and a low‐power broadband equalizer topology for compensating the lossy long interconnect. The duobinary transmitter and receiver circuits are implemented in 1.8 V, 0.18 µm Digital CMOS technology. The designed high‐speed duobinary Tx/Rx circuits work up to 8 Gb/s speed while transmitting the data over 29.5 in. FR4 PCB trace for a targeted bit error rate (BER) of 10^?15. The power consumed in the transmitter and receiver circuits is 42.9 mW at 8 Gb/s. Copyright © 2010 John Wiley & Sons, Ltd.     

Impact of self-heating effect on long-term reliability and performance degradation in CMOS circuits

As the technology feature size is reduced, the thermal management of high-performance very large scale integrations (VLSIs) becomes an important design issue. The self-heating effect and nonuniform power distribution in VLSIs lead to performance and long-term reliability degradation. In this paper, we analyze the self-heating effect in high-performance sub-0.18-/spl mu/m bulk and silicon-on-insulator (SOI) CMOS circuits using fast transient quasi-dc thermal simulations. The impact of the self-heating effect and technology scaling on the metallization lifetime and the gate oxide time-to-breakdown (TBD) reduction are also investigated. Based on simulation results, an optimized clock-driver design is proposed. The proposed layout reduces the hot-spot temperature by 15/spl deg/C and by 7/spl deg/C in 0.09-/spl mu/m SOI and bulk CMOS technologies, respectively.