A wide range delay locked loop for low power and low jitter applications

In this paper, a design of analog delay locked loop is introduced in which new techniques are applied to eventually increase operating frequency range and reduce jitter considerably. In this design, all blocks of a delay locked loop including a voltage controlled delay line, charge pump, and loop filter are accurately designed. A new delay cell is proposed with wide delay range, in which increase of delay range results in using fewer cells, and consequently the power consumption will decrease. Current mirror techniques and feedback in the proposed charge pump also cause higher current matching and better jitter performance. This delay locked loop, which is designed with TSMC 0.18‐μm CMOS technology, has a wide frequency range from 217 to 800 MHz. It consumes maximum 3.4‐mW and minimum 2.6‐mW power dissipation in source voltage of 1.8 V, which is suitable for low power applications. It also has an appropriate lock time that is at least equal to 3 clock cycles at 217 MHz and at most 25 clock cycles at 800 MHz. Jitter performance in this delay locked loop is improved significantly: RMS jitter is 0.65 ps at 800 MHz and 2.54 ps at 217 MHz. Moreover, its maximum peak‐to‐peak jitter is equal to 5.17 ps, and its minimum peak‐to‐peak jitter is equal to 1.39 ps at 217 and 800 MHz, respectively.     

Bang‐bang cycle‐slip detector improves jitter‐tolerance in SONET PLL/DLL CDR

The phase‐locked loop circuit (PLL) cycle‐slips (CS) phenomenon is a problem in two‐level baseband clock and data recovery (CDR) data‐synchronization. A singular example is that of a CDR synchronizer that uses a PLL in cascaded with delay‐lock‐loop (P/DLL) architecture. The CS issue is most evident when testing jitter‐tolerance to sine‐modulated jitter, particularly for sine‐modulated jitter‐frequencies near the PLL bandwidth. Reuse of a bang‐bang frequency‐detector, already on board of reference‐less CDRs, does CS detection and provides for suppression producing a clean demodulation. In the cascaded‐DLL of Rhee's P/DLL [1], this CS‐suppressed PLL‐clock assures proper DLL operation to broadband the jitter‐tolerance recommendation of the synchronous optical network (SONET). Copyright © 2016 John Wiley & Sons, Ltd.     

A small fully digital open‐loop clock and data recovery circuit for wired BANs

This paper proposes a new open‐loop and low complexity (small size) fast‐lock synchronization circuit for clock and data recovery in wearable systems. The system includes sensors embedded in textile and connected by conductive yarns. Synchronization is based on the open‐loop selection of the correct phase of the receiver clock synchronously with the incoming signal. The clock generator of the receiver is an autonomous oscillator set to operate at the same nominal frequency. The circuit lock time is at most one clock cycle, faster than all methods based on phase‐locked loops or delay‐locked loops. The circuit can be used for baseband communication independently of the signal coding method used in the physical layer, making it suitable for many applications. The fully digital circuit (including non‐return‐to‐zero inverted decoder) occupies 0.0022 in a 0.35 complementary metal‐oxide semiconductor (CMOS) process, a smaller implementation than many existing circuits, and supports a maximum system clock frequency of 70 for a 35‐data rate. Experimental results demonstrate that the proposed circuit robustly generates a synchronous clock for data recovery. The circuit is suitable for systems that tolerate some jitter but requires fast lock time, small size, and low energy consumption. Copyright © 2015 John Wiley & Sons, Ltd.     

A new fast‐lock,low‐jitter,and all‐digital frequency synthesizer for DVB‐T receivers

Lock time and convergence time are the most important challenges in delay‐locked loops (DLLs). In this paper we cover French very high frequency band with a novel all‐digital fast‐lock DLL‐based frequency synthesizer. Because this new architecture uses a digital signal processing unit instead of using phase frequency detector, charge pump, and loop filter in conventional DLL, therefore, it shows better jitter performance, lock time, and convergence speed than previous related works. Optimization methods are used to make input and output signals of the proposed DLL in phase. The proposed architecture is designed to cover all channels of French very high frequency band by choosing number of delay cells in signal path. Simulation has been done for 22–27 delay cells, and f_REF = 16 MHz, which can produce output frequency in range of 176–216 MHz. Locking time is approximately 0.3 µs, which is equal to five clock cycles of reference clock. All of the simulation results show superiority of the proposed structure. Copyright © 2013 John Wiley & Sons, Ltd.     

Delay‐locked loop based clock and data recovery with wide operating range and low jitter in a 65‐nm CMOS process

A delay‐locked loop (DLL) based clock and data recovery (CDR) circuit with a half‐rate clock is proposed. The CDR includes a coarse and a fine tuned block, in which the novel coarse and fine phase detectors form closed loops. It is designed in a 65‐nm complementary metal‐oxide semiconductor (CMOS) process using a 1.2‐V supply voltage. The simulation results show that it can cover a wide operating range from 500 Mbps to 8 Gbps and the corresponding peak‐to‐peak jitters are 1.63 ps and 0.96 ps, respectively. Copyright © 2016 John Wiley & Sons, Ltd.     

A 20-MHz bandwidth, 75-dB dynamic range,continuous-time delta-sigma modulator with reduced nonidealities

This letter presents a 4-bit continuous-time delta-sigma modulator (CT-DSM) fabricated using a 65-nm CMOS process. The circuit is designed for wide-bandwidth applications, such as those related to wireless communications. This CT-DSM has an oversampling ratio of 16 with a 640-MHz sampling frequency. To reduce the clock jitter sensitivity and excess loop delay effect, the first DAC pulse is a nonreturn-to-zero (NRZ)–type pulse, whereas the second DAC pulse is a return-to-zero (RZ)–type pulse; this is accomplished using a current-steering DAC. In order to reduce mismatch without using a data-weighted averaging circuit, the size and layout of the unit current source in the current-steering DAC are considered carefully. The CT-DSM achieves a signal-to-noise ratio (SNR) of 67.3 dB, a signal-to-noise and distortion ratio (SNDR) of 63.4 dB, and a dynamic range of 75 dB for a 20-MHz signal bandwidth.     

A high-resolution all-digital pulse-width modulator architecture with a tunable delay element in CMOS

A design for an all-digital high-resolution pulse-width modulator (HRPWM) architecture is presented in this work. The architecture is based on a novel digitally controlled delay element that combines two different approaches, achieving a variable time interval up to 54 ps, and adjustable against process, voltage, and temperature (PVT) variations. The proposed system uses several delay elements with a counter-based digital pulse-width modulator (DPWM) in a hybrid configuration, which allows to obtain duty cycles with 18-bit resolution without using a high-frequency internal clock and maintaining a low power dissipation. The HRPWM was implemented in a standard low-cost 130-nm CMOS technology, together with a memory used to store the duty cycles, and a serial communication module. Post layout simulation results show good linearity between the control word and the duty cycle in all the range. The chip can be fine tuned to improve its performance using the calibration capabilities of the architecture. The analysis includes a comparison with another state-of-art HRPWMs showing the advantages of the proposed approach.     

Positive-negative DC-DC converter using amorphous-InGaZnO TFTs

This paper presents two DC-DC converters capable of generating either positive or negative output DC voltage using amorphous-indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs). While one uses conventional diode-connected cross-coupled (design-1), the other employs a bootstrapped cross-coupled (design-2) DC-DC converter, which overcomes the limitations of design-1 but requires boosted clock pulses. Therefore, an on-chip clock booster is proposed to generate all the required signals without any external clock pulses. The performance of the proposed circuits (DC-DC converters and clock booster) has been demonstrated using in-house a-IGZO TFT models in the Cadence environment. The simulation results have shown that design-1 (design-2) generates negative or positive output DC voltage of 7.25 V (7.8 V) or 12.7 V (15.2 V), respectively, for a supply voltage of 8 V, using a single DC-DC converter. Therefore, the output DC voltage of design-2 is close to the theoretical value, and it ensures robust performance against different load currents when compared with design-1. Besides, design-2 has shown a maximum power efficiency of 90%, superior compared with design-1, where power efficiency is 60.7%. Therefore, this circuit finds potential applications in the next generation flexible displays.     

A 120–420 MHz delay‐locked loop with multi‐band voltage‐controlled delay unit

A low‐jitter and low‐power dissipation delay‐locked loop (DLL) is presented. A proposed multi‐band voltage control delay unit (MVCDU) is employed to extend the operation frequency of the DLL by controlling the delay cell within the MVCDU. The jitter of DLL is reduced due to MVCDU's low sensitivity. The delay cell in the MVCDU employs a differential configuration to further reduce the noise impact from the fluctuation in the supply and ground voltage. The operating frequency of the proposed DLL ranges from 120 to 420 MHz. The proposed design has been fabricated in a TSMC 0.18µm CMOS process. The measured RMS and peak‐to‐peak jitters are 4.86 and 34.55 ps, respectively, at an operating frequency of 300 MHz. The power dissipation is below 14.85 mW at an operating frequency of 420 MHz. Copyright © 2010 John Wiley & Sons, Ltd.     

A fast‐corrected all‐digital DCC with synchronous input clock

This paper presents a fast‐corrected all‐digital duty‐cycle corrector (DCC) with synchronous input clock. The proposed DCC has many features, including fast locking in 4 cycles, wide range correction, and synchronous 50% duty‐cycle clock with an input clock. The circuit can operate from 500 to 900 MHz and corrects a wide range of input duty cycle ranging from 25 to 75%. The duty‐cycle error of the output clock is between ?2.4 and 2.7%. The largest static phase error between the input and output clock is ?44 ps at 900 MHz. The RMS and peak‐to‐peak jitters are 1.9 and 14.7 ps at 900 MHz, respectively. The proposed DCC is implemented in a 0.18‐µm complementary metal oxide semiconductor process. The proposed DCC occupies an area of 0.05 mm² and dissipates 23 mW with 1.8‐V supply voltage at 900 MHz. Copyright © 2014 John Wiley & Sons, Ltd.     

高速低抖动时钟稳定电路设计

基于0.18 μm CMOS Mixed Signal工艺,设计实现了用于高速ADC的低抖动时钟稳定电路.在传统延迟锁相环结构(DLL)时钟电路研究基础上进行改进:设计基于RS锁存器的新型鉴相器,消除传统鉴相器相位误差积累效应;采用连续时间积分器取代电荷泵进行时钟占空比检测,减小由于电荷泵充放电电流不一致而导致的误差....     

铁电体触发开关的实验研究

利用铁电体作为脉冲开关的触发源,是当前脉冲功率技术发展的一个重要研究方向,为掌握铁电体作为触发极的工作性能,阐述了铁电体触发开关在真空条件下的工作原理和实验结果,给出了铁电体触发开关的设计思路及电极结构图并进行了真空条件下铁电体触发开关的实验研究,在开关间距0.3mm、真空压力度8cPa的条件下测得开关的抖动<800ps。实验结果表明:触发电压的高低对开关抖动的影响很大,随着触发电压的升高开关的抖动越来越小,但触发电压超过某一值时开关的抖动又会增加;开关阴阳极之间的间距对开关抖动基本无影响,对于不同的铁电体触发极,其触发电压的最佳值不同。     

Non‐idealities in linear CDR phase detectors

The effects of circuit non‐idealities in a “Hogge”‐type phase detector are examined. Using a behavioral model for each circuit block, it is shown that various circuit non‐idealities introduce static phase offset in the phase detector, reduce the monotonic range of its transfer characteristics and eventually degrade the capture range and jitter tolerance of the clock and data recovery (CDR) loop. Lower bounds on the bandwidths of the various blocks in the CDR are also established in order to avoid variations of the transfer characteristics. Copyright © 2011 John Wiley & Sons, Ltd.     

Compact CMOS active quenching/recharge circuit for SPAD arrays

Avalanche diodes operating in Geiger mode are able to detect single photon events. They can be employed to photon counting and time‐of‐flight estimation. In order to ensure proper operation of these devices, the avalanche current must be rapidly quenched, and, later on, the initial equilibrium must be restored. In this paper, we present an active quenching/recharge circuit specially designed to be integrated in the form of an array of single‐photon avalanche diode (SPAD) detectors. Active quenching and recharge provide benefits like an accurately controllable pulse width and afterpulsing reduction. In addition, this circuit yields one of the lowest reported area occupations and power consumptions. The quenching mechanism employed is based on a positive feedback loop that accelerates quenching right after sensing the avalanche current. We have employed a current starved inverter for the regulation of the hold‐off time, which is more compact than other reported controllable delay implementations. This circuit has been fabricated in a standard 0.18 µm complementary metal‐oxide‐semiconductor (CMOS) technology. The SPAD has a quasi‐circular shape of 12 µm diameter active area. The fill factor is about 11%. The measured time resolution of the detector is 187 ps. The photon‐detection efficiency (PDE) at 540 nm wavelength is about 5% at an excess voltage of 900 mV. The break‐down voltage is 10.3 V. A dark count rate of 19 kHz is measured at room temperature. Worst case post‐layout simulations show a 117 ps quenching and 280 ps restoring times. The dead time can be accurately tuned from 5 to 500 ns. The pulse‐width jitter is below 1.8 ns when dead time is set to 40 ns. Copyright © 2015 John Wiley & Sons, Ltd.     

A CMOS DCO design using delay programmable differential latches and a novel digital control scheme

A novel 16-bit CMOS digitally controlled oscillator (DCO) is described. This CMOS DCO design is based on a delay programmable differential latch and a novel digital control scheme which yields improved phase noise characteristics. Simulations of a 4-stage CMOS DCO using the 0.5 μm Agilent CMOS process parameters achieved a controllable frequency range of 750 MHz–1.6 GHz with a monotone tuning range of around 1 GHz. Monte Carlo simulations indicate that the time-period jitter due to random supply voltage fluctuations is under 250 ps for worst-case considerations. Also, phase noise was found to be in the range of −175 dBc at a frequency of 600 KHz from the carrier at 1.5 GHz (for digital control word of 1512 H) after numerous iterations of Monte Carlo simulations. FFT analysis indicate a total harmonic distortion (THD) of around − 57 dB for the DCO output signal. This CMOS design would thus provide considerable performance enhancement in digital PLL applications.     

基于TVS的控制器设计

介绍TVS -A和TVS-B两种真空触发开关,通过实验研究它们的延时特性.同时为了便于调节触发能量,以此为基础设计了一个有关TVS控制电路.实验数据表明延迟时间和抖动时间随触发能量的提高而降低.延迟时间和抖动时间随主间隙电压的升高而大幅度地降低.通过提高主气隙电压,提高了触发的可能性.同时证明由于在触发结构上的改进,TVS -B比TVS -A有更优越的延时特性.     

An all‐digital DLL with duty‐cycle correction using reusable TDC

This paper presents the design of an all‐digital delay‐locked loop (ADDLL) with duty‐cycle correction using reusable time‐to‐digital converter (TDC). The proposed ADDLL uses a reusable TDC for achieving a wide‐operating frequency range. In addition, it achieves the frequency doubling output clock easily by changing the quantization interval. It is implemented in a 0.18‐µm complementary metal‐oxide semiconductor technology. This circuit corrects the duty cycle and synchronizes the input and output clocks in 10 clock cycles. The output duty cycle is corrected to 50 ± 1.5% as the input duty cycle ranges from 25% to 75%. The acceptable input frequency range is from 300 to 900 MHz without frequency doubling. The acceptable input frequency range is from 150 to 450 MHz when using frequency doubling. It dissipates 6.2 mW from a 1.8‐V supply at 900 MHz. The peak‐to‐peak and RMS jitters at 900 MHz are 14 and 1.8 ps, respectively. Copyright © 2015 John Wiley & Sons, Ltd.     

Control of SF6 discharge gap switch by XeCl excimer laser

Experimental studies have been carried out on triggering characteristics of the SF₆ discharge gap switch by use of XeCl excimer laser (wavelength = 308 nm). First, laser irradiation characteristics are studied on a pure SF₆ in the pressure range of p = 160 ～ 3,800 torr. Using a lens of f (focal length) = 133 mm, the laser is irradiated into the gas, where the energy absorption is studied. If the laser is injected into the gas with the energy above a certain threshold for the breakdown, the rate of energy absorption is found to be ～ 17 percent of the incident energy at p > 760 torr. Injecting the laser into the SF₆-filled gap switch (gap length = 7 mm, p = 760 torr), we have studied the triggering characteristics. Excellent triggering characteristics were obtained; delay time for the discharge ～ 20 ns, and the jitter ～ 260 ps when the gap voltage is operated at 99 percent of the self-breakdown voltage. In addition, the triggering characteristics are studied by changing the focusing point axially. It is found that both the delay time and the jitter decrease when the focusing point tends to approach the high-voltage electrodes.     

Wideband third-order single-transistor all-pass filter

In this letter, a third-order wideband voltage-mode all-pass filter (APF) is proposed for application as a true time delay (TTD) cell. The advantages of designing a single-stage higher order filter over cascading several lower order stages are illustrated. The proposed APF circuit is based on a single metal-oxide-semiconductor (MOS) transistor and is canonical because it requires one resistor, one inductor, and two capacitors. To the best of the authors' knowledge, this is the first single-transistor third-order APF circuit to be reported in the literature. The operation of the proposed APF is validated through post-layout simulations in a 65-nm CMOS technology. The simulation results demonstrate a group delay of 59.4 ps across a 13.2-GHz bandwidth with a maximum delay-bandwidth product of 0.783, while consuming only 3.54mW from a 1-V supply voltage. Moreover, the designed circuit achieves an input-referred IP3 of 19.95 dBm and occupies an area of 161.5μm × 204.8μm.     

IO circuit design for 2.5D through‐silicon‐interposer interconnects

This paper presents four topologies of voltage‐mode un‐terminated IO cells in 28‐nm CMOS for single‐ended rail‐to‐rail signaling over a passive interposer die in 2.5D configuration for >1Gbps data rates. The presented design explores the existing IO design‐space from a 2.5D viewpoint, optimizing existing topologies from area, speed, power and protection perspectives, with a higher degree of configurability in the form of pre‐emphasis and slew‐rate control. The transmitter (TX) embeds pre‐emphasis to enhance high‐frequency components of the signal for longer low‐pass natured channels. The TX also implements slew‐rate control to minimize reflections on shorter channels because of impedance discontinuities and also to minimize simultaneous switching noise. Level‐shifting capability embedded in the receiver (RX) enables multi‐technology interfacing where different dies are signaling at their core voltages (range: 0.7 V–1.8 V) instead of following a particular signaling standard. The measurement results of the transceivers, over a interposer of length of 3.5 mm, demonstrate ±5% duty‐cycle distortion with 700 μW at 500 MHz/0.8‐V‐signaling on the channel with jitter of 20 ps, ±10% duty‐cycle distortion with 1.8 mW at 1Gbps/0.9‐V signaling with jitter of 20 ps, ±10% duty‐cycle distortion with 2 mW at 2Gbps/0.7‐V signaling for 1‐V receiver core voltage with a jitter of 10 ps. Copyright © 2016 John Wiley & Sons, Ltd.