A reversible ALU using HNG and Ferdkin gates in QCA nanotechnology

Quantum dot cellular automata (QCA) with the characteristics such as low energy dissipation and high density is a suitable alternative technology to CMOS technology. Arithmetic logic unit (ALU) is one of the most important critical components of a microprocessor, and it is the core component of central processing unit (CPU). In this work, a novel reversible ALU in QCA nanotechnology is proposed. The reversible ALU contains three Ferdkin gates and one HNG gate. The proposed structure needs one constant input and generates only one garbage output. The proposed circuit does not need any rotated cells and only uses one layer that improves the manufacturability of the design interestingly. This circuit can perform 20 operations such as AND, OR, XOR, XNOR, COPY, addition, and increment. Our design contains only 480 cells and 12 majority voters and requires 15 clock phases. The proposed structures are simulated using QCADesigner version 2.0.3. The reversible ALU, despite a 25% increase in operations, has a 28% improvement in cell numbers and a 6% improvement in delay.     

Innovative design methodologies in quantum‐dot cellular automata

Current transistor‐based IC fabrication technology faces many trivial issues such as those of excess power dissipation, expensive fabrication and short channel effects at very low device size [1]. Quantum‐dot cellular automata (QCA)‐based digital electronics on the other hand provide scope for further development in the future by shrinking the device size. Current QCA logic circuits are based on logic synthesis using Inverters and (three or five input) Majority Gates. In this paper, a new design methodology has been described that can be used to create circuits with even greater device substrate densities than what are currently achieved in existing QCA designs. Based on the proposed methodology, a new QCA inverter is proposed. It is further tested through simulations on QCA Designer. Through the simulations, it is subsequently proved to be much more reliable and robust than the presently used common QCA inverter(s). In the second section of this paper, simple QCA circuits such as ring oscillators using odd number of inverters in daisy chains are described and designed using the proposed inverter design. Copyright © 2013 John Wiley & Sons, Ltd.     

A comparative analysis and design of quantum‐dot cellular automata memory cell architecture

Quantum‐dot cellular automata (QCA) nanotechnology is considered as the best candidate for memory system owing to its dense packages and low power consumption. This paper analyzes the drawbacks of the previous QCA memory architectures and improves memory cell that exploits regular clock zone layout by employing two new clocking signals and a compact Read/Write circuit. The proposed layout is verified with the modified QCADesigner simulator and is analyzed by considering the noise effect. This design, occupying only a fraction of the area compared with the previous memory design, has superior performance. It is shown that the clock circuitry is very regular, helping manufacturability for physical implementation. Comparisons show that Read/Write latency of the proposed design is mitigated, the overall cell number, control cell and layout area are reduced (100%), and its performance against random charge noise is presented to be better. Copyright © 2010 John Wiley & Sons, Ltd.     

Robust QCA full-adders using an efficient fault-tolerant five-input majority gate

Quantum-dot cellular automata (QCA) is considered as a top candidate for nanoscale technologies with unique features such as very low occupancy and ultralow power consumption. Despite the potential benefits of QCA technology over CMOS technology, QCA circuits are highly prone to defects. Therefore, a demand has risen in designing fault-tolerant circuits. In this research, a novel fault-tolerant five-input majority gate is first suggested, and then it is evaluated by implementing a variety of faults such as cell omission, cell displacement, and extra-cell deposition. The evaluation results reveal that the proposed structure is 100%, 51.85%, and 18.8% fault-tolerant under extra-cell deposition, single-cell omission, and double-cell omission, respectively. Moreover, two single-layer and coplanar fault-tolerant QCA full-adders are offered using the suggested fault-tolerant structure. The stability of the presented single-layer full-adder has also been investigated under single and double cell omission defects. The evaluation outcomes show that the suggested fault-tolerant single-layer full-adder has a high stability in Sum and C_out outputs compared with other full-adders. In order to validate the functionality of the suggested fault-tolerant five-input majority gate, a number of physical investigations are given. The QCADesigner 2.0.3 software has been used to evaluate the simulation results.     

Design of novel efficient adder and subtractor for quantum‐dot cellular automata

Quantum‐dot cellular automata (QCA) is one of the new emerging technologies being investigated as an alternative to complementary metal oxide semiconductor technology. This paper proposes optimized one‐bit full adder (FA) for implementation in QCA. The fault effects at the proposed FA outputs due to the missing cell defects are analyzed, and the test vectors for detection of all faults are identified. Also, the efficient designs of one‐bit full subtractor (FS), one‐bit FA/FS and four‐bit carry flow adder (CFA) are presented using the proposed FA. These structures are designed and simulated using QCADesigner software. The proposed designs are compared with other previous works. In comparison with the best previous design, the proposed FA has 25% and 26% improvement in cells count and area, respectively, and it is faster. For the proposed FS, FA/FS and CFA, the obtained results confirm that these designs are more efficient in terms of area, cell count and delay. Therefore, the implementation of these designs may lead to the efficient use of the calculative unit in various applications, which may be used as a basic building block of a general purpose nanoprocessor. Copyright © 2014 John Wiley & Sons, Ltd.     

A design of cellular automata-based PUF and its implementation on FPGA

Since the number of networked devices increases continuously, ensuring the safety and reliability of these systems is growing at the same time. Today, a unique identity of a device can be obtained from physical unclonable functions (PUFs) and this identity as a trust anchor in higher-level security architectures. This article is exploring the cellular automaton (CA) paradigm to extract and magnify unique features of the underlying hardware to uniquely identify a device. The proposed PUF is based on a field-programmable gate arrays (FPGAs) implementation of CA with random memory (CARM) model. Implementation of the memory part of CARM is the challenge of the introduced PUF, and corresponding response is obtained from the introduced evolution figure metric. The uniqueness and reliability of the PUF hardware are compared with the results from the state-of-the-art PUF designs implemented on FPGA in the literature. The test results show that the introduced CA-based design is a promising and competitive candidate for PUF primitives.     

基于元胞自动机演化的环网拓扑着色新算法

针对在线监测系统中网络拓扑分析受嵌套环网结构限制的问题,提出了一种新颖的元胞自动机演化算法。在构建环网拓扑的基础上,基于元胞自动机、近邻粒和演化阶等定义,推导了网络拓扑的反演分析模型,给出了自动机算法实现流程。利用新算法完成了3个数值实验,实验结果表明新算法能满足工程应用需求,演化阶越大,推演代数越少,对于满阶自动机,只需推演1代便达稳定。     

Architecture for an external input into a molecular QCA circuit

A simple architecture for data input into a molecular quantum-dot cellular automata (QCA) circuit from an external CMOS circuit is proposed. A “T”-shaped interconnect, utilizing fixed-polarization cells to provide the desired polarization, is controlled via external electrodes connected to a standard CMOS input driver. The applied input signal is used to gate either the propagation of a fixed polarization, P=+1, or that of the complementary fixed polarization, P=−1, into the QCA circuit. The architecture utilizes the field-driven clocking scheme proposed in recent literature to achieve transduction between applied input voltage and a molecular configuration. The system is modelled using the coherence vector formalism with a three-state basis and simulated using the QCADesigner simulation tool.     

Design and simulation of modular 2n to 1 quantum‐dot cellular automata (QCA) multiplexers

In this paper a novel design of a quantum‐dot cellular automata (QCA) 2 to 1 multiplexer is presented. The QCA circuit is simulated and its operation is analyzed. A modular design and simulation methodology is developed, which can be used to design 2ⁿ to 1 QCA multiplexers using the 2 to 1 QCA multiplexer as a building block. The design methodology is formulated in order to increase the circuit stability. Copyright © 2009 John Wiley & Sons, Ltd.     

基于异质元胞自动机的互联电网连锁故障控制措施

为减少互联电网停电事故的规模及频率,提出了一种基于异质元胞自动机的互联电网连锁故障控制措施。首先,依据互联电网由多个不同特性的区域电网构成这一实际,并考虑区域电网间相互影响,建立了异质元胞自动机的互联电网连锁故障模型。其次,考虑各区域电网特性和不同故障阶段区域间的协调关系,提出了一种多区域多阶段线路潮流控制措施。最后,以IEEE118节点系统作为仿真案例,采用异质元胞自动机模型进行停电事故仿真,分别从幂律分布和故障时间序列两个方面验证了控制措施的有效性。并通过与其他控制措施比较,展示了其所具有的优越性。仿真结果表明:调度人员根据各区域电网运行情况,合理选择区域间的支援系数,可有效降低各区域电网大停电风险。     

基于元胞自动机的电网隐性故障传播模型关键线路识别方法

有效辨识电网中关键线路对优化电网结构、减少电网连锁故障具有重大意义。为此,考虑电网线路隐性故障,建立了基于元胞自动机理论的电网隐性故障模型,并在此基础上提出了一种综合考虑线路两端负荷量、线路故障频率和线路邻居数量的电网关键线路辨识方法。以IEEE39节点系统为算例,识别了该节点系统的关键线路,并通过与别的方法对比验证了该模型的合理性及其电网关键线路辨识方法的有效性。该模型和方法能为电网连锁故障模型和脆弱性评估提供新的参考。     

Novel quantum‐dot cellular automata implementation of flip‐flop and phase‐frequency detector based on nand‐nor‐inverter gates

CMOS technology faces fundamental challenges such as frequency and power consumption due to the impossibility of further reducing dimensions. For these reasons, researchers have been thinking replacement of this technology with other technologies such as quantum‐dot cellular automata (QCA) technology. Many studies have been done to design digital circuits using QCA technology. Phase‐frequency detector (PFD) is one of the main blocks in electrical and communication circuits. In this paper, a novel structure for PFDs in QCA technology is proposed. In the proposed design, the novel D flip‐flop (D‐FF) with reset ability is used. The D‐FF is designed by the proposed D latch which is based on nand‐nor‐inverter (NNI) and an inverter gate. This proposed D latch has 22 cells and 0.5 clock cycle latency and 0.018‐μm² area. The inverter gate of the D‐FF has output signal with high polarization level and lower area than previous inverters, and the NNI gate of the D‐FF is a universal gate. The proposed PFD has 141 cells, 0.17‐μm² occupied area, and two clock cycle latency that is smaller compared with PFD and is based on common inverter and majority gates.     

细胞自动机伪随机序列的线性复杂度分析

细胞自动机是一种时间、空间和状态均离散的动力学系统,是反馈移位寄存器这一有限状态机的推广.本文使用Berlekamp-Massey算法对细胞自动机产生的伪随机序列进行线性复杂度分析,在此基础上利用计算机模拟出了细胞自动机的线性复杂度分类图.最后,对细胞自动机产生的m序列的局部伪随机统计特性进行了分析和仿真,实验说明了基于细胞自动机的伪随机序列具有与移位寄存器相似的伪随机统计特性,且其电路具有更高的速度优势.     

可逆转轮单通道流动大涡模拟

为准确预测不可压复杂边界的湍流流动,本文应用高精度有限体积法对曲面边界湍流进行了大涡模拟。空间离散采用有限体四阶紧致格式,时间推进采用四阶Runge．Kutta法,压力一速度耦合应用四阶紧致格式的动量插值,亚格子应力模式采用动态Smagorinsky模式,复杂边界的处理则应用了浸没边界法,成功地实现了弯槽湍流、NACA0012标准翼型绕流流动和可逆式水泵水轮机转轮内单流道流动的大涡模拟计算,所得结果与已有结果或实验结果吻合良好,表明该方法对于湍流大涡模拟方法在流体机械工程领域中的应用和发展具有重要意义。     

The role of buffer layer in strontium bismuth tantalate based ferroelectric gate mos structures for non-volatile non destructive read out memory applications

Abstract

Metal Ferroelectric Insulator Semiconductor (MFIS) structure has been fabricated with strontium bismuth tantalate (SBT) as the ferroelectric thin film and zirconium oxide (ZrO₂) as the insulating buffer layer. SBT film was deposited by spin-on metal organic deposition (MOD) technique. ZrO₂ film was deposited by electron beam evaporation. The capacitance versus voltage characteristics(C-V) of the MFIS structure shows hysteresis and the direction of hysteresis corresponds to ferroelectric polarization. The C-V characteristics of MFIS structure shows memory window of 1.8 volts for a write/erase voltage of 9V at a sweep rate of 1 sec/1.8V. In order to understand the role of coercive voltage on the memory window in MFIS structures, C-V characteristics metal-ferroelectric-metal (MFM) structures with various SBT film thickness’ were also studied.     

可逆质子交换膜燃料电池研究进展

可逆质子交换膜燃料电池(RPEMFC)是一种在同一装置上实现水电解(充电)和燃料电池发电(放电)两种功能的储能电池。随着PEMFC技术的迅速发展,RPEMFC开始引起人们更多关注。介绍了它的工作原理,对电催化、膜电极(MEA)制作、电池性能以及应用等方面的研究进展进行评述。双效氧电极(氧还原和氧气析出)是RPEMFC的技术关键,但其电催化剂的双效高活性功能以及稳定性还没有得到很好解决。由于它的理论比能量高(可达3 600 Wh/kg),可靠性好,并且寿命长,因此RPEMFC在许多蓄电池的应用领域,特别是对质量有严格限制的场合(如航天飞机和太阳能飞机等),将得到广泛应用。     

A new TDOA algorithm based on Taylor series expansion in cellular networks

Time difference of arrival (TDOA) is the positioning technique with the most potential in cellular mobile telecommunication systems. The Taylor series expansion method has been widely used in solving nonlinear equations for its high accuracy and good robustness. However, the performance of the Taylor’s method depends highly on the initial estimation. Therefore, one new algorithm, hybrid optimizing algorithm (HOA) was proposed, which combines the Taylor series expansion method with the steepest decent method. The steepest decent method features fast convergence at the initial iteration and small computation complexity. HOA takes great advantage of both methods. Simulation results show that HOA achieves better performance on positioning accuracy and efficiency. __________ Translated from Journal on Communications, 2007, 28(6): 7–11 [译自: 通信学报]     

PWM并网变换器多内模并联结构重复控制策略

以“净化”电力系统中电力电子接口为背景,以实现并网电流快速、精确跟踪参考为目的,分析了多内模并联结构重复控制器(PSRC)及其控制系统。PSRC采用并联组成的一组nk+i次谐波内模(i=0, 1,…, n-1)实现对所有谐波的零误差跟踪或扰动抑制。相对于常规重复控制器(CRC),PSRC具有时间延迟小、收敛速度快、跟踪精度不下降、数字实现所需内存单元不增加的优点。将PSRC应用于恒压恒频(CVCF)脉宽调制(PWM)并网变流系统,包括三相/单相整流和三相/单相逆变并网系统中。实验结果验证了PSRC的有效性和优越性。     

One-sided 10T static-random access memory cell for energy-efficient and noise-immune internet of things applications

This paper presents a one-sided 10-transistors static-random access memory (SRAM) cell appropriate for the internet of things (IoT) applications in which energy-efficient SRAM cells are necessary to raise the battery lifetime. The bit-cell core of the proposed SRAM cell is composed of two inverters with different structures based on the gate-wrap-around (GWA) carbon nanotube (CNT)-gate-diffusion input (GDI) technique and only one-bit line to perform both read and write operations to minimize active power consumption. The proposed bit-cell uses a transmission gate network and write-assist schemes to significantly improve the write-ability and stack read-decoupling technique to enhance hold-/read-stability. Moreover, a memory mini-array has been implemented using the proposed cell along with all the principal circuitries. Extensive Monte Carlo (MC) simulations show that write/hold/read static noise margins (SNMs) are improved by about 1.252, 1.196, and 1.152 times, respectively. Also, the results of evaluating the write- and read-yield parameters for the proposed SRAM bit-cell are about 22% and 13% better than counterpart bit-cell designs, respectively. In addition, the bit error rate (BER) and energy dissipation parameters for the proposed memory cell are almost 61% and seven times higher than the studied SRAM bit-cell in the same simulation process. Finally, to evaluate the effectiveness of the proposed SRAM bit-cell in the real-world application, a memory array architecture with an online (or off-chip) adaptive power supply voltage based on a hardware algorithm for storing digital images at a minimum energy dissipation is proposed. Our simulation results emphasize that the proposed memory array can be a good candidate for energy-efficient and noise-immunity IoT platforms.