1 kHz步进低噪声YIG调谐微波频率综合器

低噪声微波频率综合器在现代电子系统和高性能测试系统中起着非常重要的作用,其实现方式通常以压控振荡器(VCO)和YIG调谐振荡器锁相频率合成为主。基于4~9 GHz YIG调谐振荡器,通过VCO合成小步进可变参考,使锁相环路在不降低鉴相频率的前提下,设计了完成高分辨率、低杂散的宽带低噪声YIG频率综合器。技术验证样品测试结果表明,在4~9 GHz工作带宽内频率步进为1 k Hz,相位噪声优于-95d Bc@10 k Hz,-115 d Bc@100 k Hz,其软硬件设计支持连续扫频和合成扫频功能,工作性能稳定可靠,可满足工程中本振和信号源应用需求。     

Low‐power quadrature generators for body area network applications

This paper presents different alternatives for the implementation of low‐power monolithic oscillators for wireless body area networks and describes the design of two quadrature generators operating in the 2.4‐GHz frequency range. Both implementations have been designed in a 90‐nm Complementary Metal‐Oxide Semiconductor (CMOS) technology and operate at 1 V of supply voltage. The first architecture uses a voltage‐controlled oscillator (VCO) running at twice the desired output frequency followed by a divider‐by‐2 circuit. It experimentally consumes 335 μW and achieves a phase noise of ?110.2 dBc/Hz at 1 MHz. The second architecture is a quadrature VCO that uses reinforced concrete phase shifters in the coupling path for phase noise improvement. Its power consumption is only 210 μW, and it obtains a phase noise of ?111.9 dBc/Hz at 1 MHz. Copyright © 2011 John Wiley & Sons, Ltd.     

Analysis and design of LC oscillators associated with frequency multipliers: a phase noise perspective

When a local oscillator signal generation system is based on an LC oscillator and a frequency multiplier, the question of determining the optimal multiplication factor is a key issue. In this paper, the problem is addressed in order to minimize the 1/f ² phase noise within a tuning range constraint. The analysis, with a practical graphical representation, reveals the oscillator phase noise dependence on the oscillating frequency in the transition from two different regimes, named the inductor‐limited quality factor and the capacitor‐limited quality factor. The results obtained enable the evaluation of the phase noise performance of systems based on a sub‐harmonic and super‐harmonic oscillators and how they compare with an oscillator in the fundamental mode. Crucial questions like the phase noise improvement that these systems can achieve are analytically answered. A design methodology is thus proposed and verified through measurements on a frequency source at 31 GHz, composed by a sub‐harmonic voltage‐controlled oscillator followed by an injection‐locked frequency tripler, dedicated to backhauling applications, designed on a BiCMOS process technology. The tuning range is 10%, and the phase noise at a 1‐MHz offset is −112 dBc/Hz. Copyright © 2017 John Wiley & Sons, Ltd.     

Design and analysis of differential ring voltage controlled oscillator for wide tuning range and low power applications

Voltage-controlled oscillator (VCO) is the most basic component required for all wireless and communication systems. In this article, a four-stage differential ring VCO with two control voltages for wide tuning range is proposed. This VCO uses the dual-delay loop technique for high operation frequency. Also, a low-V_T NMOS transistor is used in series with pull down network of the proposed VCO delay cell to achieve low frequencies. Prelayout simulation of the proposed VCO is performed in 65-nm TSMC CMOS technology in Cadence software under 1.2-V supply voltage. The tuning range of the proposed VCO varies from 1 MHz to 13.8 GHz and has been improved by 19.77% compared to other works. The power consumption of this low power VCO is between 29.3 μW to 1.715 mW. The phase noise of the proposed circuit is −82.3 dBc/Hz at 1 MHz offset frequency and −106.9 dBc/Hz at 10 MHz offset frequency from 5.161 GHz center frequency, while its area is 102.457 μm² . This design demonstrates other benefits in low power consumption and area compared with other ring oscillators.     

基于ADF4002的低相噪取样本振设计

本文设计并实现了一种微波锁相环中取样器的本振电路,取样本振以频率合成芯片ADF4002为鉴相器,反馈通道采用内插混频器的结构,避免了单环通过简单倍频产生的相位噪声恶化。详细阐述了取样本振电路的实现方案和工作原理,并使用仿真软件对环路滤波器进行设计。通过实验测试,输出频率为214．815MHz时锁相环的相位噪声为：-137dBc／Hz@10kHz、-140dBc／Hz@100kHz,最大输出频率间隔1MHz,满足了取样本振的低相位噪声和高频率分辨率的要求。     

基于DDS的C波段宽带小步进低相噪频率源的设计与实现

设计一款基于直接数字频率合成(DDS)驱动的C波段频率源,该频率源使用AD9912 DDS芯片产生低频参考,通过驱动锁相环产生C波段的频率输出。其中,DDS作为驱动可以保证频率综合器足够细小的分辨率,锁相环作为可变次数倍频器可完成对参考频率的频率倍增,从而在C波段范围下同时实现宽频带、小步进、低相位噪声与低杂散的指标要求。通过实验与测试,该频率源可以1k Hz为频率步进实现6.75~7.75GHz的频率输出范围,其相位噪声达到―95dBc/Hz@10kHz,杂散抑制度达到70dBc。即与典型的锁相环结构相比,在同样的频率步进与输出频率下,实现了宽频带,并获得了更好的杂散表现与相位噪声。     

Performance Enhancement of Tunable Bandpass Filters Using Selective Etched Ferroelectric Thin Films

The inclusion of voltage-tunable barium strontium titanate (BSTO) thin films into planar band pass filters offers tremendous potential to increase their versatility. The ability to tune the passband so as to correct for minor deviations in manufacturing tolerances, or to completely reconfigure the operating frequencies of a microwave communication system, are highly sought-after goals. However, use of ferroelectric films in these devices results in higher dielectric losses, which in turn increase the insertion loss and decrease the quality factors of the filters. This study explores the use of patterned ferroelectric layers to minimize dielectric losses without degrading tunability. Patterning the ferroelectric layers enables us to constrict the width of the ferroelectric layers between the coupled microstrip lines, and minimize losses due to ferroelectric layers. Coupled one-pole microstrip bandpass filters with fundamental resonaces at ～7.2 GHz and well-defined harmonic resonances at ～14.4 and ～21.6 GHz, were designed, simulated and tested. For one of the filters, experimental results verified that its center frequency was tunable by 528 MHz at a center frequency of 21.957 GHz, with insertion losses varying from 4.3 to 2.5 dB, at 0 and 3.5 V/ w m, respectively. These data demonstrate that the tuning-to-loss figure of merit of tunable microstrip filters can be greatly improved using patterned ferroelectric thin films as the tuning element, and tuning can be controlled by engineering the ferroelectric constriction in the coupled sections.     

Design of a CMOS 65-nm inductor-less VCO for ISM applications in the VHF band

This paper presents a design of a CMOS cross-coupled voltage-controlled oscillator (VCO) using active inductors (AIs) for wide-band applications and can also be applied to various wireless technologies standards. The compatibility of this design to different wireless standards highlights its potential to be implemented at the core of the communication front end in the Internet of Things (IoT). The proposed AI design employs a gyrator-C topology as the basic structure to generate an inductance. The VCO uses a cross-coupled oscillator structure with a pair of varactors to sweep the frequency. Two extra capacitors, between the AIs and the outputs of the VCO core tank, are employed to enhance the performance of the phase noise and make the VCO work similarly to a linear transconductance (LiT) oscillator. Both the AIs and the VCO are designed in the TSMC 65-nm CMOS technology, and the performance is analyzed using postsimulation results, as well as through measurements. The fundamental frequency spans from 140 to 463 MHz. Thus, the relative tuning range of this design is approximately 107%. The optimal phase noise of the design is around −97 dBc/Hz at 1-MHz offset. Furthermore, it achieves an excellent figure of merit (FOM) around −163 dBc/Hz with a direct current (DC) power consumption less than 3 mW. The proposed design shows an advantage in phase noise and power consumption in comparison with previous active inductor VCO and ring VCO designs, respectively. The final layout occupies only 0.4 × 0.62 mm² including the pads. The proposed AI-VCO shows a compact size, linear tuning, low power consumption, and good phase noise performance.     

Sinusoidal shaping of the ISF in LC oscillators

A new method to decrease the phase noise of the sinusoidal oscillators is proposed. The proposed method is based on using a dynamic transistor biasing in a typical oscillator topology. This method uses the oscillator impulse sensitivity function (ISF) shaping to reduce the sensitivity of the oscillator to the transistor noise and as a result reducing the oscillator phase noise. A 1.8 GHz, 1.8 V designed oscillator based on the proposed method shows a phase noise of ?130.3dBc/Hz at 1 MHz offset frequency, thereby showing about 6 dB phase noise decreasing in comparison with the typical constant bias topology. This result is obtained from the simulation based on 0.18u CMOS technology and on‐chip spiral inductor with a quality factor equal to 8. Copyright © 2007 John Wiley & Sons, Ltd.     

A CMOS DCO design using delay programmable differential latches and a novel digital control scheme

A novel 16-bit CMOS digitally controlled oscillator (DCO) is described. This CMOS DCO design is based on a delay programmable differential latch and a novel digital control scheme which yields improved phase noise characteristics. Simulations of a 4-stage CMOS DCO using the 0.5 μm Agilent CMOS process parameters achieved a controllable frequency range of 750 MHz–1.6 GHz with a monotone tuning range of around 1 GHz. Monte Carlo simulations indicate that the time-period jitter due to random supply voltage fluctuations is under 250 ps for worst-case considerations. Also, phase noise was found to be in the range of −175 dBc at a frequency of 600 KHz from the carrier at 1.5 GHz (for digital control word of 1512 H) after numerous iterations of Monte Carlo simulations. FFT analysis indicate a total harmonic distortion (THD) of around − 57 dB for the DCO output signal. This CMOS design would thus provide considerable performance enhancement in digital PLL applications.     

Increasing power efficiency in the design of a low power and low phase noise CMOS LC oscillator

This study developed a local oscillator (LO) with low phase noise and low power consumption. The proposed oscillator core comprises a pair of cross‐coupled transistors, which are fed by another pair of transistors that injects current at moments close to the peak of output voltage. The position of the current injection transistors, which are inserted in series with the cross‐coupled transistors, affects the waveform of current injected into an inductive–capacitive (LC) tank. Installing a capacitor on the source node of the cross‐coupled transistors increases the current injected into the LC tank and thereby augments the output voltage amplitude and power efficiency of the LO. The resonator phase shift and Q can be corrected by adjusting the source capacitance, which filters noise. These changes reduce the phase noise to ?123.4 dBc/Hz at a frequency offset of 1 MHz and improve oscillator performance with a figure of merit equal to ?193.5 dBc/Hz. To evaluate the LC tank, a 5 GHz LO was simulated at 1.8 V power supply and 2.5 mW power consumption. The simulation was conducted using a practical 0.18 complementary metal–oxide–semiconductor model manufactured by the Taiwan Semiconductor Manufacturing Company. The simulation results confirmed the analytical findings.     

Optimal design of third‐order microstrip bandpass filters by direct synthesis technique (DST)

To design microstrip filters is not easy for the sake of their distributed‐element effect. Undoubtedly, to understand their physical mechanism is very important to their design. In this paper, one effective approach to design some third‐order microstrip bandpass filters with each of 2 transmission zeros at each side of the passband is discussed. Lumped‐element equivalent circuits are used to represent these microstrip filters. Then, these lumped‐element equivalent circuits can be synthesized by direct synthesis technique we recently proposed, so that it is likely to calculate initial structural parameters of these microstrip filters and then facilitate their design. Verified by the measured results of the filter designed through the approach in this paper, the performance of the filters is close to ideal frequency responses. Furthermore, another third‐order microstrip bandpass filter is presented, in which open‐circuited stubs at input/output ports are introduced to suppress one specified harmonic to improve out‐of‐band attenuation.     

A low jitter sub-sampling phase-locked loop with sampling thermal noise cancellation technique

The traditional sub-sampling phase-locked loop faces the tradeoffs between phase noise and spur, in that low in-band phase noise requires large sampling capacitor size but at the sacrifice of spur performance. This paper presents a sub-sampling PLL aimed at minimizing in-band phase noise via sampling thermal noise cancellation technique. It enables the substantial reduction of in-band phase noise while reducing the sampling capacitor size. In addition, due to the reduction of the sampling capacitance, the reference spur performance of the PLL is improved, and the power consumption of the isolation buffer is reduced. Implemented in a 65 nm CMOS process, the in-band phase noise at 200 kHz offset is −133.4 dBc/Hz at 2.2 GHz and integrated jitter is 80 fs_rms. The reference spur is −67 dBc. It consumes 5.5 mA from 1.2 V supply and occupies 0.72 mm².     

A high output power and low phase noise GaN HEMT VCO with array of switchable inductors

This paper presents cross‐coupled voltage‐controlled oscillators (VCOs) involving array of switchable inductors (i.e., N  = 1 and N  = 2 switchable inductors) and implemented using gallium‐nitride high electron mobility transistors on Si substrate technology for worldwide interoperability for microwave access applications. Band selection and coarse frequency tuning were achieved using the array of switchable inductors, whereas fine tuning was controlled using varactors. Two bands were obtained using the one‐stage switchable inductor VCO operating in the ranges 3.41–3.57 GHz and 3.85–3.94 GHz. The VCO output power (P_out) was 21.8 dBm at 3.57 GHz from a 10‐V power supply. Four continuous bands were obtained using the two‐stage switchable inductors VCO operating in the range of 3.16–3.4, 3.25–3.64, 3.48–3.71 and 3.64–3.9 GHz, respectively. An additional band was generated by fine‐tuning the inductance through mutual coupling between the transmission line and one of the inductors. The proposed two‐stage switchable inductors VCO provided a 21% tuning range at frequencies ranging with a control voltage ranging from 12 to 20 V, a low phase noise of −123 dBc/Hz at a 1‐MHz offset from a 3.3‐GHz carrier and a P_out of 21 dBm at 3.5 GHz from a 10‐V power supply. Copyright © 2017 John Wiley & Sons, Ltd.     

Tunable Dual Band Filter with BST Capacitors

A tunable double band band-stop filter based on BST is presented. This configuration has a coplanar microstrip loaded with stepped impedance resonators. Ferroelectric BST parallel plate capacitors were loaded at the end of the stepped impedance resonators. When a DC voltage is applied to the BST capacitors, the change in capacitance shifts the resonance frequency of the stepped impedance transformers. The filters were designed with notch frequencies at 1.5 GHz and 3.5 GHz without loading them with BST capacitors. The filter circuits were simulated with Agilent ADS and were fabricated on FR-4 substrates. By loading the resonators with BST capacitors with no DC applied voltage, the first and second notch frequency shifts significantly. The first notch frequency can be tuned from 570 MHz to 781 MHz and the second notch frequency from 2.16 GHz to 2.55 GHz by applying the bias voltage of 5volts. The performance of the BST tuned filters were compared with filters tuned with p-n junction varactors.     

Experimental comparison of phase‐noise in cross‐coupled RC‐ and LC‐oscillators

Relaxation RC‐oscillators are notorious for their poor phase‐noise performance. However, there are reasons to expect a phase‐noise reduction in quadrature oscillators obtained by cross‐coupling two relaxation oscillators. We present measurements on 5 GHz oscillators, which show that in RC‐oscillators the coupling reduces both the phase‐noise and quadrature error, whereas in LC‐oscillators the coupling reduces the quadrature error, but increases the phase‐noise. A comparison using standard figures of merit indicates that quadrature RC‐oscillators may be a viable alternative to LC‐oscillators when area and cost are to be minimized. Copyright © 2009 John Wiley & Sons, Ltd.     

Tunable selective receiver front end with impedance transformation filtering

A highly selective impedance transformation filtering technique suitable for tunable selective RF receivers is presented in this paper. To achieve blocker rejection comparable with surface acoustic wave (SAW) filters, we use a two‐stage architecture based on a low‐noise transconductance amplifier (LNTA). The filter rejection is captured by a linear periodically varying model that includes band limitation by the LNTA output impedance and the related parasitic capacitances of the impedance transformation circuit. This model is also used to estimate ‘back folding’ by interferers placed at harmonic frequencies. Discussed is also the effect of thermal noise folding and phase noise on the circuit noise figure. As a proof of concept, a chip design of a tunable RF front end using 65 nm complementary metal‐oxide‐semiconductor (CMOS) technology is presented. In measurements, the circuit achieves blocker rejection competitive to SAW filters with noise figure 3.2–5.2 dB, out of band IIP3 > +17 dBm, and blocker P_1dB > +5 dBm over frequency range of 0.5–3 GHz. Copyright © 2015 John Wiley & Sons, Ltd.     

Simulation of Single-Stage Tunable Amplifier Using Ferroelectric Materials

The non-linear electric field dependence of ferroelectric thin films can be used to design frequency and phase agile components. Tunable components have traditionally been developed using mechanically tuned resonant structures, ferrite components, or semiconductor-based voltage controlled electronics, but they are limited by their frequency performance, high cost, high losses, and integration into larger systems. In contrast, the ferroelectric-based tunable microwave component can easily be integrated into conventional microstrip circuits and attributes such as small size, light weight, and low-loss make these components attractive for broadband and multi-frequency applications, many of these components are essential elements in the design of a microwave sensor and/or circuit. It has been reported that with a thin ferroelectric film placed between the top conductor layer and the dielectric material of a microstrip structure, and the proper DC bias scheme, tunable components above the Ku band can be fabricated. Components such as phase shifters, coupled line filters, and Lange couplers have been reported in the literature using this technique. In this work, simulated results from a full wave electromagnetic simulator are obtained to show the tunability of a single stage amplifier. Input and output matching networks are simulated on a ferroelectric thin film to control the frequency response of the amplifier.     

Towards minimum achievable phase noise of relaxation oscillators

A relaxation oscillator design is described, which has a phase noise rivaling ring oscillators, while also featuring linear frequency tuning. We show that the comparator in a relaxation‐oscillator loop can be prevented from contributing to 1/f² colored phase noise and degrading control linearity. The resulting oscillator is implemented in a power efficient way with a switched‐capacitor circuit. The design results from a thorough analysis of the fundamental phase noise contributions. Simple expressions modeling the theoretical phase noise performance limit are presented, as well as a design strategy to approach this limit. To verify theoretical predictions, a relaxation oscillator is implemented in a baseline 65 nm CMOS process, occupying 200 µm × 150 µm. Its frequency tuning range is 1–12 MHz, and its phase noise is L(100kHz) = ?109dBc/Hz at f_osc = 12MHz, while consuming 90 μW. A figure of merit of ?161dBc/Hz is achieved, which is only 4 dB from the theoretical limit. Copyright © 2012 John Wiley & Sons, Ltd.     

A wideband low‐spur 0.18‐µm CMOS phase‐locked loop with bandwidth calibration

This paper presents a 0.18‐µm complementary metal‐oxide‐semiconductor wideband phase‐locked loop with low reference spurs. The dual‐level charge‐pump current calibration technique is proposed to maintain a constant loop bandwidth for wide operation frequency range and achieve low reference spurs. The first level charge‐pump current calibration is seamlessly incorporated in the automatic frequency band hopping control and the mechanism also ensures enough negative transconductance for the voltage‐controlled oscillator to function throughout the whole frequency range. The charge‐pump current mismatch is calibrated by the second level charge‐pump current calibration combined with the pulse‐width scaling technique. The operation frequency range of the phase‐locked loop covers from 4.7 GHz to 6.1 GHz. The measured phase noise is?116 dBc/Hz at 1‐MHz offset and the reference spurs are below?66.8 dBc. Copyright © 2015 John Wiley & Sons, Ltd.