A low‐power small‐area 10‐bit analog‐to‐digital converter for neural recording applications

In vivo neural recording systems require low power and small area, which are the most important parameters in such systems. This paper reports a new architecture for reducing the power dissipation and area, in analog‐to‐digital converters (ADCs). A time‐based approach is used for the subtraction and amplification in conjunction with a current‐mode algorithm and cyclical stage, which the conversion reuses a single stage for three times, to perform analog‐to‐digital conversion. Based on introduced structure, a 10‐bit 100‐kSample/s time‐based cyclical ADC has been designed and simulated in a standard 90‐nm Complementary Metal Oxide Semiconductor (CMOS) process. Design of the system‐level architecture and the circuits was driven by stringent power constraints for small implantable devices. Simulation results show that the ADC achieves a peak signal‐to‐noise and distortion ratio (SNDR) of 59.6 dB, an effective number of bits (ENOB) of 9.6, a total harmonic distortion (THD) of ?64dB, and a peak integral nonlinearity (INL) of 0.55, related to the least significant bit (LSB). The ADC active area occupies 280µm × 250µm. The total power dissipation is 5µW per conversion stage and 20µW from an 1.2‐V supply for full‐scale conversion. Copyright © 2010 John Wiley & Sons, Ltd.     

An adaptive continuous-time incremental Σ∆ ADC for neural recording implants

In this paper, an analog-to-digital converter (ADC) with adaptive resolution is presented for wireless neural recording implants. The resolution of the ADC is changed according to the neural signal content, and for this purpose, a continuous-time (CT) incremental sigma-delta (IΣ∆) modulator is employed. The ADC digitizes the action potential (AP) and background noise (B-noise) with 8-bit and 3-bit resolutions, respectively. An automatic AP detector is used to separate the APs from the B-noise in order to select one of the two proportional resolutions. The power dissipation and output data rate of the ADC are reduced by using this technique. Analytical calculations and behavioral simulation results are provided to evaluate the performance of the proposed ADC. To further confirm its efficiency, the circuit-level implementation of the CT IΣ∆ ADC is presented in Taiwan Semiconductor Manufacturing Company (TSMC) 90-nm complementary metal-oxide semiconductor (CMOS) process. According to the simulation results, the proposed ADC achieves 8-bit or 3-bit resolution adaptively with 10 kHz bandwidth while the average power consumption is less than 1.89 μW from a single 1-V power supply.     

A 14b 150 MS/s 140 mW 2.0 mm2 0.13µm CMOS A/D converter for software‐defined radio systems

This work proposes a 14 b 150 MS/s CMOS A/D converters (ADC) for software‐defined radio systems requiring simultaneously high‐resolution, low‐power, and small chip area at high speed. The proposed calibration‐free ADC employs a wide‐band low‐noise input sample‐and‐hold amplifier (SHA) along with a four‐stage pipelined architecture optimizing scaling‐down factors for the sampling capacitance and the input trans‐conductance of amplifiers in each stage to minimize thermal noise effect and power consumption. A signal‐insensitive 3‐D fully symmetric layout achieves a 14 b level resolution by reducing a capacitor mismatch of three MDACs. The prototype ADC in a 0.13µm 1P8M CMOS technology demonstrates a measured differential nonlinearity (DNL) and integral nonlinearity within 0.81LSB and 2.83LSB at 14 b, respectively. The ADC shows a maximum signal‐to‐noise‐and‐distortion ratio of 64 and 61 dB and a maximum spurious‐free dynamic range of 71 and 70 dB at 120 and 150 MS/s, respectively. The ADC with an active die area of 2.0mm² consumes 140 mW at 150 MS/s and 1.2 V. Copyright © 2010 John Wiley & Sons, Ltd.     

500 MS/s 12位流水线ADC的设计研究

在超高速高精度模数转换器(ADC)设计中,低压运算放大器及其数字辅助校准算法至关重要。基于40 nm CMOS工艺、工作电压1.1 V,设计了一款500 MS/s、12位流水线ADC。系统采用前端无采保结构及低压级间运算放大器以降低系统功耗。本文提出了一种基于数字检测的算法校准级间增益和电容失配误差,使用较小的面积和功耗有效提高了ADC的整体性能。本数字校准方案将ADC的差分非线性(DNL)和积分非线性(INL)从2.4 LSB和5.9 LSB降低为1.7 LSB和0.8 LSB。对于74.83 MHz的正弦信号,校准技术分别实现了63.14 dB的信号-失真噪声比(SNDR)和75.14 dB的无杂散动态范围(SFDR),功耗为123 mW,满足设计指标,证明了带有数字校正的低压流水线ADC设计的有效性。     

基于STM32与AD7606的高精度和快速响应数字多功能表的设计

针对国内传统的变送器或电表普遍存在响应时间较长或精度不高的实际状况,介绍一种基于STM32与AD7606为核心的数字多功能表的设计方案。该方案采用模块化设计,包括信号采集、数据处理、显示、按键、通讯和变送输出等。信号采集部分采用16位高精度同步采样ADC,同时,电流线路采用有源补偿方式,确保了整个测量段的数据精度;变送输出采用16位高性能DAC转换器,能够以最高30MHz的时钟速率工作。系统以每周期256点为采样点数,同时在算法上采用了逐点处理的方法,使得数据精度高,实时性好。基于ARM内核32位MCU,系统能够独立完成所需主要数据的采集、计算、显示和存储等工作。     

电力监控器硬件电路设计

电力控制器以87C196CB单片机为控制核心,数字信号处理芯片ADSP-2185执行数据采集和处理功能.作为主控制器的单片机具有内置的CAN总线接口,使远程通信更容易实现.数据采集采用AD73360模/数转换器芯片,它是一个6通道16位同步模拟输入转换器,与DSP结合实现了对多路电压、电流信号的实时采集与数据处理.     

A 12‐bit 10‐MS/s SAR ADC with a binary‐window DAC switching scheme in 180‐nm CMOS

This paper presents an energy‐efficient 12‐bit successive approximation‐register A/D converter (ADC). The D/A converter (DAC) plays a crucial role in ADC linearity, which can be enhanced by using larger capacitor arrays. The binary‐window DAC switching scheme proposed in this paper effectively reduces DAC nonlinearity and switching errors to improve both the spurious‐free dynamic range and signal‐to‐noise‐and‐distortion ratio. The ADC prototype occupies an active area of 0.12 mm² in the 0.18‐μm CMOS process and consumes a total power of 0.6 mW from a 1.5‐V supply. The measured peak differential nonlinearity and integral nonlinearity are 0.57 and 0.73 least significant bit, respectively. The ADC achieves a 64.7‐dB signal‐to‐noise‐and‐distortion ratio and 83‐dB spurious‐free dynamic range at a sampling rate of 10 MS/s, corresponding to a peak figure‐of‐merit of 43 fJ/conversion‐step.     

流水线模数转换器设计

设计了一款14位、125MS/s流水线模数转换器(ADC)。通过前端采样/保持电路(SHA)消除对输入信号采样的孔径误差,采用4位结构的首级转换电路提高ADC线性性能,设计了带输入缓冲的栅压自举开关以缓解首级转换电路输入采样开关中自举电容对SHA的负载效应,流水线ADC级间通过逐级按比例缩减策略使功耗得到节省。该设计采用0.18μm 1P5MCMOS工艺,ADC版图面积2.3 mm×1.4 mm。Spectre后仿真结果显示,采样频率125 MHz、输入信号在接近Nyquist频率(61MHz)处时信号噪声畸变比(SNDR)和无杂散动态范围(SFDR)可分别达到75.7 dB和85.9 dB。在1.8V电源电压下,ADC核心部分功耗为263 mW。     

A multipurpose circuit to read out and digitize pixel signal for low-power CMOS imagers

A complementary metal oxide semiconductor (CMOS) image sensor with a resolution of 128 × 128 pixels is presented in this paper in which pixel signal readout, noise suppression, and comparing operations are performed by one circuit during two steps: reading and conversion. The main idea of this work is to combine three main operations of an image sensor in one circuit. This method helps to decrease power consumption, silicon area, total noise, and imaging time. The total power consumption of the imager is 11 mW with a 2.5-V power supply and 40-fps frame rate. The pixel layout size is 10 × 10 μm² with a fill-factor of 81%. The analog to digital converter (ADC) resolution is 10 bits, and the error resulted from the proposed circuit is about ±0.5 least significant bit (LSB). The proposed CMOS image sensor was designed based on Taiwan Semiconductor Manufacturing Company (TSMC) 0.18-μm CMOS technology and was simulated by CADENCE SPECTRE circuit simulator. This circuit can be proposed for a CMOS imager with highly accurate and efficient power consumption.     

基于DSP技术的高速ADC动态测试平台设计

频域动态测试法是基于数字信号处理技术的高速模数转换器动态参数测试法之一,该方法能快速准确评估高速ADC的性能。利用PC、DSP芯片和FIFO芯片,设计和搭建了一套操作简易的高速ADC动态测试平台,完成了硬件设计以及相关测试软件编程,实现了对高速ADC9480(8位)的频域动态测试。该方法结合了MATLAB和串口通信两者优势,可以方便快捷地对ADC动态性能进行测试。测试结果表明该动态测试平台可行且操作简便。     

An 11‐μ W, 9‐bit fully differential,cyclic/algorithmic ADC in 0.13 μm CMOS

This paper describes a fully differential, cyclic, analogue‐to‐digital converter (ADC). It utilizes a 4‐bit binary weighted capacitor array to obtain 9‐bit resolution. The ADC uses an operational amplifier to suppress supply voltage variations. The operational amplifier with the slew‐rate detection is used to increase the speed of the ADC. The ADC is fabricated in IBM 0.13 μm CMOS process and occupies 650 × 850μm² active area. At 10 kS/s sampling rate, the ADC consumes 11 μW. In order to test immunity of the ADC on the supply voltage variations, static and dynamic performance of the ADC is measured with triangular supply voltage (V _{D C}  = 1.5 V, V _{A C}  = 200mV _pp, f  = 1 kHz). The measured peak of differential nonlinearity and integral nonlinearity is  + 0.26/ − 0.67 and  + 0.65/ − 0.59, respectively. At 250 Hz, effective number of bit is 8.4 bits, S F D R  = 66.7 dB and S N D R  = 52.6 dB. Copyright © 2016 John Wiley & Sons, Ltd.     

一款基于18位ADC的高精度三相标准表的设计

针对国内高准确度三相标准电能表稀缺,而进口高准确度表价格又相对昂贵的这样一种状况,设计了一款基于18位ADC的高准确度标准电能表。另外,利用电流互感器的有源补偿技术,使电流采样的线性度和稳定度好;利用电源隔离技术,噪声干扰小,信号稳定;采用低温漂进口箔电阻进行信号取样,长期稳定性好;每个周波1 024点采样,且运用逐点处理方法进行电量计算,数据更新快,实时性好,测量准确度高。综合各方面先进技术和高品质器件,经试验表明,这款三相标准电能表的准确度等级能达到0.01%以内。     

A 0.5‐V 5.9‐fJ/conversion‐step SAR ADC in 0.18‐μm CMOS

In this paper, we present a 434‐nW 8‐bit successive approximation register analog‐to‐digital converter (SAR ADC). We mainly consider the optimization of power consumption. A modified split‐capacitor array involving a novel switching scheme is proposed, which reduces the switching power consumption to just 13.8 for the single‐ended scheme without any losses in performance. Based on the SMIC CMOS 0.1 μm EEPROM 2P4M process, the simulation results show that at 0.5 V supply voltage, 300 kS/s sample frequency, and 4.98 kHz input frequency, the ADC achieves an signal‐to‐noise‐plus‐distortion ratio (SNDR) of 49.58 dB and effective number of bits (ENOB) of 7.94, and consumes 434 nW, resulting in a figure of merit of 5.9 fJ/conversion step. © 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A 7.5‐μW 0.08‐mm2 single‐ended SC delta‐sigma ADC for acoustic sensor applications

This study presents an ultra‐low‐power, small‐size, 1‐bit, single‐ended, and switched‐capacitor (SC) delta‐sigma analog‐to‐digital converter (ADC) for wireless acoustic sensor nodes. This wireless sensor node has a delta‐sigma ADC that converts the sensed signal to a digital signal for convenient data processing and emphasizes the features of small size and low‐power consumption. The chip area of the delta‐sigma ADC is dominated by the capacitor; therefore, a novel common‐mode (CM) controlling technique with only transistors is proposed. This ADC achieves an extremely small size of 0.08 mm² in a 130‐nm CMOS process. The conventional operational transconductance amplifiers (OTAs) are replaced by inverters in the weak inversion region to achieve high power efficiency. At 4‐MHz sampling frequency and 0.7‐V power supply voltage, the delta‐sigma ADC achieves a 55.8‐dB signal‐to‐noise‐plus‐distortion ratio (SNDR) and a 298‐fJ/step figure‐of‐merit (FOM) in a signal bandwidth of 25 kHz, while consuming only 7.5 μW of power. Copyright © 2015 John Wiley & Sons, Ltd.     

Design considerations for low power time‐mode SAR ADC

This paper describes circuit design considerations for realization of low power dissipation successive approximation register (SAR) analog‐to‐digital converter (ADC) with a time‐mode comparator. A number of design issues related to time‐mode SAR ADC are discussed. Also, noise and offset models describing the impact of the noise and offset on the timing error of time‐domain comparator are presented. The results are verified by comparison to simulations. The design considerations mentioned in this paper are useful for the initial design and the improvements of time‐mode SAR ADC. Then, a number of practical design aspects are illustrated with discussion of an experimental 12‐bit SAR ADC that incorporates a highly dynamic voltage‐to‐time converter and a symmetrical input time‐to‐digital converter. Prototyped in a 0.18‐µm six‐metal one‐polysilicon Complementary Metal‐Oxide‐Semiconductor (CMOS) process, the ADC, at 12 bit, 500 kS/s, achieves a Nyquist signal‐to‐noise‐and‐distortion ratio of 53.24 dB (8.55 effective number of bits) and a spurious‐free dynamic range of 70.73 dB, while dissipating 27.17 μW from a 1.3‐V supply, giving a figure of merit of 145 fJ/conversion‐step. Copyright © 2013 John Wiley & Sons, Ltd.     

一种高精度流水线 ADC 系统设计与建模方法

针对传统模数转换器(analog to digital convertor,ADC)设计复杂度高、仿真迭代时间长的问题,提出了一种高精度 ADC系统设计与建模方法。该方法以10 bit 50 MHz 流水线 ADC为例,首先选取分离采样架构,进行电路的s 域变换理论分 析;其次对电路中各种非理想噪声的表达式进行精确推导,根据系统中的运放功耗指标进行参数优化;最后分别在 MATLAB 和 Cadence 软件中建立模型,进行100点蒙特卡洛仿真。仿真结果表明,在 TSMC180 nm工艺失配下,该流水线 ADC有效位 数达到9.70 bit, 无杂散动态范围维持在76 dB 附近,微分非线性在0.3 LSB以内,积分非线性在0.5 LSB以内,核心功耗在 8mW, 该分析方法在保证流水线 ADC 优异性能的同时,大幅提高了设计效率。     

A novel flash-like all-metal-oxide semiconductor analog-to-digital converter suitable for system on chips systems

The analog-to-digital converters (ADCs) play a very important role in electronic products, radar, communication systems and signal processing, to name such a few. In this paper, a novel all-metal-oxide semiconductor (MOS) flash-like analog-to-digital converter (FLADC) that consists of five stages is proposed. The design was performed using only MOS transistors, and the proposed ADC works in a way similar to the conventional flash ADC. According to the proposed ADC, there is no need for the comparators used in the conventional flash ADCs, thus resulting in a reduction in both the transistor count and the power consumption. The sound operation and the superiority of the proposed ADC compared to previous works is verified by simulation using the 0.13-μm complementary MOS (CMOS) technology with a power-supply voltage, V_DD, of 1.2 V. The simulation has been conducted on a 5-bit FLADC that is built by 276 MOS transistors only which is approximately 32% of the transistor count of the corresponding conventional flash ADC and has no resistors. According to the simulation results, the proposed 5-bit FLADC consumes 3.23 mW at sampling rate of 0.5 GS/s.     

A capacitance‐ratio quantification design for linearity test in differential top‐plate sampling sar ADCS

Successive approximation register (SAR) analog‐to‐digital converters (ADCs) are widely used due to their low power consumption and area cost. However, testing SAR ADCs on an embedded chip is costly. This paper proposes a capacitance‐ratio quantification design for the linearity test of differential top‐plate sampling SAR ADCs. First, the pattern generator controls the switches connected to the bottom plate of capacitors to create a voltage difference proportional to a certain capacitance ratio on the top plates to be quantified. Then, the proposed mechanism quantifies the capacitance ratio via the auxiliary transistors connected to the input pair of the comparator in the SAR ADC. The capacitance ratios are recorded to construct the differential nonlinearity (DNL) and integral nonlinearity (INL) using the derived construction principles, which simplifies the implementation of the output response analyzer. Thus, the test time and area cost can be reduced with these two proposed mechanisms. For characterizing the DNL, the error between the results obtained using the proposed method and those obtained using conventional linear ramp histogram method is from ?0.10 to 0.11 least significant bits (LSBs). For the INL, the estimation error is from ?0.19 to 0.11 LSBs. Moreover, a test time reduction of about 76% is achieved at the expense of an 18.54% area overhead for the capacitance‐ratio quantification mechanism. Copyright © 2014 John Wiley & Sons, Ltd.     

一种1Gsps ADC

介绍了一种1Gsps ADC,可以8位分辩率处理2．2GHz模拟输入。     

Flexible fingerprint sensor driver IC and bendable evaluation

The paper presents a flexible polyimide fingerprint sensor driver IC driven by a 0.18-μm CMOS technology and studies the sensor bendable performance. The finger valley and ridge are sensitive to environment noise; therefore, we propose low-ripple cross non-overlap charge pump that performs 7.2 V pumped output voltage with Δ30 mV ripple and 98.36% pump efficiency to increase the sensing level and propose mutual V_ref SAR ADC circuit with 6.6 V input swing range, 30 MS/s, ENOB of 10 bits, SNDR 74.1 dB, and bit error with INL [0.61, −0.7] and DNL [0.9, −0.62] to enhance the resolution. Through low-ripple charge pump and mutual V_ref SAR ADC circuitry implementation, it makes the sensing of fingerprint valley and ridge capacitance signal still distinguishable when the film is bent harshly by the substrate radius 10 mm and, in the meanwhile, meet the FBI PIV biometric fingerprint image quality, which is upmost tough standard in biometric fingerprint of identification product.