基于功率预测的光伏微逆变器低频电流纹波抑制策略

随着单块光伏电池输出功率越来越高,以反激电路为基础的传统光伏微逆变器(PM)难以达到高效率,因此以桥式电路为基础的PM越来越受到重视。文中提出一种较小容值的桥式PM及其基于功率预测的输入侧低频电流纹波抑制方法。该方法取消了传统的电流内环,而且保证变换器的输出功率能够在一个开关周期时间内实现快速跟踪。考虑到实际参数与检测值的误差,所提功率预测方法仍具有很好的稳定性与鲁棒性。通过建立系统的小信号模型,设计了电压外环的调节器参数,使得电压环具有较大的带宽。实验结果证明了所提PM性能优良。     

A high‐performance CMOS CCII

A CMOS second generation Current Conveyor (CCII) is presented which is based on a novel voltage follower with a symmetric two‐gain‐stage topology. Simulations on a 0.8 μm design employing a 3.3 V power supply show a 0.03 per cent low‐frequency voltage gain error, a THD better than ?70 dB for a 1 V_p?p 100 kHz input signal, and reduced offset. Copyright © 2001 John Wiley & Sons, Ltd.     

A duplex current‐reused CMOS LNA with complementary derivative superposition technique

A duplex current‐reused complementary metal–oxide–semiconductor low‐noise amplifier (LNA) is proposed for 2.5‐GHz application. The duplex current‐reused topology with equivalent three common‐source gain stages cascaded is utilized to fulfil the low‐power consumption and high gain simultaneously. The complementary derivative superposition linearization technique with bulk‐bias control is employed to improve the linearity performance with large‐signal swing and to extend the auxiliary transistors bias‐control range. The proposed LNA is fabricated in a 0.18‐um 1P5M complementary metal–oxide–semiconductor process and consumes a 3.13‐mA quiescent current from a 1.5 V voltage supply. The measurement results show that the proposed LNA achieves power gain of 28.1 dB, noise figure of 1.64 dB, input P1dB and IIP3 of −19.6 dBm and 3.2 dBm, respectively, while the input and output return loss is 19.2 dB and 18.4 dB. Copyright © 2016 John Wiley & Sons, Ltd.     

Realization of arbitrary current transfer functions based on commercially available CCII + s

In this paper, a new topology for realizing arbitrary n^th‐order current transfer function (TF), consisting of only plus‐type second‐generation current conveyors (CCII+s), is suggested. The proposed TF simulator employs only grounded capacitors and is free from the passive element matching requirements. The developed TF simulator can be constructed directly with commercially available active components such as AD844s. It has low‐input and high‐output impedances, a feature which makes it fully cascadable with other current‐mode topologies. Moreover, the proposed simulator can provide gain at its outputs. Simulation and experimental test results for various filter examples are included to confirm the claimed theory. Copyright © 2012 John Wiley & Sons, Ltd.     

High-gain,high-CMRR class AB operational transconductance amplifier based on the flipped voltage follower

A novel class AB operational transconductance amplifier (OTA) topology is proposed, based on a class AB flipped voltage follower. The OTA has class AB behavior, with current boosting both for the load and the compensation capacitors. It has a high gain of (g_mr₀)⁴ , obtained using a two-stage structure with cascoded stages, and is a two-stage Miller-compensated amplifier employing multipath to remove the positive zero. It has close to rail-to-rail output swing (limited by cascoding) and very low common-mode gain thanks to a replica technique (allowing the use of low-power common-mode feedback [CMFB] loops). Ninety-two decibels of gain and 176 dB of common-mode rejection ratio (CMRR) without CMFB are achieved using a 40-nm complementary metal-oxide semiconductor (CMOS) process. The OTA is used to design a low-power sample-and-hold amplifier (SHA) operating at 5 MSps, a typical application for CMOS OTAs, which has been chosen to verify the proposed circuit's performance and to show that the OTA is robust in Monte Carlo simulations under process variations and mismatches in an actual application.     

一种新型零电压转换高压直流变换器的分析

为克服电流型有源箝位推挽变压器的输入电感过大和变压器升压倍数过大的缺点,满足行波管电源高电压、小电流特别是小体积的要求,提出了一种新型的高压变换器拓扑——有源箝位推挽倍压变换器,它利用变压器及开关管的寄生参数实现开关管的零压开通,同时采用倍压整流技术解决变压器升压倍数高、体积大、制作困难等问题。在详细推导了该变换器的稳态工作原理后,给出了开关管实现软开关的条件等重要结论。用PSPICE软件仿真试验的结果表明,该变换器适用于要求低电压输入、高电压输出、高效率的开关电源。     

Low-loss 7-bit S-band CMOS passive phase shifter with digital control

This paper presents the design and implementation of a 7-bit S-band digital passive phase shifter using Complementary Metal-Oxide-Semiconductor (CMOS) 65-nm technology in 2.6- to 3.2-GHz frequency band. New switched delay network topology has been used for 5.625° and 2.8°, and modified switched filter topology has been used for implementation of other phase bits to achieve 7-bit performance with low insertion loss and better isolation. The measured results of the fabricated chip show 7-bit performance with an average insertion loss of 11 dB, average root mean square (RMS) phase error of less than 2.0°, average RMS amplitude error of less than 0.6 dB, input matching (S₁₁) better than −7.5 dB, and output matching (S₂₂) better than −14.5 dB across the target frequency band at 50Ω input/output impedance.     

Inverted-load network for high-power Doherty amplifier

In this article, a high-power, high-efficiency inverted Doherty power amplifier (PA), having a more compact load network than that of the conventional Doherty amplifier, was designed and implemented for wide-band code-division multiple access (WCDMA) base-station applications. Its configuration and working principle are compared with the conventional Doherty amplifier. For experimental verification, we implemented an inverted Doherty amplifier, using a 190 W peak-envelope-power (PEP) laterally diffused metal-oxide-semiconductor (LDMOS) field-effect transistors (FETs). Using a four-carrier down-link WCDMA signal, we achieved a high power-added efficiency (PAE) of 32% and an average output power level as high as 46.3 dBm at a given adjacent channel leakage ratio (ACLR) level of -30 dBc. This is a 9.5% improvement in efficiency and 1 dB improvement in output power under the same ACLR conditions from those of the balanced class-AB operation using the same devices.     

A proposal for high‐performance CCII‐based analogue CMOS design

A novel fully differential CMOS second‐generation current conveyor (CCII) topology is presented. It can be considered as a universal fully differential programmable active element. The circuit operates in moderate inversion region, and features high linearity over a wide input range. Current gain between terminals X and Z can be continuously tuned in a wide range. These features are essential to extend the utilization of CCII‐based circuits to high‐performance VLSI applications. Analogue design based on this new cell is illustrated by various examples. The proposed CCII has been fabricated in a 0.5‐µm CMOS technology and its main performance characteristics have been measured. They are in good agreement with theory and demonstrate that operation in moderate inversion can lead to distortion levels much lower than those achieved in strong inversion. Experimental results for a Tow–Thomas biquadratic filter fabricated on the same chip are also presented, showing continuous frequency tuning in more than a decade. Copyright © 2005 John Wiley & Sons, Ltd.     

A CCII‐based non‐inverting Schmitt trigger and its application as astable multivibrator for capacitive sensor interfacing

This paper presents a novel second‐generation current conveyor (CCII)‐based non‐inverting Schmitt trigger topology. By means of the use of only three resistances, it is possible to set easily the threshold values or, in addition, the trigger can be set also to work as a zero‐voltage comparator. The theoretical working principle has been confirmed through PSpice simulations implementing an integrated CCII, designed in a low‐cost standard complementary metal–oxide–semiconductor technology (Austria Micro Systems (AMS) 0.35 µm) with low‐voltage low‐power characteristics, and then by experimental tests on the fabricated printed circuit board prototype through the use of the commercial component AD844 (Analog Devices) as CCII. As its main application example, the presented trigger has been employed to implement an astable multivibrator proposed here as a capacitive sensor interface capable to accurately detect about five decades of capacitive variations in the range of [100 pF–5.5 μF] with a maximum relative error lower than ±10%. Copyright © 2016 John Wiley & Sons, Ltd.     

Research on Low Sampling Rate Digital Pre-distortion Technology Based on Improved Chebyshev Polynomial

This paper presents a low sampling rate digital pre-distortion technique based on an improved Chebyshev polynomial for the non-linear distortion problem of amplifiers in 5G broadband communication systems. An improved Chebyshev polynomial is used to construct the behavioural model of the broadband amplifier, and an undersampling technique is used to sample the output signal of the amplifier, reduce the sampling rate, and extract the pre-distortion parameters from the sampled signal through an indirect learning structure to finally correct the non-linearity of the amplifier system. This technique is able to improve the linearity and efficiency of the power amplifier and provides better flexibility. Experimental results show that by constructing the behav-ioural model of the amplifier using memory polynomials (MP), generalised polynomials (GMP) and modified Chebyshev polynomials respectively, the adjacent channel power ratio of the obtained system can be improved by more than 13.87dB, 17.6dB and 19.98dB respectively compared to the output signal of the amplifier without digital pre-distortion. The Chebyshev polynomial improves the neighbourhood channel power ratio by 6.11dB and 2.38dB compared to the memory polynomial and generalised polynomial respectively, while the normalised mean square error is effectively improved and enhanced. This shows that the improved Chebyshev pre-distortion can guarantee the performance of the system and improve the non-linearity better.     

Sixth-order differential Sallen-and-Key switched capacitor LPF using a-IGZO TFTs

This paper presents sixth-order fully differential active low pass RC and switched-capacitor (SC) filters using N-type IGZO thin-film transistors for flexible wearable continuous health monitoring systems. As a first step, a low-gain amplifier using a diode-connected load and a fully differential amplifier is designed with positive feedback based on capacitor bootstrapping. These amplifiers present a gain around 5.03 and 40 dB, respectively, whereas their respective GBW product are around 450 and 200 kHz. Then these amplifiers are employed to realize biquads, with which a sixth-order Sallen-Key low-pass RC and SC filters are implemented. The SC filter realized with low-gain DDA has shown a simulated THD of −30.9 dB, SFDR of 30.1 dB, and a power consumption of 456 μW. On the other hand, the SC filter presents a THD of −31.4 dB, SFDR of 32.2 dB, and a power consumption of 573 μW with high-gain differential difference amplifier (DDA) when a power supply of 10 V is used. Circuit simulations have been carried out in Cadence Virtuoso using in-house IGZO TFT models.     

A 1.9‐GHz silicon‐on‐insulator CMOS stacked‐FET power amplifier with uniformly distributed voltage stresses

A 1.9‐GHz single‐stage differential stacked‐FET power amplifier with uniformly distributed voltage stresses was implemented using 0.32‐μm 2.8‐V thick‐oxide MOSFETs in a 0.18‐μm silicon‐on‐insulator CMOS process. The input cross‐coupled stacked‐FET topology was proposed to evenly distribute the voltage stresses among the stacked transistors, alleviating the breakdown and reliability issues of the stacked‐FET power amplifier in sub‐micrometer CMOS technology. With a 4‐V supply voltage, the proposed power amplifier with an integrated output coupled‐resonator balun showed a small‐signal gain of 17 dB, a saturated output power of 26.1 dBm, and a maximum power‐added efficiency of 41.5% at the operating frequency. Copyright © 2017 John Wiley & Sons, Ltd.     

High‐efficiency grid‐connected inverter topology for low‐power photovoltaic applications

For low‐power applications, such as household photovoltaic panels, the efficiency and reliability of the distributed generation system is an important issue. A high‐efficiency inverter topology derived from the normal full‐bridge circuit is proposed for grid‐connected photovoltaic applications. In the proposed topology, a couple of diodes are added in parallel with the grid‐frequency switches as freewheeling diodes working during the positive and negative half‐cycles of the utility voltage, respectively, thus preventing the output current from flowing through the body diodes of switches. Because of its natural configuration, simple operation, and three‐level function, the proposed topology features a high level of efficiency and reliability over a wide voltage range, and allows the best cost–effective ratio. These characteristics are compared with those of other existing advanced topologies, followed by a theoretical analysis on the output filter and the implemented circuit of modulation scheme. Experimental results from a 3 kW hardware prototype verify the feasibility of the proposed solution. © 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

An improved full-bridge zero-voltage switching PWM converter usinga two-inductor rectifier

An improved full-bridge ZVS PWM power convertor using a two-inductor rectifier DC/DC power converter is presented in this paper. For this improved topology, the main devices are switched under zero-voltage (ZVS) conditions using the energy stored in the secondary filter inductors. In addition, it utilizes the low leakage inductance of a coaxial winding transformer to reset the currents in the rectifier diodes and eliminate the secondary voltage spike. The two-inductor rectifier has only one diode conduction drop in addition to frequency doubling in the output capacitor. The secondary filter size in the proposed topology is rather small. The advantages of the new topology include a wide load range with ZVS, no lost duty cycle due to diode recovery, no secondary voltage spikes, in addition to high power density and high efficiency     

并联有源电力滤波器交流侧输出滤波器设计

针对输出滤波器存在的放大网侧电流畸变率、阻尼电阻发热严重的问题,提出一种工程化有源电力滤波器交流侧输出滤波器参数设计方法.采用二阶高通滤波器作为有源电力滤波器输出滤波器拓扑,在综合考虑输出滤波器的开关纹波滤波效果与电流畸变率、电容无功容量、电阻功耗之间关系的基础上,结合理论分析、仿真、实验研究,设计总结了并联有源电力滤波器输出滤波器的参数选择方法.采用该方法为50kVA并联有源电力滤波器设计了一套输出滤波器.实验结果表明:加装输出滤波器后,电流纹波抑制到滤波前的1/4以下,网侧电流畸变率增大约1个点,滤波电阻上90%以上的工频电流被旁路,电阻发热得到有效控制,实验结果验证了该输出滤波器设计方法的有效性.     

A novel single‐stage AC–DC converter with quasi‐resonant zero‐voltage‐switching for high power factor and high efficient applications

A new single‐stage‐isolated ac–dc converter that can guarantee both high efficiency and high power factor is proposed. It is based on a new dc–dc topology that has prominent conversion ratio similar to that of boost topology so that it is adequate to deal with the universal ac input. In addition, since it utilizes the transformer more than others based on the general flyback topology, the size of whole power system can be reduced due to the reduced transformer. Moreover, the voltage stresses on the secondary rectifiers can be clamped to the output voltage by adopting the capacitive output filter and clamp diode, and the turn‐off loss in the main switch can be reduced by utilizing the resonance. Furthermore, since this converter operates at the boundary conduction mode, the line input current can be shaped as the waveform of a line voltage automatically and the quasi‐resonant zero‐voltage switching can be obtained. Consequently, it features higher efficiency, lower voltage stress, and smaller sized transformer than other topologies. A 100 W prototype has been built and tested as the validation of the proposed topology. Copyright © 2010 John Wiley & Sons, Ltd.     

Multiple output differential OTA with linearizing bulk‐driven active‐error feedback loop for continuous‐time filter applications

A CMOS circuit realization of a highly linear multiple‐output differential operational transconductance amplifier (OTA) has been proposed. The presented approach exploits a differential pair as an input stage with both the gate and the bulk terminals as signal ports. For the proposed OTA, improved linearity is obtained by means of the active‐error feedback loop operating at the bulk terminals of the input stage. SPICE simulations of the OTA show that, for 0.35 µm AMS process, total harmonic distortion at 1.36Vpp is less than 1% with dynamic range equal to 60.1 dB at power consumption of 276 μW from 3.3 V supply. As an example, both single output and dual differential OTAs are used to design third‐order elliptic low‐pass filters. The cut‐off frequency of the filters is 1 MHz. The power consumption of the OTA‐C filter utilizing the dual output differential OTA is reduced to 1.24 mW in comparison to 2.2 mW consumed by the single output differential OTA‐C filter counterpart. Copyright © 2014 John Wiley & Sons, Ltd.     

A 1.2 V 83 dB DR single‐ended input SC ΔΣ modulator including a large‐swing analog buffer for portable ECG applications

This study proposes a subsystem consisting of an analog buffer and a single‐ended input to a fully differential ΔΣ modulator to obtain low‐power consumption for portable electrocardiogram applications. With the proposed subsystem, the need for an inverting amplifier is avoided, and low‐power consumption is achieved. The ΔΣ modulator with a second order, 1 bit, and cascade of integrators feedforward structure consumes a low power, in which an inverting and a non‐inverting path implement a single‐ended input to fully‐differential signals. A double sampling technique is proposed for a digital‐to‐analog converter feedback circuit to reduce the effect of the reference voltage, reduce the amplifier requirements, and obtain low‐power consumption. Input‐bias and output‐bias transistors working in the weak‐inversion region are implemented to obtain an extremely large swing for the analog buffer. At a supply voltage of 1.2 V, signal bandwidth of 250 Hz, and sampling frequency of 128 kHz, the measurement results show that the modulator with a buffer achieves a 77 dB peak signal‐to‐noise‐distortion ratio, an effective‐number‐of‐bits of 12.5 bits, an 83 dB dynamic range, and a figure‐of‐merit of 156 dB. The total chip size is approximately 0.28 mm² with a standard 0.13 µm Complementary Metal‐Oxide‐Silicon (CMOS) process. Copyright © 2016 John Wiley & Sons, Ltd.