化学机械抛光对铜互连器件的影响及失效分析

探讨了Cu化学机械抛光(CMP)工艺引起Cu互连器件失效的原因以及对可靠性的影响,对Cu CMP工艺缺陷导致器件失效的案例进行分析.由于CMP的技术特点,不可避免地会产生一些工艺缺陷和工艺误差,从而引起器件失效.必须根据标准要求,出厂或封装前对圆片进行芯片功能参数测试和严格的镜检,以便在封装前剔除存在潜在工艺缺陷的芯片,达到既定可靠性要求.     

圆片级封装用玻璃通孔晶片的减薄工艺北大核心

对圆片级封装用玻璃通孔（TGV）晶片的减薄加工工艺进行了研究并最终确定出工艺路线。该减薄加工工艺主要包括机械研磨及化学机械抛光（CMP）过程。通过机械研磨,玻璃通孔晶片的残余玻璃层及硅层得到有效去除,整个晶片的平整度显著提高,用平面度测量仪测试该晶片研磨后的翘曲度与总厚度变化（TTV）值分别为7.149μm与3.706μm。CMP过程使得TGV晶片的表面粗糙度大幅度降低,经白光干涉仪测试抛光后TGV晶片的表面粗糙度为4.275 nm。通过该减薄工艺加工的TGV晶片能够较好满足圆片级封装时的气密性要求。     

ULSI电路层间SiO_2介质CMP工艺与抛光液

阐明了化学机械抛光(CMP)工艺在集成电路制造中所发挥的关键作用,介绍了作为IC多层布线层间介质SiO2的化学机械抛光机理及其抛光液在化学机械抛光中扮演的重要角色,着重分析了影响SiO2介质化学机械抛光质量的主要因素并在此基础上提出CMP工艺的优化工艺条件以及今后SiO2介质CMP研究重点。     

化学机械抛光压力控制技术研究

概述了化学机械抛光技术的发展现状,讨论分析了主要工艺参数对抛光机理的影响。重点论述了化学机械抛光工艺中不同压力控制方法及其技术特点,提出了一种新的压力控制方案,并通过实验验证了该控制技术的先进性。     

CMOS工艺中钨的化学机械抛光技术

介绍了深亚微米CMOS集成电路中研制的关键技术———钨化学机械抛光,比较了化学机械抛光技术与传统反应离子回刻法在金属层与层之间的垂直连接中的优缺点,并指出了钨化学机械抛光工艺中尚存的一些问题,最后对该工艺进行了总结与展望。     

铜化学机械抛光工艺中碟形缺陷的优化

铜化学机械抛光是近些年发展最快的一种工艺,铜碟形是铜化学机械抛光工艺中的主要问题之一。严重的碟形缺陷会造成产品良率的缺失,使得利润下降。碟形是由于在抛光过程中铜线与介质层不同的抛光速率所导致。文章详细地介绍了铜化学机械抛光的基本步骤和不同作用,然后指出了在抛光过程中碟形产生的基本原理,最后对抛光过程中最重要的抛光液及其成份对碟形的影响进行了分析。通过试验各种成分的剂量组成不同配方的抛光液,最终给出了减少碟形的具体改进方案。     

蓝宝石衬底nm级CMP技术研究

介绍了蓝宝石衬底的化学机械抛光工艺,讨论分析了影响蓝宝石衬底化学机械抛光的因素,定量确定了最佳CMP工艺。提出先以重抛过程提高蓝宝石抛光速率,然后以轻抛过程降低最终表面粗糙度的工艺路线。在配制抛光液时加入FA/OⅠ型活性剂保护SiO2胶粒的双电子层结构。在轻抛过程之前抛光垫用原液浸泡20～30min,抛光磨料直径为20～40nm。实验最佳工艺条件下的抛光速率达231.6nm/min,粗糙度降至0.34nm。     

化学机械抛光（CMP）设备增势迅猛

化学机械抛光（ＣＭＰ）设备增势迅猛近来，随着硅片直径的不断增大（＞２００ｍｍ）和图形线宽的急骤缩小（＜０．３５μｍ），ＩＣ加工工艺对圆片的平整度要求越来越高。单一的化学或机械方法抛光的片子很难满足工艺要求，而九十年代兴起的化学机械抛光方法则从加工性能...     

化学机械抛光后板刷擦洗清洗(英文)

板刷擦洗是一种在化学机械抛光后清洗中常用的方法。它可以非常有效地把研磨剂颗粒从已抛光的晶圆表面去除掉。在氧化硅化学机械抛光的清洗工艺中,去离子水(或者稀释的氢氧化氨)是刷洗过程中常用的化学品起到的作用及刷洗的机械力对去除氧化硅研磨剂颗粒时所起的作用。     

CMP设备市场及技术现状

综述全球CMP设备市场概况及适应0.18μm工艺平坦化要求的CMP技术现状,给出了向φ300mm圆片转移过程中CMP技术占用成本及CMP设备性能指标.     

Critical Dimension Uniformity Via Real-Time Photoresist Thickness Control

In this paper, we present the experimental results on wafer-to-wafer and within-wafer critical dimension (CD) control. It is known that photoresist thickness affects CD. In this paper, we control photoresist thickness to control CD. As opposed to run-to-run control where information from the previous wafer or batch is used for control of the current wafer or batch, the approach here is real time and makes use of the current wafer information for control of the current wafer CD. The experiments demonstrate that such an approach can reduce CD nonuniformity wafer to wafer and within wafer.     

Manufacturability aspects in low-temperature nickel silicidation: Temperature control and repeatability

In this paper, results obtained on nickel silicidation and nickel−platinum silicidation in a RTA system based on conductive heating are presented. It is shown that with the Levitor system, it is possible to obtain silicide uniformities <1% at temperatures as low as 240 °C. Next to these, within-wafer results, run-to-run uniformity results are presented. The run-to-run results, monitored over 18 weeks, show that with the Levitor system the temperature repeatability is within a band of 1.5 °C.It can be concluded that with the Levitor system excellent within-wafer and run-to-run, uniformities can be obtained at temperatures well within the process window for nickel silicidation.     

Planning wafer allocation for CMOS process development. Anonparametric approach

In this paper, we present techniques that can be used to answer the following two questions: (1) how many wafers need to be allocated per treatment to detect a given difference in a device performance metric and (2) how can one determine if a given treatment significantly improved a performance metric? The approach presented here does not make any assumptions regarding the shape of the distribution or the spatial dependency structure for the within-wafer performance measurements and remains applicable for a variety of performance metrics, such as mean, variance, and median. The analysis method can be used in decisions regarding the appropriateness of allocating half or quarter wafer splits to a treatment. Furthermore, the approach allows us to evaluate and compare within-wafer sampling strategies for comparing performance metrics from competing flows     

碱性铜精抛液中表面活性剂ADS对平坦化效果的影响

研究了阴离子表面活性剂十二烷基硫酸铵(ADS)在弱碱性铜抛光液中对晶圆平坦化效果的影响.对不同质量分数的阴离子表面活性剂ADS下的抛光液表面张力、铜去除速率、抛光后铜膜的碟形坑高度、晶圆片内非均匀性和表面粗糙度进行了测试.实验结果表明,当阴离子表面活性剂ADS的质量分数为0.2％时,抛光液的表面张力降低,铜的去除速率为202.5 nm·min-1,去除速率片内非均匀性减小到4.15％,抛光后铜膜的碟形坑高度从132 nm降低到68.9 nm,表面粗糙度减小到1.06 nm.与未添加表面活性剂相比,晶圆表面的平坦化效果得到改善.     

Analyses of thermal stresses and control schemes for fasttemperature ramps of batch furnaces [IC manufacture]

This work studies fast temperature ramps of batch furnaces under different control schemes based on thermal and stress analyses. A thermal model is first developed to predict temperature distributions on silicon wafers during ramping processes. Thermoelastic model of stresses is then used to predict the onset of slip-line generation under dynamic conditions. Three control schemes, one based on a maximum allowable within-wafer temperature difference, one with a constant cooling rate, and the third based on the condition for onset of slip generation, are then analyzed. The results show that in order to achieve the highest ramp rates while maintaining defect-free wafer processing, the ultimate criterion for temperature control of the furnaces should be the condition for the onset of defect generation instead of the conventional scheme based on constant ramp rates     

Impact of within-wafer process variability on radiation response

The impact of sample-to-sample variability on total ionizing dose (TID) response within-wafer for a 180-nm CMOS technology has been studied. Large variations in leakage current and threshold voltage shift after irradiation are observed. These variations are mainly contributed to the process variability. The process steps which cause TID response variation are preliminarily discussed.     

高温离子注入靶盘设计

简要介绍了高温离子注入靶室的设计。通过设计辅助加热装置使离子注入时晶片表面温度达到500℃以上,并通过靶盘旋转和往返平移扫描的方式实现了晶片片内和片间的温度均匀性,满足了碳化硅掺杂、SOI晶片制造等特殊需要。     

LPCVD silicon nitride uniformity improvement using adaptive real-time temperature control

An effective approach to improve silicon nitride thickness uniformity has been demonstrated on a batch LPCVD furnace platform. Implementation of adaptive real-time temperature control provides accurate, real-time estimation of substrate temperature profiles that enables model-based optimization of process temperature. Optimization of a 200-nm silicon nitride deposition yielded long-term, overall nitride thickness uniformity of 0.79% 1/spl sigma/ over a seven-week period, compared to 1.24% for an equivalent PID-tuned process. Three sequential silicon nitride deposition iterations were implemented in the process recipe to enable increased temperature ramp rates for more efficient optimization of within-wafer uniformity. The optimized process requalified quickly after major and minor equipment maintenance, and is suitable for use in a manufacturing environment. The ART-optimized temperature ramp intervals used in this study are comparable to temperature deltas often used to offset dichlorosilane depletion effects encountered in some large-batch vertical furnace depositions. SIMS depth profiling of ART-optimized silicon nitride does reveal small oxygen and chlorine peaks, indicating slight interface formation between deposition steps.     

Dielectric resolution enhancement coating technology (DiRECT) - a sub-90 nm space and hole patterning technology using 248-nm lithography and plasma-enhanced polymerization

A plasma polymerization coating process named Dielectric Resolution Enhancement Coating Technology (DiRECT) is proposed to shrink critical dimensions (CDs) of space and hole patterns. Fluorocarbon plasmas are used as the precursors to coat a polymer layer on the patterned photo-resist. By adding only one processing step, we are able to shrink poly space and contact hole to sub-90 nm-level using 248-nm lithography. The results of our extensive tests have demonstrated the production-worthiness of this technique for its consistent lot-to-lot repeatability, tight within-wafer CD uniformity, and low defect level.     

High-speed operation of a low-power 4-bit serial-to-parallel converter

This paper presents a high-speed low-power 4-bit superconducting serial-to-parallel converter (SPC) that has been demonstrated experimentally to operate at data rates up to 1 Giga-bits (Gb/s). The primary design goals for this device are high-speed operation, low-power dissipation, and high circuit yield for use as a core element in an address decoder or a demultiplexer. First, the circuit design and optimization are discussed. Simulated performance of the circuit shows proper operation at 20 Gb/s, with a discussion of its potential for use at even higher rates. The power dissipation is computed to be 28 /spl mu/W in continuous operation and the predicted within-wafer yield is 95%. Measured results are then given for data rates of 100 Mb/s and 1 Gb/s.