Systematic Width-and-Length Dependent CMOS Transistor Mismatch Characterization and Simulation

This paper presents a methodology for characterizing the random component of transistor mismatch in CMOS technologies. The methodology is based on the design of a special purpose chip which allows automatic characterization of arrays of NMOS and PMOS transistors of different sizes. Up to 30 different transistor sizes were implemented in the same chip, with varying transistors width W and length L. A simple strong inversion large signal transistor model is considered, and a new five parameters MOS mismatch model is introduced. The current mismatch between two identical transistors is characterized by the mismatch in their respective current gain factors /, V _TO threshold voltages , bulk threshold parameters , and two components for the mobility degradation parameter mismatch ₀ and _e. These two components modulate the mismatch contribution differently, depending on whether the transistors are biased in ohmic or in saturation region. Using this five parameter mismatch model, an extraordinary fit between experimental and computed mismatch is obtained, including minimum length (1 m) transistors for both ohmic and saturation regions. Standard deviations for these five parameters are obtained as well as their respective correlation coefficients, and are fitted to two dimensional surfaces f(W, L) so that their values can be predicted as a function of transistor sizes. These functions are used in an electrical circuit simulator (Hspice) to predict transistor mismatch. Measured and simulated data are in excellent agreement.     

An alternative to source degeneration of CMOS differential pair

This paper presents a method to extend linear range of conventional CMOS source-coupled pair with transistor polarised on saturation of strong inversion. The used principle is similar to the principle of source degeneration, but the additional device is horizontally added, in parallel with the input transistors, which overcame the constraints on common mode range and supply voltage and allow low voltage operation. SPICE simulations using 0.35 μm CMOS process and a bias current of 10 μA, show that for less than 1% of transconductance variation, the linear range is up to 0.35 V _pp in comparison to 0.1 V _pp for source-degenerated pair, and 0.01 V _pp for conventional differential pair, under the same biasing current and geometrical dimensions.     

Optimizing Drain Current, Inversion Level, and Channel Length in Analog CMOS Design

This paper describes a methodology for selecting drain current, inversion level (represented by inversion coefficient), and channel length for optimum performance tradeoffs in analog CMOS design. Here, inversion coefficient replaces width as a design choice to permit a conscious optimization of inversion level while width is implicitly considered. Transconductance, gate-referred thermal-noise voltage, and drain-source saturation voltage are optimized towards weak inversion while transconductance linearity and drain-referred thermal-noise current are optimized in strong inversion. Voltage gain, flicker noise, and dc mismatch are optimized towards weak inversion at long channel length while bandwidth is optimized in strong inversion at short channel length. Optimization expressions are given along with measured transconductance efficiency and Early voltage from weak through strong inversion over a wide range of channel lengths. Transconductance efficiency and Early voltage are used as normalized measures of transconductance and drain-source resistance, independent of drain current. The methodology presented is used to design three 0.5-μm operational transconductance amplifiers having equal 50-μA bias currents, but different tradeoffs in gain, bandwidth, noise, and dc mismatch. The amplifiers have measured voltage gains of 16.8, 110, and 326 V/V, −3-dB bandwidths of 350, 51, and 5 MHz, input-referred flicker-noise voltage at 100 Hz of 2,000, 450, and 58 nV/Hz^1/2, and input-referred dc mismatch voltages of 10.2, 2.2, and 1.1 mV respectively. The design methodology can be readily extended to deeper submicron CMOS processes. David M. Binkley (S’81, M’82, SM’93) joined the University of North Carolina at Charlotte in 2000 as an associate professor in the electrical and computer engineering department. Dr. Binkley and his students are researching analog design and testing methodologies including micropower, low-noise analog CMOS design for neural implants and radiation hardened, deep space applications. Dr. Binkley was a cofounder and vice president of integrated circuit development at Concorde Microsystems and senior scientist at CTI PET Systems where he designed both discrete and integrated CMOS electronics for positron emission tomography (PET) medical imaging systems. Concorde and CTI are currently part of Siemens Medical Solutions. Dr. Binkley received the B.S., M.S., and Ph.D. degrees in electrical engineering from the University of Tennessee, Knoxville. He is the author of over 60 papers in analog circuit design and instrumentation and holds five U.S. patents. Dr. Binkley is currently writing the book, Analog CMOS Design, Tradeoffs and Optimization, for John Wiley and Sons with planned publication in 2006. Benjamin J. Blalock (S’, M’) received his B.S. degree in electrical engineering from the University of Tennessee, Knoxville, in 1991 and the M.S. and Ph.D. degrees in electrical engineering from the Georgia Institute of Technology, Atlanta, in 1993 and 1996 respectively. He joined the Department of Electrical and Computer Engineering at Mississippi State University in 1996 and the University of Tennessee in 2001. His current research focus includes mixed-signal/mixed-voltage circuit design for systems-on-a-chip in SOI technology, analog IC design for extreme environments, multi-gate transistors and circuits on SOI, body-driven circuit techniques for ultra low-voltage analog, and bio-microelectronics. He has over 25 publications in the field of analog IC design and has contributed to The Circuits and Filters Handbook. He has also worked as an analog IC design consultant for Cypress Semiconductor Corp. and Concorde Microsystems, Inc. James M. Rochelle (M’84) received the B.S., M.S., and Ph.D. degrees in Electrical engineering from the University of Tennessee, Knoxville. From 1965 to 1982 he was with the Instrumentation and Controls Division of the Oak Ridge National Laboratory. From 1982 to 2001, he was Associate Professor of Electrical and Computer Engineering at the University of Tennessee, Knoxville teaching and conducting research in integrated circuit device modeling and mixed-signal integrated circuit design. In 2001 he retired from academia and is presently an emeritus associate professor and vice president of ASIC development at Concorde Microsystems, Inc., now part of Siemens Medical Solutions located in Knoxville, Tennessee. His current research interests are mixed-signal ASIC's for medical imaging readout electronics and micropower battery-powered devices.     

Effective parameter extraction using multiple-objective function for VLSI circuits

In this paper an input stage and an output stage are presented for application in low-voltage CMOS operational amplifiers. The input stage operates in strong inversion and has a rail-to-rail common-mode input voltage range. The transconductance (g _m ) is insensitive to the common-mode input voltage. The class AB output stage has a rail-to-rail output range. A class AB control circuit prevents any transistors in the output stage from switching off. This improves the large-signal high-frequency behavior and the step response of the amplifier. A complete two-stage Op Amp employing the proposed input and output stages was realized in a semi-custom CMOS process with minimum channel lengths of 10µm and transistor threshold voltages of approximately 0.7 V. The measured minimum supply voltage is 2.5 V. The measured input voltage range exceeds the supply rails and the output voltage reaches both rails within 130 mV. The unity-gain bandwidth of the complete Op Amp is severely limited by the long channel lengths. Simulations show that a unity-gain bandwidth of 7 MHz is feasible if 2.5µm channel lengths are used.     

Optimal superior-order curvature-corrected voltage reference based on the weight difference of gate-source voltages

A new curvature-correction technique for improving the temperature behavior of a CMOS voltage reference will be presented. The reducing of the temperature coefficient for the reference voltage will be realized compensating the nonlinear temperature dependence of the gate-source voltage for a MOS transistor working in weak inversion with the difference between two gate-source voltages. These MOS transistors are biased at drain currents with different temperature dependencies (PTAT and PTAT ^α, respectively), α parameter being selected to the optimal value for the implementing technology. The PTAT voltage generator will be designed using an original Offset Voltage Follower block, with the advantage of a reduced silicon occupied area as a result of replacing classical resistors by MOS active devices. SPICE simulation reports TC = 1.95 ppm/K for an extended temperature range, 273 K < T < 363 K, without considering the parameters spread. The circuit is compatible with low-power low-voltage designed, having a maximal power consumption of 0.4 μW for a minimal supply voltage of 1.1 V.     

A new five-parameter MOS transistor mismatch model

A new five-parameter MOS transistor mismatch model is introduced capable of predicting transistor mismatch with very high accuracy for ohmic and saturation regions, including short-channel transistors. The new model is based on splitting the contribution of the mobility degradation parameter mismatch Δ&thetas; into two components, and modulating them as the transistor transitions from ohmic to saturation regions. The model is tested for a wide range of transistor sizes (30), and shows excellent precision, never reported before for such a wide range of transistor sizes, including short-channel transistors     

A CMOS threshold voltage reference source for very-low-voltage applications

This paper describes a CMOS voltage reference that makes use of weak inversion CMOS transistors and linear resistors, without the need for bipolar transistors. Its operation is analogous to the bandgap reference voltage, but the reference voltage is based on the threshold voltage of an nMOS transistor. The circuit implemented using 0.35 μm n-well CMOS TSMC process generates a reference of 741 mV under just 390 nW for a power supply of only 950 mV. The circuit presented a variation of 39 ppm/°C (after individual resistor trimming) for the −20 to +80 °C temperature range, and produced a line regulation of 25 mV/V for a power supply of up to 3 V.     

MOS Translinear Principle for All Inversion Levels

In this brief, we derive a translinear principle for alternating loops of saturated MOS transistors that is valid at all levels of inversion starting from a simplified version of the Enz-Krummanacher-Vittoz model of the MOS transistor. This generalized translinear principle reduces to the conventional one when all transistors in a translinear loop are biased in weak inversion and it reduces to the voltage-translinear principle when all transistors in the loop are biased in strong inversion. We show experimental measurements from an alternating loop of four nMOS transistors that was fabricated in a 0.5-mum CMOS process through MOSIS to corroborate the generalized translinear principle. Finally, we discuss some potential applications of the principle.     

An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications

A fully analytical MOS transistor model dedicated to the design and analysis of low-voltage, low-current analog circuits is presented. All the large- and small-signal variables, namely the currents, the transconductances, the intrinsic capacitances, the non-quasi-static transadmittances and the thermal noise are continuous in all regions of operation, including weak inversion, moderate inversion, strong inversion, conduction and saturation. The same approach is used to derive all the equations of the model: the weak and strong inversion asymptotes are first derived, then the variables of interest are normalized and linked using an appropriate interpolation function. The model exploits the inherent symmetry of the device by referring all the voltages to the local substrate. It is shown that the inversion chargeQ _inv is controlled by the voltage differenceV _P – V_ch, whereV _ch is the channel voltage, defined as the difference between the quasi-Fermi potentials of the carriers. The pinch-off voltageV _P is defined as the particular value ofV _ch such that the inversion charge is zero for a given gate voltage. It depends only on the gate voltage and can be interpreted as the equivalent effect of the gate voltage referred to the channel. The various modes of operation of the transistor are then presented in terms of voltagesV _P – V_S andV _P – V_D. Using the charge sheet model with the assumption of constant doping in the channel, the drain currentI _D is derived and expressed as the difference between a forward componentI _F and a reverse componentI _R. Each of these is proportional to a function ofV _P – V_S, respectivelyV _P – V_D, through a specific currentI _S. This function is exponential in weak inversion and quadratic in strong inversion. The current in the moderate inversion region is then modelled by using an appropriate interpolation function resulting in a continuous expression valid from weak to strong inversion. A quasi-static small-signal model including the transconductances and the intrinsic capacitances is obtained from an accurate evaluation of the total charges stored on the gate and in the channel. The transconductances and the intrinsic capacitances are modelled in moderate inversion using the same interpolation function and without any additional parameters. This small-signal model is then extended to higher frequencies by replacing the transconductances by first order transadmittances obtained from a non-quasi-static calculation. All these transadmittances have the same characteristic time constant which depends on the bias condition in a continuous manner. To complete the model, a general expression for the thermal noise valid in all regions of operation is derived. This model has been successfully implemented in several computer simulation programs and has only 9 physical parameters, 3 fine tuning fitting coefficients and 2 additional temperature parameters.     

New implementation of high linear LNA using derivative superposition method

New implementation of a high linear low-noise amplifier (LNA) using the improved derivative superposition (DS) method is proposed. The input stage is formed by two transistors connected in parallel. One transistor is biased in the strong inversion region as usual and another one is biased in the moderate inversion region instead of the weak inversion region, thus allowing a feasible source degeneration inductance at the sources of the two transistors to achieve a good input impedance matching and low noise figure (NF) while keeping high third-order input intercept point (IIP3) improvement with the DS method. The new implementation has been used in a 0.18-μm CMOS high linear LNA. The measured results show that the LNA achieves +11.92 dBm IIP3 with 9.36 dB gain, 2.25 dB NF and 7.5 mA at 1.8 V power consumption.     

An ultra-low-power CMOS symmetrical OTA for low-frequency <Emphasis Type="Italic">G</Emphasis><Subscript><Emphasis Type="Italic">m</Emphasis></Subscript>-<Emphasis Type="Italic">C</Emphasis> applications

In this paper an ultra-low-power CMOS symmetrical operational transconductance amplifier (OTA) for low-frequency G _m -C applications in weak inversion is presented. Its common mode input range and its linear input range can be made large using DC shifting and bulk-driven differential pair configuration (without using complex approaches). The symmetrical OTA was successfully verified in a standard CMOS 0.35-μm process. The measurements show an open loop gain of 61 dB and a unit gain frequency of 195 Hz with only 800 mV of power supply voltage and just 40 nW of power consumption. The transconductance is 66 nS, which is suitable for low-frequency G _m -C applications.     

Design of low noise charge amplifier in sub-micron technology for fast shaping time

A discussion of the noise optimisation of the fast charge sensitive amplifier (CSA) for imaging systems using highly segmented semiconductor detectors is presented. In such systems a limited power dissipation per single channel is available while a good noise performance and a fast signal processing time are required. This paper describes the CSA noise optimisation for several CMOS technology generations with the minimum transistor gate length ranging from 0.13μm to 0.8μm and for a detector capacitance in the range from 0.5 pF to 12 pF. In a well-designed CSA, followed by a fast shaper stage, an equivalent noise charge (ENC) is dominated by the thermal noise of an input MOS transistor. In the applications considered the input transistor usually works in a moderate inversion region where no simple formula for the noise performance exists. Our analyses are made using a simplified EKV model and are compared with HSPICE simulations using BSIM3v3 models. We show several novel aspects of the noise optimisation of the CSA regarding the optimum transistor width and the sensitivity of the ENC to this width. Paweł Gryboś was born in Bielsko-Bielsko, Poland, in 1967. He received M.Sc. degree in electronics in 1991, Ph.D. degree in physics in 1995 and habilitation Ph.D. degree in electronics in 2004 from the AGH University of Science and Technology in Cracow, Poland. His current research interests are in the areas of designing and testing of low noise, multichannel ASICs for physics and neurobiology applications. Marek Idzik graduated in Electronic Engineering (1990) at University of Science and Technology of Cracow and in Theoretical Physics (1991) at Jagiellonian University of Cracow, Poland. Received his Ph.D. in Experimental Physics (1995) at University of Science and Technology of Cracow. Since 1995 Assistant Professor at University of Science and Technology of Cracow. Research activity: design of VLSI electronics, physics of semiconductor detectors, heavy ion physics. Teaching activity in international schools: ICFA (1997) Leon, Mexico, ICFA (2004) Rio de Janeiro, Brasil. More than 50 scientific publications on international journals. Andrzej Skoczeń was born in Cracow, Poland, on February 25, 1962. He is an assistant professor in Nuclear Electronics Department at the Faculty of Physics and Applied Computer Science at the AGH University of Science and Technology in Cracow. He received his Ph.D. in physics in the field of semiconductor devices in May 1993. He is involved with problems concerning project and design of integrated circuits for physics experiments at DESY (Hamburg), GSI (Darmstadt) and CERN (Geneva). He deals with radiation sensors applications, CAD modeling, characterization, and VLSI mixed signal design. At his home institution he works also as a lecturer in the field of introduction to physics and electronics.     

Mismatch reduction technique for transistors with minimum channel length

An analog calibration technique is presented to improve the parameter matching between transistors in the differential high-frequency signal path of analog CMOS circuits. It can be applied for mismatch reduction in differential broadband amplifiers and direct down-conversion mixers in which short-channel devices are utilized to minimize bandwidth reduction from parasitic capacitances. In general, the proposed methodology is suitable for radio frequency (RF) applications in which direct matching of the transistors is undesired because sophisticated layout practices would increase the coupling between the high-frequency paths. The approach involves auxiliary devices which sense the existing mismatch as part of a feedback loop for error minimization. This technique is demonstrated with a differential amplifier that has a loaded gain and −3 dB frequency of 12.9 dB and 2.14 GHz, respectively. It was designed in 90 nm CMOS technology with a 1.2 V supply. Monte Carlo simulations indicate that the 4.06 mV standard deviation of the amplifier’s anticipated input-referred offset voltage improves to 0.76–1.28 mV with the mismatch reduction loop, which is contingent on the layout configuration of the calibration circuitry. The associated drain current mismatch reduction for the transistor pair under calibration in the amplifier core is from 3.1% to 0.6–1.0%.     

Robust Design of LV/LP Low-Distortion CMOS Rail-to-Rail Input Stages

Two robust CMOS rail-to-rail OpAmp input stages are presented for low voltage ( 3 V) applications. The robust input stages are implemented using two recently reported universal approaches to achieve constant transconductance. Transconductance control circuit is also introduced to compensate for K _p , K _n mismatch of PMOS and NMOS differential pairs in the input stage. The input stages are designed for operation in the strong inversion and have a rail-to-rail common mode input voltage range. Compared with an OpAmp with simple complementary input pairs, a two stage rail-to-rail OpAmp design example exhibits lower total harmonic distortion (THD) levels over the entire common mode input voltage range.currently on leave as a visiting scholar at OSU     

Characterization of subthreshold MOS mismatch in transistors for VLSI systems

MOS transistor mismatch is revisited in the context of subthreshold operation and VLSI systems. We report experimental measurements from large transistor arrays with device sizes typical for digital and analog VLSI systems (areas between 9 and 400μm²). These are fabricated at different production qualified facilities in 40-nm gate oxide,n-well andp-well, mask lithography processes. Within the small area of our test-strips (3 mm²), transistor mismatch can be classified into four categories: random variations, “edge,” “striation,” and “gradient” effects. The edge effect manifests itself as a dependence of the transistor current on its position with reference to the surrounding structures. Contrary to what was previously believed, edge effects extend beyond the outer most devices in the array. The striation effect exhibits itself as a position-dependent variation in transistor current following a sinusoidal oscillation in space of slowly varying frequency. The gradient effect is also a position-dependent spatial variation but of much lower frequency. When systematic effects are removed from the data, the random variations follow an inverse linear dependence on the square root of transistor area.     

FinFET for high sensitivity ion and biological sensing applications

A double-gate (DG) fin field effect transistor (FinFET) is discussed as new label-free ion and biological sensor. Simulations as function of channel doping, geometrical dimensions, operation point and materials investigated the device response to an external potential difference which provides a body threshold voltage modulation. The simulation results presented in this work clearly state the key features for an ultrasensitive FET based sensor: an enhancement low doped and partially gated transistor operating in weak-moderate inversion regime. The optimized sensitivity, obtained when the width of the fin is equal to the gate height (w_NW ∼ h_g), reaches a value of 85% for an extraction current, I_d, of 0.1 μA. These results pave the way for the fabrication process of an innovative CMOS compatible sensing system.     

A compact model of MOSFET mismatch for circuit design

This paper presents a compact model for MOS transistor mismatch. The mismatch model uses the carrier number fluctuation theory to account for the effects of local doping fluctuations along with an accurate and compact dc MOSFET model. The resulting matching model is valid for any operation condition, from weak to strong inversion, from the linear to the saturation region, and allows the assessment of mismatch from process and geometric parameters. Experimental results from a set of transistors integrated on a 0.35 /spl mu/m technology confirm the accuracy of our mismatch model under various bias conditions.     

A novel CMOS exponential transconductor operating in weak inversion

A novel CMOS exponential transconductor which employs only three NMOS transistors operating in weak inversion, is presented. The main advantage of the proposed circuit is its wide range of exponential behaviour, which reaches up to five decades of current range, and above 10 μA to an input voltage range of 800 mV. The physical realisation is achieved in two forms: in the first one, the circuit is implemented with discrete MOS transistor arrays by CD4007 series; in the second one, the circuit is fully integrated in a 0.5 μm CMOS standard process. Simulated and experimental results of the proposed exponential transconductor are also presented.     

Measurement of MOS current mismatch in the weak inversion region

Measures the current matching properties of MOS transistors operated in the weak inversion region. The authors measured a total of about 1400 PMOS and NMOS transistors produced in four different processes and report the results in terms of mismatch dependance on current density, device dimensions, and substrate voltage, without using any specific model for the transistor     

A Linear CMOS Voltage-to-Current Converter

An improved complementary metal oxide semiconductor (CMOS) voltage-to-current converter is presented. PMOS transistors are employed in the resistor-replacement and voltage-level shifting of the proposed converter to avoid the body effect. To accurately annihilate the nonlinear voltage terms, a better modeling of the drain-to-source current of the MOS transistor operating in the linear region is essential and is adopted. Specifically, the substrate-bias effect of the MOS transistor is treated more accurately in our design. Consequently, the nonlinearity of the large-signal transconductance of the converter is reduced. The voltage-to-current converter is designed and fabricated in a 0.35 μm CMOS technology. The fabricated circuit occupies an area of 267 μm × 197 μm (≈0.053 mm²) and dissipates 3.92 mW from a 3.3 V supply. The measured and simulated data are in good agreement. For a 1 V_P-P input voltage, the measured total harmonic distortion (THD) of the output current is less than 1.2%.