Application-specific economic analysis of integral passives inprinted circuit boards

This paper presents an application-specific economic analysis of the conversion of discrete passive components (resistors and capacitors) to integral passives that are embedded within a printed circuit board. In this study we assume that integral resistors are printed or plated directly onto wiring layers (as opposed to requiring a dedicated layer), that bypass capacitors, if present, are embedded by dielectric substitution into existing reference plane layers, and that singulated nonbypass capacitors, if present, are embedded using dedicated layer pair addition. The model presented performs three basic analyses. 1) Board size analysis is used to determine board sizes, layer counts, and the number of boards that can be fabricated on a panel. 2) Panel fabrication cost modeling including a cost of ownership model is used to determine the impact of throughput changes associated with fabricating integral passive panels. 3) Assembly modeling is used to determine the cost of assembling all discrete components, and their associated inspection and rework. The combination of these three analyses is used to evaluate size/cost tradeoffs for several example systems including the NEMI hand-held emulator, a picocell board, and a fiber channel card     

小尺寸分立器件与嵌入聚合物厚膜电阻在移动电话中的应用比较

随着移动电话越来越多功能的嵌入,设计者们不得不持续地寻求节省基板面积的方法.嵌入无源器件和使用小尺寸的分立器件(02 01)是两种较为通用的解决方法.文章考察了小尺寸的分立器件与嵌入式聚合物厚膜电阻在降低成本与节省基板面积间的协调和平衡.实验中运用高产量组装和艺术板制作技术组装小离散或聚合物厚膜电阻的方案分析了三种典型的移动电话的设计,并列举了各种方案对基板尺寸和成本的影响.     

Design of integrated low noise amplifiers (LNA) using embedded passives in organic substrates

The noise figure of a low noise amplifier (LNA) is a function of the quality factor of its inductors. The lack of high-Q inductors in silicon has prevented the development of completely integrated complementary metal oxide semiconductor (CMOS) LNAs for high sensitivity applications like global system for mobile communications (GSM) (1.9 GHz) and wideband code-division multiple-access (W-CDMA) (2.1GHz). Recent developments in the design of high-Q inductors (embedded in low cost integrated circuit (IC) packages) have made single-package integration of RF front-ends feasible. These embedded passives provide a viable alternative to using discrete elements or low-Q on-chip passives, for achieving completely integrated solutions. Compared to on-chip inductors with low Q values and discrete passives with fixed Q/sub s/, the use of these embedded passives also leads to the development of the passive Q as a new variable in circuit design. However, higher Q values also result in new tradeoffs, particularly with respect to device size. This paper presents a novel optimization strategy for the design of completely integrated CMOS LNAs using embedded passives. The tradeoff of higher inductor size for higher Q has been adopted into the LNA design methodology. The paper also presents design issues involved in the use of multiple embedded components in the packaging substrate, particularly with reference to mutual coupling between the passives and reference ground layout.     

Integrated RF architectures in fully-organic SOP technology

Future wireless communications systems require better performance, lower cost, and compact RF front-end footprint. The RF front-end module development and its level of integration are, thus, continuous challenges. In most of the presently used microwave integrated circuit technologies, it is difficult to integrate the passives efficiently with required quality. Another critical obstacle in the design of passive components, which occupy the highest percentage of integrated circuit and circuit board real estate, includes the effort to reduce the module size. These issues can be addressed with multilayer substrate technology. A multilayer organic (MLO)-based process offers the potential as the next generation technology of choice for electronic packaging. It uses a cost effective process, while offering design flexibility and optimized integration due to its multilayer topology. We present the design, model, and measurement data of RF-microwave multilayer transitions and integrated passives implemented in a MLO system on package (SOP) technology. Compact, high Q inductors, and embedded filter designs for wireless module applications are demonstrated for the first time in this technology.     

Implementing ASIC/memory integration by system-on-package

A system-on-package (SOP) solution of an application specific integrated circuit (ASIC) chip integrating with an embedded data output (EDO) memory die has been realized. Both chips are assembled into a new form factor that appears as a standard plastic ball grid array (PBGA) with 90 balls and 1.27 mm ball pitch. Topically, size reduction of approximately 60% over the equivalent printed circuit board implementation is achieved. Other benefits include simplified board design and reduction in material cost. Assembly processes are expressed to indicate how this package is made. Reliability analyzes such as: pre-conditioning, temperature cycle test (TCT), and pressure cook test (PCT), are conducted     

Design method and material technologies for passives in printed circuit Board Embedded circuits

The integration of passive components into the printed circuit board (PCB) as embedded passives integrated circuits (emPIC) results in a higher power density of power converters. To achieve a highly automated, low cost, integral manufacturing, the devices are constructed layer wise. Materials and processes necessary for the manufacturing of such circuits are described in this publication. Especially for magnetic components like inductors and transformers the design of such thin components is challenge. Because of the high aspect ratio, traditionally used models lead to a high calculation effort or use nonappropriate approximations. This contribution presents an analytic approach for the design. The model considers the magnetic flux distribution in the core and in the winding area and therefore allows a precise calculation of the inductivity as well as the losses in the device and their distribution. It is very well suited for a parametric analysis and thus for the synthesis of thin planar magnetic components. Material technologies for the construction of the capacitive layers and the magnetic cores are investigated. A ferrite polymer compound is adapted to be compatible with the PCB laminating process. Accordingly a 60-W offline converter was designed and fabricated using the new technology. Its transformer is entirely integrated in the PCB as well as 11 capacitors. Standard PCB lamination processes are used for the layerwise integration of the components. The circuit needs an area of the size of a credit card with a PCB thickness of 4 mm. Up to 82% efficiency could be demonstrated.     

A novel heuristic simulation‐optimization method for critical infrastructure in smart transportation systems

A simulation‐based optimization is a decision‐making tool that helps in identifying an optimal solution or a design for a system. An optimal solution and design are more meaningful if they enhance a smart system with sensing, computing, and monitoring capabilities with improved efficiency. In situations where testing the physical prototype is difficult, a computer‐based simulation and its optimization processes are helpful in providing low‐cost, speedy and lesser time‐ and resource‐consuming solutions. In this work, a comparative analysis of the proposed heuristic simulation‐optimization method for improving quality‐of‐service (QoS) is performed with generalized integrated optimization (a simulation approach based on genetic algorithms with evolutionary simulated annealing strategies having simplex search). In the proposed approach, feature‐based local (group) and global (network) formation processes are integrated with Internet of Things (IoT) based solutions for finding the optimum performance. Further, the simulated annealing method is applied for finding local and global optimum values supporting minimum traffic conditions. A small‐scale network of 50 to 100 nodes shows that genetic simulation optimization with multicriteria and multidimensional features performs better as compared to other simulation‐optimization approaches. Further, a minimum of 3.4% and a maximum of 16.2% improvement is observed in faster route identification for small‐scale IoT networks with simulation‐optimization constraints integrated model as compared to the traditional method. The proposed approach improves the critical infrastructure monitoring performance as compared to the generalized simulation‐optimization process in complex transportation scenarios with heavy traffic conditions. The communicational and computational‐cost complexities are least for the proposed approach.     

激光修整埋入无源元件的最佳设计

当设计具有埋入无源元件的PCB时,必须仔细考虑影响修整生产率和准确性的因素,而采用激光修整是最佳的。     

Cost and performance tradeoff analysis in radio and mixed-signal system-on-package design

An optimal total solution for radio and mixed-signal system integration needs tradeoffs between different design options. Among various design metrics, cost and performance are probably the two most important factors for design decisions. In this paper, we review and analyze cost-performance tradeoffs of system-on-chip (SOC) versus system-on-package (SOP) solutions for radio and mixed-signal applications. A new design methodology, which quantitatively predicts performance and cost gains of SOP versus SOC, is presented. The performance model evaluates various mixed-signal isolation techniques between sensitive analog/RF circuits and noisy digital circuits in SOC or SOP. The cost analysis includes new factors such as extra chip area and additional process steps for mixed-signal isolation, seamless integration of "virtual components" or intellectual property (IP) modules, yield and technology compatibility for merging logic, memory and analog/RF circuits on a single chip, and extra costs for moving passives off chip. In addition to these, a complete and systematic analysis method for on-chip versus off-chip passives tradeoffs is presented. The analysis and modeling techniques explore tradeoffs between performance, cost, robustness, and yield when different on-chip or off-chip passives are used. It thus provides a complete picture of quantitative tradeoffs for using on-chip or off-chip passives. The design methodology and analysis techniques are then demonstrated through several design examples in wireless applications. It is clearly shown that for all complex and high performance mixed-signal systems, SOP is a lower cost solution than SOC. Finally, some design guidelines for SOC versus SOP and on-chip versus off-chip are concluded.     

高集成度有源相控阵天线

相控阵系统要求降低成本、提高集成度,对此,提出一种无连接器馈电的一体化相控阵天线集成方法。该方法采用微波多层印制电路板为载体,电路板正面安装集成电路,反面装配阵列天线,内层集成馈电网络和电源分配网络。阵列采用金属槽缝天线,同时满足电辐射和热传导功能。按此方法加工了接收阵列样件,给出了测试结果,验证了方案可行性。与传统阵列相比,本方法中天线和馈电网络互联,省去了大量连接器、射频电缆和机械 支撑背板,从而大幅降低了加工复杂度、简化了装配流程、缩小了系统体积、降低了系统成本。     

印刷电子学的发展

综述了印刷电子学的发展及趋势,着重介绍了喷墨打印技术的新进展及其在印制电路板(PCB)和嵌入式无源元件中的应用,指出了目前印刷电子产品生产过程中尚待解决的问题,预测印刷电子电路(PEC)将是印刷电子学的未来发展方向。     

基于GA的系统冗余可靠性设计多目标优化模型

系统冗余可靠性多目标设计是一个复合最优化问题。传统的用于解决此类问题的方法,如拉格朗日乘子法、动态规划法、直接寻查法等,在系统单元较多的情况下存在着计算量大、难以获取全局最优解等问题。针对此问题,本文建立了基于遗传算法（GA）的系统冗余可靠性设计的多目标优化模型,该模型可在系统可靠性约束条件下,使系统的成本费用、体积、重量等指标达到最优设计。     

基于FPGA动态自重构的嵌入式系统设计

本文提出了一种设计动态自重构系统的设计方法。这种方法可以有效地利用现有的IP核,将其经过处理就可以作为动态重构系统的可重构IP核使用。该方法可降低开发成本,缩短设计周期,同时应用动态重构技术的系统层设计是目前的研究热点。本设计使用Xilinx公司新推出的ISE8．2i、EDK8．2i和PlanAhead9．2．7FPGA开发工具,依托XUP Virtex-ⅡPro xc2vp30 FF896-7 FPGA开发板为平台,以其内嵌微处理器为核心搭建了一个可重构系统。该设计有3个重构区域,每个区域有至少两个配置文件,可根据需要在软件程序的调配下实现动态配置。由此系统功能的灵活性和硬件资源的利用率将得到改善。     

Optimizing the performance of a surface mount placement machine

Process planning is an important and integral part of effectively operating a printed circuit board (PCB) assembly system. A PCB assembly system generally consists of different types of placement machines, testing equipment, and material handling equipment. This research develops a new solution approach to determine the component placement sequence and feeder arrangement for a turret style surface mount-placement machine often used in PCB assembly systems. This solution approach can be integrated into a process planning system to reduce assembly time and improve productivity. The algorithm consists of a construction procedure that uses a set of rules to generate an initial component placement sequence and feeder arrangement along with an improvement procedure to improve the initial solution. An industrial case study conducted at Ericsson, Inc., using a Fuji CP4-3 machine and actual PCB data, is presented to demonstrate the performance of the proposed solution approach. The solutions obtained using the proposed solution approach are compared to those obtained using state of the art PCB assembly process optimization software. For all PCBs in the case study, the proposed solution approach yielded lower placement times than the commercial software, thus generating additional valuable production capacity. This research is applicable for both researchers and practitioners in printed circuit board assembly systems     

PTFE埋电阻多层印制板制造技术

随着电子产品技术的发展,无源器件集成技术与聚四氟乙烯(PTFE)材料在多层印制电路板制造中扮演着越为重要的角色。论文在无源器件集成技术之一的薄膜埋电阻技术的基础上对PTFE埋薄膜电阻多层印制板制造工艺过程进行了讨论。     

Reliability Modeling and Assessment of Embedded Capacitors in Organic Substrates

Understanding and quantifying the RLC characteristics of the embedded passives under thermomechanical deformation during fabrication and accelerated thermal conditions is necessary for their successful implementation. Embedded passives are composite layers with dissimilar material properties compared to the neighboring layers in the integral substrate. The ongoing project explores the fabrication, multifield physics-based reliability modeling and accelerated testing of embedded passive test vehicles. As a first step, in this paper, the effect of thermomechanical deformation on the electrical characteristics of embedded capacitors is studied at frequencies from 100 KHz to 2 GHz using two test vehicles. Test vehicles with embedded passives were fabricated and were subjected to accelerated thermal cycles between -55degC to 125degC, between -40degC to 125degC and high humidity and temperature conditions of 85degC/85% RH. Significant changes in the electrical parameters of the embedded capacitors are observed. The fabrication process mechanics with multiphysics global-local modeling methodology is demonstrated to study the effect of thermal cycling on the electrical characteristics of embedded capacitors. The results obtained from the multiphysics global-local modeling methodology are validated against the measured electrical characteristics of the fabricated functional test boards. The effect of changes in electrical parameters of embedded passives on system performance of low-pass filters is presented     

Low-power data forwarding for VLIW embedded architectures

Proposes a low-power approach to the design of embedded very long instruction word (VLIW) processor architectures based on the forwarding (or bypassing) hardware, which provides operands from interstage pipeline registers directly to the inputs of the function units. The power optimization technique exploits the forwarding paths to avoid the power cost of writing/reading short-lived variables to/from the register file (RF). Such optimization is justified by the fact that, in application-specific embedded systems, a significant number of variables are short-lived, that is, their liveness (from first definition to last use) spans only few instructions. Values of short-lived variables can thus be accessed directly through the forwarding registers, avoiding writeback to the RF by the producer instruction and successive read from the RF by the consumer instruction. The decision concerning the enabling of the RF writeback phase is taken at compile time by the compiler static scheduling algorithm. This approach implies a minimal overhead on the complexity of the processor control logic and, thus, no critical path increase. The application of the proposed solution to a VLIW embedded core has shown an average RF power saving of 7.8% with respect to the unoptimized approach on the given set of target benchmarks.     

基于SiP技术的胶囊内窥镜微型电路系统制造

胶囊内窥镜是近年发展起来的微型医疗仪器,其电路构造具有体积小、功能全等特点。文章提出用高密度封装SiP技术实现胶囊内窥镜的电路系统微型化。相对传统的芯片定制方式,采用堆叠式、表面贴装式或倒装焊式等组装方式具有成本低、难度低、开发周期短的优点。SiP封装、埋植式元件基板制造等高密度封装技术的不断发展,使得采用普通商用芯片实现胶囊内窥镜电路系统制造具有可行性。     

Reliability optimization models for embedded systems with multiple applications

Summary and Conclusions-This paper presents four models for optimizing the reliability of embedded systems considering both software and hardware reliability under cost constraints, and one model to optimize system cost under multiple reliability constraints. Previously, most optimization models have been developed for hardware-only or software-only systems by assuming the hardware, if any, has perfect reliability. In addition, they assume that failures for each hardware or software unit are statistically independent. In other words, none of the existing optimization models were developed for embedded systems (hardware and software) with failure dependencies. For our work, each of our models is suitable for a distinct set of conditions or situations. The first four models maximize reliability while meeting cost constraints, and the fifth model minimizes system cost under multiple reliability constraints. This is the first time that optimization of these kinds of models has been performed on this type of system. We demonstrate and validate our models for an embedded system with multiple applications sharing multiple resources. We use a Simulated Annealing optimization algorithm to demonstrate our system reliability optimization techniques for distributed systems, because of its flexibility for various problem types with various constraints. It is efficient, and provides satisfactory optimization results while meeting difficult-to-satisfy constraints.     

Hardware-Software Partitioning for Real-Time Embedded Systems

In this paper, we present an approach to hardware-software partitioning for real-time embedded systems. Hardware and software components are modeled at the system level, so that cost and performance tradeoffs can be studied early in the design process and a large design space can be explored. Feasibility factor is introduced to measure the possibility of a real-time system being feasible, and is used as both a constraint and an attribute during the optimization process. An imprecise value function is employed to model the tradeoffs among multiple performance attributes. Optimal partitioning is achieved through the use of an existing computer-aided design tool. We demonstrate the application of our approach through the design of an example embedded system.