A 1-MHz-bandwidth second-order continuous-time quadrature bandpass sigma-delta modulator for low-IF radio receivers

This paper presents a quadrature bandpass /spl Sigma//spl Delta/ modulator with continuous-time architecture. Due to the continuous-time architecture and the inherent anti-aliasing filter, the proposed /spl Sigma//spl Delta/ modulator needs no additional anti-aliasing filter in front of the modulator in contrast to quadrature bandpass /spl Sigma//spl Delta/ modulators with switched-capacitor architectures. The second-order /spl Sigma//spl Delta/ modulator digitizes complex analog I/Q input signals at 1-MHz intermediate frequency and operates within a clock frequency range of 25-100 MHz. The modulator chip achieves a peak signal-to-noise-distortion ratio (SNDR) of 56.7 dB and a dynamic range of 63.8 dB within a 1-MHz signal bandwidth and at a clock frequency of 100 MHz. Furthermore, it provides an image rejection of at least 40 dB. The 0.65-/spl mu/m BiCMOS chip consumes 21.8 mW at 2.7-V supply voltage.     

IF-sampling fourth-order bandpass /spl Delta//spl Sigma/ modulator for digital receiver applications

Bandpass modulators sampling at high IFs (/spl sim/200 MHz) allow direct sampling of an IF signal, reducing analog hardware, and make it easier to realize completely software-programmable receivers. This paper presents the circuit design of and test results from a continuous-time tunable IF-sampling fourth-order bandpass /spl Delta//spl Sigma/ modulator implemented in InP HBT IC technology for use in a multimode digital receiver application. The bandpass /spl Delta//spl Sigma/ modulator is fabricated in AlInAs-GaInAs heterojunction bipolar technology with a peak unity current gain cutoff frequency (f/sub T/) of 130 GHz and a maximum frequency of oscillation (f/sub MAX/) of 130 GHz. The fourth-order bandpass /spl Delta//spl Sigma/ modulator consists of two bandpass resonators that can be tuned to optimize both wide-band and narrow-band operation. The IF is tunable from 140 to 210 MHz in this /spl Delta//spl Sigma/ modulator for use in multiple platform applications. Operating from /spl plusmn/5-V power supplies, the fabricated fourth-order /spl Delta//spl Sigma/ modulator sampling at 4 GSPS demonstrates stable behavior and achieves a signal-to-(noise + distortion) ratio (SNDR) of 78 dB at 1 MHz BW and 50 dB at 60 MHz BW. The average SNDR performance measured on over 250 parts is 72.5 dB at 1 MHz BW and 47.7 dB at 60 MHz BW.     

A third-order /spl Sigma//spl Delta/ modulator in 0.18-/spl mu/m CMOS with calibrated mixed-mode integrators

This paper describes a third-order sigma-delta (/spl Sigma//spl Delta/) modulator that is designed and implemented in 0.18-/spl mu/m CMOS process. In order to increase the dynamic range, this modulator takes advantage of mixed-mode integrators that consist of analog and digital integrators. A calibration technique is applied to the digital integrator to mitigate mismatch between analog and digital paths. It is shown that the presented modulator architecture can achieve a 12-dB better dynamic range than conventional structures with the same oversampling ratio (OSR). The experimental prototype chip achieves a 76-dB dynamic range for a 200-kHz signal bandwidth and a 55-dB dynamic range for a 5-MHz signal bandwidth. It dissipates 4 mW from 1.8-V supply voltages and occupies 0.7-mm/sup 2/ silicon area.     

A 1 GHz CMOS analog front-end for a generalized PRML read channel

A 1 GHz CMOS analog front-end for general partial response maximum likelihood (GPRML) read channel in hard disk drive application has been implemented in 0.35 /spl mu/m CMOS. A continuous time analog filter fulfills the relaxed equalization for GPRML detection and can save up to 35% power consumption for the whole read channel. An analog DFE-based timing recovery loop is implemented to avoid the extremely long latency in the digital signal processing path (Viterbi decoder). The measured performances is 1.1 dB off simulations at 800 MHz and 1.6 dB off at 1GHz. The chip draws 240 mW from a 3.3 V supply at 800MHz clock and 380 mW from a 3.6 V supply at 1 GHz clock.     

A four-channel digital signal processor in 1.2-μm CMOS withon-chip D/A and A/D conversion serving four speech channels in anew-generation subscriber line circuit

The major component for a new-generation line circuit was designed and fabricated in a 1.2-μm CMOS technology. The circuit includes digital signal processing of receive (RX) and transmit (TX) signals as well as the analog front end of four subscriber lines to a PCM (pulse code modulation) digital exchange. The device operates on a single 5-V power supply. The four-channel digital signal-processor including the analog front ends is fabricated on a 40-mm² 1.2-μm CMOS die area. The DSP functions, the RX and TX filters, the decimator, the interpolator, and the A/μ-law transcoder are included as independent data paths, one for the TX and RX filters, one for the decimator, and another for the interpolator, the digital sigma-delta modulator, and the transcoder. The on-chip analog front end contains a notch filter to cancel the 12/16-kHz payphone signal, a switched-capacitor PDM A/D and D/A converter, and smoothing filters. On the first measured samples, the signal-to-distortion ratio is measured to be 33 dB at -45 dBmo for -7 dB gain setting     

A cascaded continuous-time /spl Sigma//spl Delta/ Modulator with 67-dB dynamic range in 10-MHz bandwidth

This paper presents the design of a 2-2 cascaded continuous-time sigma-delta modulator. The cascaded modulator comprises two stages with second-order continuous-time resonator loopfilters, 4-bit quantizers, and feedback digital-to-analog converters. The digital noise cancellation filter design is determined using continuous-time to discrete-time transformation of the sigma-delta loopfilter transfer functions. The required matching between the analog and digital filter coefficients is achieved by means of simple digital calibration of the noise cancellation filter. Measurement results of a 0.18-/spl mu/m CMOS prototype chip demonstrate 67-dB dynamic range in a 10-MHz bandwidth at 8 times oversampling for a single continuous-time cascaded modulator. Two cascaded modulators in quadrature configuration provide 20-MHz aggregate bandwidth. Measured anti-alias suppression is over 50 dB for input signals in the band from 150 to 170 MHz around the sampling frequency of 160 MHz.     

A monolithic ΣΔ A/D and D/A converter with filter forbroad-band speech coding

The authors present a 5-V-only 14-b, 16 ksamples/s linear codec suitable as the audio part of a CCITT G722 codec. The device uses second-order sigma-delta modulation for both analog/digital (A/D) and digital/analog (D/A) conversion at 2.048 Msamples/s. A time-continuous modulator with integrated antialias filtering is used at the A/D side, obviating the need for an external antialiasing filter. The digital filters for decimation and interpolation are implemented with both a custom digital signal processor (DSP) and specialized hardware. The device was realized with 74000 transistors on a 31-mm² die in a 3-μm SACMOS technology. A dynamic range of more than 80 dB and a passband ripple of 0.3 dB were attained with A/D and D/A paths in cascade     

Single-chip per channel codec with filters utilizing /spl Delta/-/spl Sigma/ modulation

A single-chip per channel codec with filters, fabricated using a single poly-Si NMOS technology, is discussed. In the encoder, the analog signal is converted to a 2.048 M samples/s digital signal by a /spl Delta/-/spl Sigma/ modulator. Filtering necessary for the sampling rate 8 k sample/s and compression by the /spl mu/255 law are performed digitally. In the decoder, the 8 k samples/s PCM is successively resampled and converted into the 2.048 M samples/s /spl Delta/-/spl Sigma/ signal, which is then decoded by a /spl Delta/-/spl Sigma/ demodulator. All the high-frequency images, which appear around multiples of 8 kHz, are removed by digital filters. The chip has continuous-signal antialiasing and smoothing filters for the 2.048 Samples/s sampling rate. It also has reference voltage generators for /spl Delta/-/spl Sigma/ modulation/demodulation. Some of the observed characteristics are given. The NMOS /spl Delta/-/spl Sigma/ modulator requires only two on-chip matched capacitors as precision components, and does not require a linear amplifier. A deliberate quantization step imbalance is introduced to allow a low sampling rate. The main band limiting for the 8 k samples/s is done by the recursive filter. This is realized with the serial-parallel pipeline multiplier (SPPM) in four-phase logic. The whole system is integrated on a 296 mil/spl times/342 mil chip.     

A 1-V 3.5-mW CMOS switched-opamp quadrature IF circuitry for Bluetooth receivers

A 1-V switched-capacitor (SC) quadrature IF circuitry for Bluetooth receivers is demonstrated using switched-opamp technique. To achieve double power efficiency while maintaining low sensitivity to finite opamp gain effects for the SC IF circuitry, half-delay integrator-based filters and /spl Sigma//spl Delta/ modulator have been proposed. The proposed quadrature IF circuitry employs a seventh-order IF filter for channel selection and a third-order /spl Sigma//spl Delta/ modulator for analog-to-digital conversion. A noise-shaping extension technique is employed to enhance the resolution of the low-pass /spl Sigma//spl Delta/ modulator by 16 dB while operating at the same oversampling ratio and power consumption. At a 1-V supply, the quadrature IF circuitry achieves a measured IIP3 of -3 dBm at a nominal gain of 24 dB with a 48-dB variable gain control while consuming a total power dissipation of 3.5 mW.     

A 64-MHz clock-rate /spl Sigma//spl Delta/ ADC with 88-dB SNDR and -105-dB IM3 distortion at a 1.5-MHz signal frequency

A 64-MHz clock rate sigma-delta (/spl Sigma//spl Delta/) analog-to-digital converter (ADC) with -105-dB intermodulation distortion (IMD) at a 1.5-MHz signal frequency is reported. A linear replica bridge sampling network enables the ADC to achieve high linearity for high signal frequencies. Operating at an oversampling ratio of 29, a 2-1-1 cascade with a 2-b quantizer in the last stage reduces the quantization noise level well below that of the thermal noise. The measured signal-to-noise and distortion ratio (SNDR) in 1.1-MHz bandwidth is 88 dB, and the spurious-free-dynamic-range (SFDR) is 106 dB. The modulator and reference buffers occupy a 2.6-mm/sup 2/ die area and have been implemented with thick oxide devices, with minimum channel length of 0.35 /spl mu/m, in a dual-gate 0.18-/spl mu/m 1.8-V single-poly five-metal (SP5M) digital CMOS process. The power consumed by the ADC is 230 mW, including the decimation filters.     

A 2.5-V 57-MHz 15-tap SC bandpass interpolating filter with 320-MS/s output for DDFS system in 0.35-/spl mu/ hboxm CMOS

A switched-capacitor (SC) bandpass interpolating filter is proposed with the capability of achieving, simultaneously, channel selection and frequency up-translation, together with sampling rate increase, in a multirate configuration at high frequency. This filter has been designed for efficient use in a direct-digital frequency synthesis (DDFS) system with considerable rewards in terms of speed reduction of the digital core plus the digital-to-analog converter (DAC), as well as in the relaxation of the continuous-time (CT) smoothing filter order. It exhibits a 15-tap finite impulse response (FIR), with a bandpass frequency response centered at 57 MHz and a stop-band rejection higher than 45 dB. At the same time, it translates 22-24 MHz input signals at 80 MS/s, to the frequency range of 56-58 MHz in the output at 320 MS/s, allowing also a perfect operation at 400 MS/s, in 0.35-/spl mu/m CMOS technology. To implement a specific multi-notch FIR function, the filter architecture will comprise an effective low-speed polyphase-based interpolation structure with autozeroing capability, high-speed SC circuitry with fast opamps, and also ultra-low timing-skew multiple phase generation in order to achieve high-performance operation at high frequency. The prototype ICs present a signal-to-noise-and-distortion ratio (SNDR) of 61 dB, with a dynamic range of 69 dB, for 1% THD, and 61 dB, for 1% IM3. It consumes 2 mm/sup 2/ of active silicon area, 120 mW (analog) and 16 mW (digital) power, with a single 2.5-V supply, which corresponds to 8.6 mW of analog power per zero.     

Hybrid /spl Sigma//spl Delta/ modulators with adaptive calibration

This paper describes an architecture for stable high-order /spl Sigma//spl Delta/ modulation. The architecture is based on a hybrid /spl Sigma//spl Delta/ modulator, wherein hybrid integrators replace conventional analog integrators. The hybrid integrator, which is a combination of an analog integrator and a digital integrator, offers an increased dynamic range and helps make the resulting high-order /spl Sigma//spl Delta/ modulator stable. However, the hybrid /spl Sigma//spl Delta/ modulator relies on precise matching of analog and digital paths. In this paper, a calibration technique to alleviate possible mismatch between analog and digital paths is proposed. The calibration adaptively adjusts the digital integrators so that their transfer functions match the transfer functions of corresponding analog integrators. Through behavioral-level simulations of fourth-order /spl Sigma//spl Delta/ modulators, the calibration technique is verified.     

A 1.5-V 75-dB dynamic range third-order G/sub m/-C filter integrated in a 0.18-/spl mu/m standard digital CMOS process

A design methodology of a CMOS linear transconductor for low-voltage and low-power filters is proposed in this paper. It is applied to the analog baseband filter used in a transceiver designed for wireless sensor networks. The transconductor linearization scheme is based on regulating the drain voltage of triode-biased input transistors through an active-cascode loop. A third-order Butterworth low-pass filter implemented with this transconductor is integrated in a 0.18-/spl mu/m standard digital CMOS process. The filter can operate down to 1.2-V supply voltage with a cutoff frequency ranging from 15 to 85 kHz. The 1% total harmonic distortion dynamic range measured at 1.5 V for 20-kHz input signal and 50-kHz cutoff frequency is 75 dB, while dissipating 240 /spl mu/W.     

A time-interleaved continuous-time /spl Delta//spl Sigma/ modulator with 20-MHz signal bandwidth

This paper presents the first implementation results for a time-interleaved continuous-time /spl Delta//spl Sigma/ modulator. The derivation of the time-interleaved continuous-time /spl Delta//spl Sigma/ modulator from a discrete-time /spl Delta//spl Sigma/ modulator is presented. With various simplifications, the resulting modulator has only a single path of integrators, making it robust to DC offsets. A time-interleaved by 2 continuous-time third-order low-pass /spl Delta//spl Sigma/ modulator is designed in a 0.18-/spl mu/m CMOS technology with an oversampling ratio of 5 at sampling frequencies of 100 and 200 MHz. Experimental results show that a signal-to-noise-plus-distortion ratio (SNDR) of 57 dB and a dynamic range of 60 dB are obtained with an input bandwidth of 10 MHz, and an SNDR of 49 dB with a dynamic range of 55 dB is attained with an input bandwidth of 20 MHz. The power consumption is 101 and 103 mW, respectively.     

A single chip FSK modem

In the development of a fully LSI-designed single-chip 300-b/s asynchronous FSK modem, two `hard to beat' problems are: (1) to build both analog and digital circuits on-chip in-such a way that the modem performance is practically free from line noise and transmission distortion; and (2) to meet the requirement (CCITT V.21) of a +5 dBm level margin to discriminate carrier-on from carrier-off under the rigid operating conditions expected. It was found that a combination of high-gain limiter, digital PLL, and postdetection filter in the demodulator section was useful to solve the first problem. A combination of a stabilized rectifier and voltage reference generator contributed to the solution of the second problem. Measurements on chips indicated at /spl plusmn/12% isochronous distortion in the received signal level range of -5 to -45 dBm, a 10/SUP -5/ bit error rate at an SNR of 3 dB, and /spl plusmn/0.15 dB carrier detection level deviation over the temperature range from -20 to +100/spl deg/C within the supply voltage variations of /spl plusmn/10%. Switched-capacitor filters were used throughout the analog section. The device requires two power supplies, +12 and +5 V. The power consumption is 85 mW, and the chip size is 5.9/spl times/5.4 mm.     

A 1-V 10.7-MHz switched-opamp bandpass /spl Sigma//spl Delta/ modulator using double-sampling finite-gain-compensation technique

A 1 V switched-capacitor (SC) bandpass sigma-delta (/spl Sigma//spl Delta/) modulator is realized using a high-speed switched-opamp (SO) technique with a sampling frequency of up to 50 MHz, which is improved ten times more than prior 1 V SO designs and comparable to the performance of the state-of-the-art SC circuits that operate at much higher supply voltages. On the system level, a fast-settling double-sampling SC biquadratic filter architecture is proposed to achieve high-speed operation. A low-voltage double-sampling finite-gain-compensation technique is employed to realize a high-resolution /spl Sigma//spl Delta/ modulator using only low-DC-gain opamps to maximize the speed and to reduce power dissipation. On the circuit level, a fast-switching methodology is proposed for the design of the switchable opamps to achieve a switching frequency up to 50 MHz. Implemented in a 0.35-/spl mu/m CMOS process (V/sub TP/=0.82 V and V/sub TN/=0.65 V) and at 1 V supply, the modulator achieves a measured peak signal-to-noise-and-distortion ratio (SNDR) of 42.3 dB at 10.7 MHz with a signal bandwidth of 200 kHz, while dissipating 12 mW and occupying a chip area of 1.3 mm/sup 2/.     

Photonic RF phase shifter and tunable photonic RF notch filter

A new photonic RF phase shifter structure for phased array antennas is presented. It is based on a single dual-output modulator and two optical switches and optical attenuators. This can realize continuous phase shifting of 0/spl deg/-360/spl deg/ without altering the signal amplitude. It has the advantages of wide bandwidth, fast response time, and fine tuning resolution. Experimental results demonstrate phase shifts over a 360/spl deg/ phase range, with RF signal power changes of less than 0.2 dB, which is in close agreement with predictions. A tunable photonic RF notch filter, which is based on the new phase shifter, is also presented. Experimental results demonstrate continuous tuning of the photonic notch filter over a wide tuning range, which covers the full free spectral range, which is in good agreement with predictions.     

A 14-bit, 10-Msamples/s D/A converter using multibit /spl Sigma//spl Delta/ modulation

A 14-bit digital-to-analog converter based on a fourth-order multibit sigma-delta modulator is described. The digital modulator is pipelined to minimize both its power dissipation and design complexity. The 6-bit output of this modulator is converted to analog using 64 current-steering cells that are continuously calibrated to a reference current. This converter achieves 85-dB dynamic range at 5-MHz signal bandwidth, with an oversampling ratio of 12. The chip was fabricated in a 0.5-/spl mu/m CMOS technology and operates from a single 2.5-V supply.     

A high-performance,low-power ∑Δ ADC for digital audio applications

A high-performance low-power ∑Δ analog-to-digital converter (ADC) for digital audio applications is described.It consists of a 2-1 cascaded ∑Δ modulator and a decimation filter.Various design optimizations are implemented in the system design,circuit implementation and layout design,including a high-overload-level coefficientoptimized modulator architecture,a power-efficient class A/AB operational transconductance amplifier,as well as a multi-stage decimation filter conserving area and power consumption.The ADC is implemented in the SMIC 0.18-μm CMOS mixed-signal process.The experimental chip achieves a peak signal-to-noise-plus-distortion ratio of 90 dB and a dynamic range of 94 dB over 22.05-kHz audio band and occupies 2.1 mm2,which dissipates only 2.1 mA quiescent current in the analog circuits.     

An energy-efficient analog front-end circuit for a sub-1-V digital hearing aid chip

A low-power energy-efficient adaptive analog front-end circuit is proposed and implemented for digital hearing-aid applications. It adopts the combined-gain-control (CGC) technique for accurate preamplification and the adaptive-SNR (ASNR) technique to improve dynamic range with low power consumption. The CGC technique combines an automatic gain control and an exponential gain control together to reduce power dissipation and to control both gain and threshold knee voltage. The ASNR technique changes the value of the signal-to-noise ratio (SNR) in accordance with input amplitude in order to minimize power consumption and to optimize the SNR by sensing an input signal. The proposed analog front-end circuit achieves 86-dB peak SNR in the case of third-order /spl Sigma//spl Delta/ modulator with 3.8-/spl mu/Vrms of input-referred noise voltage. It dissipates a minimum and maximum power of 59.4 and 74.7 /spl mu/W, respectively, at a single 0.9-V supply. The core area is 0.5 mm/sup 2/ in a 0.25-/spl mu/m standard CMOS technology.