基于多级维纳滤波器的非均匀∑△-STAP研究

该文提出了基于多级维纳滤波器的非均匀∑△-STAP并行块处理算法,在非均匀环境下能快速有效检测动目标.文中基于多级维纳滤波的广义旁瓣对消器结构,提出了联合主波束检测和自适应功率剩余检测的两级级联非均匀检测算法,能有效增强对弱干扰目标样本的检测能力.同时,将改进的并行块处理引入非均匀∑△-STAP算法,极大地降低了系统运算量.理论分析和仿真实验表明,该算法能有效剔除干扰样本,提高动目标检测性能,收敛速度快,运算量小,鲁棒性强,易于工程实施.     

ΣΔ-STAP与ΣΔG-STAP抗有源干扰性能比较

在有源干扰下,机载脉冲多普勒雷达检测性能往往受到严重影响。文中提出了ΣΔ-STAP和ΣΔG-STAP抗有源干扰算法,通过仿真对ΣΔ-STAP和ΣΔG-STAP抗干扰性能进行了详细分析与比较。结果表明,ΣΔ-STAP只能对抗一个特定方向的副瓣干扰,而ΣΔG-STAP由于有两个空域自由度,能同时对抗两个干扰。由于运算量小,实现简单,具有较大的工程推广应用价值。     

弹载导引头雷达ΣΔ-STAP低秩矩阵恢复检测方法

当弹载导引头雷达检测运动目标时,由于海杂波谱严重扩展,和差波束空时自适应处理（ΣΔ-STAP）方法抑制海杂波能力非常有限,提出了一种基于低秩矩阵恢复的弹载导引头雷达ΣΔ-STAP方法。该方法基于低秩矩阵恢复理论建立弹载导引头雷达ΣΔ-STAP信号模型,首先采用ΣΔ-STAP方法预处理海杂波;然后利用鲁棒主成份分析（RPCA）技术从距离多普勒数据矩阵中分离出含有目标成分的稀疏矩阵;最后从距离多普勒谱图中有效地检测出运动目标。仿真实验验证了该方法在低信噪比情况下的有效性和鲁棒性。      

一种改进的机载雷达抗副瓣干扰方法

某机载雷达采用和差波束空时自适应处理(ΣΔ-STAP)方法能较好地对抗一个主瓣干扰和ΔA波束非零点副瓣干扰,但当干扰从ΔA波束副瓣零点方向进入时,主瓣分裂,对抗效果差。结合雷达实际特点,提出一种改进的ΣΔ-STAP方法,利用和、差和保护3个通道进行二维自适应处理。仿真结果表明,该方法能够很好对抗副瓣零点干扰,性能较以前ΣΔ-STAP方法有10 dB的改善,并且受幅相误差的影响变弱。     

基于幅相信息的和差波束非均匀检测器北大核心CSCD

由于现有的非均匀检测器(NHD)普遍存在运算量大、难以实时实现等问题,文中提出了一种基于幅相信息的和差波束非均匀检测器。该方法首先采用恒虚警技术(CFAR)检测出强目标和强杂波信号,然后剔除强目标并对强杂波信号进行加权处理,以改善距离样本的均匀性,最后利用常规自适应算法抑制杂波,完成对弱目标的检测。理论分析和对实测数据的处理表明,该检测器能有效地检测出动目标,提高输出信噪杂比,并具有运算量小,易于工程实现等优点。     

某机载雷达抗副瓣干扰的改进方法

某机载雷达采用的ΣΔ-STAP方法能较好地对抗一个主瓣干扰和ΔA波束非零点副瓣干扰,但当干扰从ΔA波束副瓣零点方向进入时,主瓣分裂,对抗效果差。结合雷达实际特点,本文提出一种改进的ΣΔ-STAP方法,方法利用和、差和保护三个通道进行二维自适应处理。仿真结果表明,该方法能够很好对抗副瓣零点干扰,并且误差稳定性增强。     

∑△-STAP与∑△G—STAP抗有源干扰性能比较

在有源干扰下，机载脉冲多普勒雷达检测性能往往受到严重影响。文中提出了∑△-STAP和∑△G-STAP抗有源干扰算法，通过仿真对∑△-STAP和∑△G-STAP抗干扰性能进行了详细分析与比较。结果表明，∑△-STAP号能翌誓二个特定方向的副瓣干扰，而∑△G-STAP由于有两个空域自由度，能同时对抗两个干扰。由于运算量小，实现简单，具有较大的工程推广应用价值。     

机载火控雷达杂波抑制研究

研究了和差空时自适应处理(∑△-STAP)在机载火控雷达中的应用,针对在实际处理中,由于地面杂波的非均匀性将严重影响∑△-3DT算法处理的效果,在此结合非均匀环境STAP处理,采用功率选择训练的非均匀处理方法,降低了STAP处理代价,实际处理结果显示,该处理显著提高杂波估计和抑制性能,较大提高了动目标的检测性能,文中还对目标径向速度的估计和方位定位问题进行研究,为该技术用于机载火控雷达地面动目标检测创造了条件。     

基于降维稀疏重构的高效数据域STAP算法研究

本文基于信号稀疏重构技术,研究利用待检测样本直接进行动目标检测的高效空时自适应处理（STAP ）方案。该方案对时域降维的阵元-多普勒域数据采用空域稀疏重构技术估计高分辨率角度-多普勒谱,进而基于稀疏空时谱研究知识辅助的动目标检测算法。理论分析和仿真实验结果表明：本文算法能有效抑制杂波实现慢动目标检测,且运算量小易于实时并行处理。     

数字电视外辐射源雷达目标徙动补偿新方法

增加相参积累时间是提高数字电视外辐射源雷达探测能力的一种较为常见的技术,但当目标速度和加速度较大时,长时间相参积累会使目标回波面临距离徙动和多普勒徙动,且当外辐射源雷达信号在慢时域为非均匀采样(如中国移动多媒体广播信号)时,广泛采用的如Keystone变换和Radon-Fourier变换等徙动补偿算法已不能很好地适用。该文研究了一种基于两次短傅里叶变换的徙动补偿算法,可同时适用于非均匀和均匀采样信号,并在此基础上提出一种修正算法,修正后的该算法能检测具有更大速度和加速度的目标,同时用于均匀采样时,相对已有一些算法其运算量更小。文中首先分析了非均匀采样信号的特殊性及该特殊性带来的新困难,接着基于该特殊信号的多普勒处理阐述了徙动机理与该徙动补偿算法的基本原理。仿真和实测数据处理证明了该算法的有效性。     

Triangularly weighted zero-crossing detector providingΣΔ frequency-to-digital conversion

It is shown that for delta-sigma (ΣΔ) frequency-to-digital conversion (FDC) there is no need for a ΣΔ modulator, since a limited FM signal itself may be considered as an asynchronous ΣΔ bit-stream. By feeding the limited FM signal directly to a sinc² ΣΔ decimator, a triangularly weighted zero-crossing counter FDC is introduced, providing ΣΔ noise shaping. The results measured confirm the theory     

Chopper stabilised ΠΔΣ analogue to digitalconversion

A chopper stabilised ΠΔΣ ADC architecture is proposed. A chopper stabilised version of ΠΔΣ ADC, which has identical performances to the regular ΠΔΣ ADC but is immune to low frequency noises such as DC offsets, can be obtained without adding hardware complexities     

A 14-bit current-mode ΣΔ DAC based upon rotated dataweighted averaging

A new dynamic element matching (DEM) algorithm, referred to as rotated data weighted averaging (RDWA), is implemented in a third-order ΣΔ digital-to-analog converter (DAC) with 64× oversampling and a conversion bandwidth of 25 kHz. The systematic and random errors are considered in the design of the 14-bit converter. The ΣΔ DAC is fabricated in a 2-μm CMOS process and includes the on-chip reconstruction filter. The prototype was designed to test the performance of the DAC without DEM, with data weighted averaging (DWA), and with RDWA. The results show that the new RDWA algorithm is capable of achieving first-order noise shaping while eliminating the signal-dependent harmonic distortion present in DWA     

A GMSK modulator using a ΔΣ frequencydiscriminator-based synthesizer

This paper describes a new transmitter architecture suitable for wideband GMSK modulation. The technique uses direct modulation of ΔΣ frequency discriminator (ΔΣFD)-based synthesizer to produce the modulated RF signal without any up-conversion. Digital equalization is used to extend the modulation data rate far beyond the synthesizer closed-loop BW. A prototype 1.9-GHz GSM transmitter was constructed consisting of a ΔΣFD-based synthesizer and a digital transmit filter. The synthesizer consists of an 0.8-μm BiCMOS ΔΣFD chip, a digital signal processor FPGA, and an off-chip D/A converter, filter, and VCO. Measured results, using 271-kbit/s GSM modulation, demonstrate data rates well in excess of the 30-kHz synthesizer closed-loop BW are possible with digital equalization. Without modulation, the synthesizer exhibits a -76-dBc spurious noise level and a close-in phase noise of -74 dBc/Hz     

Mismatch shaping for a current-mode multibit delta-sigma DAC

Mismatch shaping allows the use of multibit quantization in delta-sigma analog-to-digital converters and digital-to-analog converters (DAC's) since it noise-shapes the error caused by static element mismatch in a multibit DAC. In this paper, mismatch-shaping techniques for low-pass delta-sigma (ΔΣ) modulators are reviewed, and a mismatch-shaping technique for bandpass ΔΣ modulators is described. The dynamic error caused by frequent element switching is identified as a major source of error in a current-mode DAC with a continuous-time output. Modifying the mismatch-shaping algorithm to account for this effect yields a continuous-time ΔΣ DAC that is insensitive to both element mismatch and element switching dynamics. Experimental results confirm the effectiveness of the proposed techniques     

Design and realization of a digital ΔΣ modulator forfractional-n frequency synthesis

The basic operation of a fractional-n frequency synthesizer has been published, but to date little has been presented on the digital ΔΣ modulators which are required to drive such synthesizers. This paper provides a tutorial overview, which relates digital ΔΣ modulation to other applications of ΔΣ modulation where the literature is more complete. The paper then presents a digital ΔΣ modulator architecture which is economical and efficient and which is practical to realize with commercially available components in comparison with other possible implementations which require extensive custom very large-scale integration (VLSI). A demonstration is made of a 28-b modulator using the architecture presented, which provides a 25-MHz tuning bandwidth and <1-Hz frequency resolution. The modulator is demonstrated in an 800-MHz frequency synthesizer having phase noise of -90 dBC/Hz at a 30-kHz offset     

Reconstruction of oversampled band-limited signals fromΣΔ encoded binary sequences

Considers the application of ΣΔ modulators to analog-to-digital conversion. The authors have previously shown that for constant input signals, optimal nonlinear decoding can achieve large gains in signal-to-noise ratio (SNR) over linear decoding. The present paper shows a similar result for band-limited input signals. The new nonlinear decoding algorithm is based on projections onto convex sets (POCS), and alternates between a time-domain operation and a band limitation to find a signal invariant under both. The time-domain operation results in a quadratic programming problem. The band limitation can be based on singular value decomposition of a certain matrix. The authors show simulation results for the SNR performance of a POCS-based decoder and a linear decoder for the single loop, double loop and two-stage ΣΔ modulators and for a specific fourth-order interpolative modulator. Depending on the modulator and the oversampling ratio, improvements in SNR of up to 10-20 dB can be achieved     

CMOS oversampling ΔΣ magnetic-to-digital converters

In this paper, two CMOS oversampling delta-sigma (ΔΣ) magnetic-to-digital converters (MDCs) are proposed. The first MDC consists of the magnetic operational amplifier (MOP) and a first-order switched-capacitor (SC) ΔΣ modulator. The second one directly uses the MOP to realize a first-order SC ΔΣ modulator. They can convert the external magnetic field into digital form. Both circuits were fabricated in a 0.5-μm CMOS double-poly double-metal (DPDM) process and operated at a 5-V supply voltage and the nominal sampling rate of 2.5 MHz. The dynamic ranges of these converters are at least ±100 mT. The gain errors within ±100 mT are less than 3% and the minimum detectable magnetic field can reach as small as 1 mT. The resolutions are 100 μT for both of the two MDCs. The measured sensitivities are 1.327 mv/mT and 0.45 mv/mT for the first and the second MDC, respectively     

A switched-capacitor delta-sigma modulator with reduced sensitivityto op-amp gain

Low operational amplifier (op-amp) gain can degrade the performance of a switched-capacitor delta-sigma modulator (ΔΣM). A ΔΣM that incorporates a new gain-compensated switched-capacitor integrator is described. The resulting ΔΣM topology has reduced sensitivity to op-amp gain. Simulation and measurement results for an experimental ΔΣM that demonstrate the advantages of the new architecture are presented     

Quadrature bandpass ΔΣ modulation for digital radio

A quadrature bandpass ΔΣ modulator IC facilitates monolithic digital-radio-receiver design by allowing straightforward “complex A/D conversion” of an image reject mixer's I and Q, outputs. Quadrature bandpass ΔΣ modulators provide superior performance over pairs of real bandpass ΔΣ modulators in the conversion of complex input signals, using complex filtering embedded in ΔΣ loops to efficiently realize asymmetric noise-shaped spectra. The fourth-order prototype IC, clocked at 10 MHz, converts narrowband 3.75-MHz I and Q inputs and attains a dynamic range of 67 dB in 200-kHz (GSM) bandwidth, increasing to 71 and 77 dB in 100- and 30-kHz bandwidths, respectively. Maximum signal-to-noise plus distortion ratio (SNDR) in 200-kHz bandwidth is 62 dB. Power consumption is 130 mW at 5 V. Die size in a 0.8-μm CMOS process is 2.4×1.8 mm²