Hierarchical test generation for combinational circuits with real defects coverage

This paper deals with the automatic test pattern generation (ATPG) technique at the higher level using a functional fault model and defect-fault relationship in the form of a defect coverage table at the lower level. The paper contributes to test pattern generation (TPG) techniques taking into account physical defect localisation. A new parameter––probabilistic effectiveness of input patterns––has been used in the TPG technique with the goal of increasing real defect coverage. This parameter is based on probabilities of physical defects in digital cells which may occur in real integrated circuits. This improvement has been implemented into the existing DefGen ATPG system for combinational circuits.     

Oscillation-Test Technique for CMOS Operational Amplifiers by Monitoring Supply Current

A comparison of the merits and possibilities of considering the output voltage and the negative supply current as test observables when using the Oscillation-test technique is carried out. The method is applied to CMOS opamps considering an exhaustive analysis of catastrophic defects (opens, shorts), GOS and floating gates using HSPICE. We analyze deviations in both frequency and signal amplitude of each observable comparing their sensitivity to defects. Results show that the supply current peak value provides the highest defect coverage for a single opamp oscillator, while the oscillating frequency provides the highest fault coverage for a double opamp oscillator.     

Modeling of Physical Defects in PN Junction Based Graphene Devices

Graphene’s exceptional electro-mechanical properties make it a strong contender to replace silicon-based Complementary Metal-Oxide Semiconductor (CMOS) devices in the future. Among other novel material-based devices, graphene is pushing the research community to find new technological solutions that exploit its special characteristics. As it is a semimetal, the key challenge for graphene-based devices to be used in digital circuits is introducing band gap. Among the proposed approaches, electrostatic doping represents a key option. It allows the implementation of graphene pn junctions through which building a new class of reconfigurable logic gates is possible. This devices are analyzed in this work. Recent works presented a quantitative analysis of such gates in terms of area, delay and power consumptions, confirming their superiority w.r.t. CMOS technologies below the 22 nm. This paper explores another dimension, that is testability, and proposes a study of possible physical defects that might alter the functionality of the graphene logic gates. Two major kinds of manufacturing defects, which are possible in these gates, namely the S h o r t s between the device’s terminals and O p e n terminals, are considered. These faults have been injected into non faulty devices at the SPICE-level and the resulting behavior is mapped to appropriate fault model. Most of such models belong to the CMOS domain, but for some specific class of defects, new fault definitions are needed.     

Design for Test of Asynchronous NULL Convention Logic (NCL) Circuits

Due to the absence of a global clock and the presence of more state holding elements that synchronize the control and data paths, conventional Automatic Test Pattern Generation (ATPG) algorithms fail when applied to asynchronous circuits, leading to poor fault coverage. This paper presents a design for test (DFT) technique for a popular asynchronous design paradigm called NULL Convention Logic (NCL) aimed at making NCL designs testable using existing DFT tools with reasonable gate overhead. The proposed technique performs test points (TPs) insertion using Sandia Controllability and Observability Program (SCOAP) analysis to enhance the controllability of feedback nets and observability for fault sites that are flagged unobservable. An Automatic DFT Insertion Flow (ADIF) algorithm and a custom ATPG NCL primitive gates library are developed. The developed DFT technique has been verified on several NCL benchmark circuits

Design and Implementation of Cost-Effective Probabilistic-Based Noise-Tolerant VLSI Circuits

As the size of CMOS devices is scaled down to nanometers, noise can significantly affect circuit performance. Because noise is random and dynamic in nature, a probabilistic-based approach is better suited to handle these types of errors compared with conventional CMOS designs. In this paper, we propose a cost-effective probabilistic-based noise-tolerant circuit-design methodology. Our cost-effective method is based on master-and-slave Markov random field (MRF) mapping and master-and-slave MRF logic-gate construction. The resulting probabilistic-based MRF circuit trades hardware cost for circuit reliability. To demonstrate a noise-tolerant performance, an 8-bit MRF carry-lookahead adder (MRF_CLA) was implemented using the 0.13-${rm mu}hbox{m}$ CMOS process technology. The chip measurement results show that the proposed master-and-slave MRF_CLA can provide a $7.00times 10^{-5}$ bit-error rate (BER) under 10.6-dB signal-to-noise ratio, while the conventional CMOS_CLA can only provide $8.84times 10^{-3}$ BER. Because of high noise immunity, the master-and-slave MRF_CLA can operate under 0.25 V to tolerate noise interference with only 1.9 ${rm mu}hbox{W/MHz}$ of energy consumption. Moreover, the transistor count can be reduced by 42% as compared with the direct-mapping MRF_CLA design .      

Testability analysis and fault modeling of BiCMOS circuits

Defect models have been used for testability analysis of BiCMOS circuits and the results have been compared with an analysis of CMOS circuits. Using a nominal point approach, faults generated are classified as logical or performance degradation faults. It is found that logical fault testing can only cover a small percentage of the total fault set, 54% for BiCMOS, versus 69% for equivalent CMOS gates. Delay faults and current faults are analyzed as applied to BiCMOS and CMOS gates. It is shown that logical fault testing in conjunction with either delay fault testing or current fault testing promises the highest fault coverage for BiCMOS logic gates, around 95%.This research was partially supported by the Department of National Defence of Canada, Academic Research Program, grant # 3705-921.     

Detecting Multiple Faults in One-Dimensional Arrays of Reversible QCA Gates

Reversible logic design is a well-known paradigm in digital computation. In this paper, quantum-dot cellular automata (QCA) is investigated for testable implementations of reversible logic in array systems. Testability of 1D arrays consisting of reversible QCA gates is investigated for multiple faulty modules. It has been shown that fault masking is possible in the presence of multiple faults without additional lines for controllability and observability. A technique for achieving C-testability of a 1D array is introduced by adding lines for observability. By adding lines for controllability, as well as observability, the array may be fully tested with a smaller number of test patterns. Different cases of arrays made of QCA reversible gates are presented to illustrate the applicability of the proposed testing method.

Physical design of testable CMOS digital integrated circuits

A methodology for physical testability assessment and enhancement, implemented with a set of test tools, is presented. The methodology, which can improve the physical design of testable CMOS digital ICs, is supported in realistic fault-list generation and classification. Two measures of physical testability, weighted class fault coverage and fault incidence, and one measure of fault hardness are introduced. The testability is evaluated prior to fault simulation; difficult-to-detect faults are located on the layout and correlated with the physical defects which originate them; and suggestions for layout reconfiguration are provided. Several design examples are described, ascertaining the usefulness of the proposed methodology. The proposed methodology demonstrated that stuck-at test sets only partially cover the realistic faults in digital CMOS designs. Moreover, it is shown that classical fault models of arbitrary faults are insufficient to describe the realistic fault set. Simulation results have shown that the fault set strongly depends on the technology and on the layout style     

Quantum circuit’s reliability assessment with VHDL-based simulated fault injection

This paper presents a VHDL-based simulated fault injection (SFI) methodology for quantum circuits. The main objective is to attain a high error modeling capability at a technology independent level. For this purpose, gate level simulation models for quantum circuits have been developed using VHDL. The proposed methodology relies on specific techniques inspired from the simulated fault injection techniques developed for classical CMOS circuits: saboteurs and mutants. In order to perform the simulation campaigns, a library of quantum gates and simulated fault injection components has been developed. The simulation results show that a wide range of quantum faults and error models has been addressed. Furthermore, a comparison between the two SFI techniques is presented.     

基于NCV门的量子电路故障的检测与定位研究

为了确保基于NCV门库的量子电路的正确性和有效性,给出了量子电路故障定位树的生成算法和量子电路黑盒检测算法来定位量子电路中的门丢失故障。该故障定位树算法去除约98%的无用输出向量,提取输出表中有效的输入向量以及对应的故障输出向量,逐层生成故障定位树。结合量子电路黑盒检测算法对量子电路进行故障定位时不需要访问输出表就能够有效定位量子电路中的丢失门。对benchmarks部分电路进行实验,结果验证了该算法定位单故障门的有效性。     

Analysis of resistive bridging fault detection in BiCMOS digitalICs

This paper presents a study of the effects on the electrical behavior of BiCMOS digital circuits induced by bridging faults, whose resistance value is shown to have a strong impact on the static and dynamic behavior of faulty gates and of their fan-out gates. The problem of fault detection is addressed considering different testing techniques (current monitoring, functional, and delay testing). Electrical simulation has been used to investigate the main differences between BiCMOS and CMOS circuits. It is shown that, because of the large driving capability of BJTs, the detection of bridging faults in BiCMOS circuits is more difficult than in the CMOS case when functional or delay testing is used whereas it becomes more effective when adopting current monitoring     

Cell architecture for nanoelectronic design

Nanotechnology research has already proved and implemented several nanoscale devices. However, due to high defect ratios, large parameter variability and reduced noise margins, special architectures are needed to build reliable mid/large nanocircuits. Up to date several architectures have been proposed to design circuits in the nanoscale, but they do not consider the entire nanoscale environment. In this work, we propose and analyze a cell architecture based on the averaging of multiple nanodevices which is capable of alleviating the three main problems of the nanodevices at the gate level (internal noise, device parameter variation and defects). The proposed structure has a low implementation complexity which further reduces the fabrication defects. Using this cell architecture we present 2 and 3-input NAND gates showing their output response and error probabilities. Finally, we show that it is possible to improve the cell error tolerance by taking advantage of interferences among nanodevices which reduces the standard deviation by a factor larger than .     

Incorporating I DDQ Testing with BIST for Improved Coverage: An Experimental Study

In this paper we present an experimental study on the effectivenessof incorporating at-speed I _DDQ testing with traditionalBIST for improved test coverage. The high speed I _DDQtesting is conducted using the differential built-in on-chip current sensor(BICS) that we have recently developed. Two test chips were designed andfabricated implementing a CMOS version of the 74181 ALU chip. In copies ofthis circuit we included the capability of activating 45 differentrealistic CMOS faults: inter- and intra-layer shorts andopens. We examine the fault coverage of both Boolean (voltage) testing andI _DDQ testing for these realistic faults. An interestingfinding of our study is that I _DDQ testing also detectedseveral of the open faults. Moreover, these include precisely those openfaults for which two pattern voltage tests can get invalidated because oftransient switching states. Our results show that combining both Boolean andcurrent testing does enhance test coverage in a BIST environment.     

An Exact approach for Complete Test Set Generation of Toffoli-Fredkin-Peres based Reversible Circuits

Reversible logic has gained interest of researchers worldwide for its ultra-low power and high speed computing abilities in the future quantum information processing. Testing of these circuits is important for ensuring high reliability of their operation. In this work, we propose an ATPG algorithm for reversible circuits using an exact approach to generate CTS (Complete Test Set) which can detect single stuck-at faults, multiple stuck-at faults, repeated gate fault, partial and complete missing gate faults which are very useful logical fault models for reversible logic to model any physical defect. Proposed algorithm can be used to test a reversible circuit designed with k-CNOT, Peres and Fredkin gates. Through extensive experiments, we have validated our proposed algorithm for several benchmark circuits and other circuits with family of reversible gates. This algorithm produces a minimal and complete test set while reducing test generation time as compared to existing state-of-the-art algorithms. A testing tool is developed satisfying the purpose of generating all possible CTS’s indicating the simulation time, number of levels and gates in the circuit. This paper also contributes to the detection and removal of redundant faults for optimal test set generation.     

CMOS IC漏极静态电流测试技术的现状与发展

全面介绍了CMOS集成电路漏极静态电流(IDDQ)测试技术的现状、应用及其发展趋势。与其它主要用于检测逻辑功能的测试技术不同，IDDQ主要用于检测电路的物理缺陷和工艺故障。作为逻辑功能测试的重要补充，IDDQ技术可提高集成电路的可测性和故障覆盖率，保证集成电路的可靠性。     

A Single Clocked Adiabatic Static Logic—A Proposal for Digital Low Power Applications

A modified method to construct adiabatic logic is introduced. Advantages of this circuitry over most of the previous ones is that logic behaves in a static mode. In the present research the applicability of a one-phase power clock was studied. The functionality was guaranteed by having the power source frequency much higher than the logic frequency. The new logic gates do not differ much from any standard CMOS logic gates. The only difference is the use of diodes to form logical 1 and 0 states. The static nature of the introduced logic family makes possible to apply the charge recycling technic to other more complex digital circuits and systems. In measurements 77% power saving was achieved compared to a conventional CMOS logic.     

Fault models of CMOS circuits

A systematic procedure for fault modelling of CMOS circuits is described. It starts with the physical fault and produces a set of tables describing the logic behaviour of the gate. This set of tables is referred to as the fault model and includes truth tables, fault equivalence tables, fault coverage tables, and fault propagation tables. Starting with the procedure of fault modelling of simple combinational circuits, a method is advised for model generation of complex sequential structures. Application of fault modelling for yield evaluation and test pattern generation is considered, too.     

Transistor-level to gate-level comprehensive fault synthesis for n-input primitive gates

In order to have a high level of confidence in system testing, more accurate fault models are needed. An accurate fault model cannot be attained unless all faults in the transistor-level (low level) are considered. However, these transistor-level faults must be mapped onto gate-level (higher level) so that the efficiency of fault simulation, fault emulation and test pattern generation at the gate-level is not sacrificed. This paper covers the static and dynamic single physical failures at transistor-level for static CMOS primitive gates and shows their effects in the output behavior in terms of gate-level faults. A specific fault pattern is proposed and a general formula to calculate the total number of static faults is concluded from these patterns for each type of gate regardless of its number of inputs. The dynamic nature of the physical faults included in the static fault list is evaluated and their cumulative effect on the timing at the circuit output is examined. A general formula for calculating propagation delay at the output due to resistive shorts and opens is derived and a delay fault pattern with variable defect resistance is provided.     

Technology mapping for high-performance static CMOS and passtransistor logic designs

Two new techniques for mapping circuits are proposed in this paper. The first method, called the odd-level transistor replacement (OTR) method, has a goal that is similar to that of technology mapping, but without the restriction of a fixed library size and maps a circuit to a virtual library of complex static CMOS gates. The second technique, the static CMOS/pass transistor logic (PTL) method, uses a mix of static CMOS and PTL to realize the circuit and utilizes the relation between PTL and binary decision diagrams. The methods are very efficient and can handle all of the ISCAS'85 benchmark circuits in minutes. A comparison of the results with traditional technology mapping using SIS on different libraries shows an average delay reduction above 18% for OTR, and an average delay reduction above 35% for the static CMOS/PTL method, with significant savings in the area     

Improving Power-Delay Performance of Ultra-Low-Power Subthreshold SCL Circuits

This brief presents a technique for improving the power-delay performance of subthreshold source-coupled logic (SCL) circuits. Based on the proposed approach, a source-follower buffer stage is used at the output of each SCL stage. Analytical results confirmed by measurements in 0.18-$muhbox{m}$ CMOS technology show an improvement by a factor of as high as 2.4 in power-delay product (PDP). It is also shown that the proposed technique can be used for implementing subthreshold ultra-low power SCL logic gates with a better power and area efficiency, compared to the traditional SCL subthreshold circuits. An optimized approach is proposed to improve the power efficiency of ultra-low power STSCL library cells.