应用于片上ESD防护中新式直通型MOS触发SCR器件的研究

在基于0.13μm CMOS工艺制程下,为研究片上集成电路ESD保护,对新式直通型MOS触发SCR器件和传统非直通型MOS触发SCR进行了流片验证,并对该结构各类特性进行了具体研究分析。实验采用TLP(传输线脉冲)对两类器件进行测试验证,发现新式直通型MOS触发SCR结构要比传统非直通型MOS触发SCR具有更低的触发电压、更小的导通电阻、更好的开启效率以及更高的失效电流。     

0.18μm RF CMOS双向可控硅ESD防护器件的研究(英文)

基于传统双向可控硅(DDSCR)提出了两种静电放电(ESD)保护器件,可应对正、负ESD应力从而在2个方向上对电路进行保护。传统的DDSCR通过N-well与P-well之间的雪崩击穿来触发,而提出的新器件则通过嵌入的NMOS/PMOS来改变触发机制、降低触发电压。两种改进结构均在0.18μmRFCMOS下进行流片,并使用传输线脉冲测试系统进行测试。实验数据表明,这两种新器件具有低触发电压、低漏电流(～nA),抗ESD能力均超过人体模型2kV,同时具有较高的维持电压(均超过3.3V),可保证其可靠地用于1.8V、3.3V I/O端口而避免出现闩锁问题。     

Design of SCR‐Based ESD Protection Circuit for 3.3 V I/O and 20 V Power Clamp

In this paper, MOS‐triggered silicon‐controlled rectifier (SCR)–based electrostatic discharge (ESD) protection circuits for mobile application in 3.3 V I/O and SCR‐based ESD protection circuits with floating diffusion regions for inverter and light‐emitting diode driver applications in 20 V power clamps were designed. The breakdown voltage is induced by a grounded‐gate NMOS (ggNMOS) in the MOS‐triggered SCR‐based ESD protection circuit for 3.3 V I/O. This lowers the breakdown voltage of the SCR by providing a trigger current to the P‐well of the SCR. However, the operation resistance is increased compared to SCR, because additional diffusion regions increase the overall resistance of the protection circuit. To overcome this problem, the number of ggNMOS fingers was increased. The ESD protection circuit for the power clamp application at 20 V had a breakdown voltage of 23 V; the product of a high holding voltage by the floating diffusion region. The trigger voltage was improved by the partial insertion of a P‐body to narrow the gap between the trigger and holding voltages. The ESD protection circuits for low‐ and high‐voltage applications were designed using 0.18 µm Bipolar‐CMOS‐DMOS technology, with 100 µm width. Electrical characteristics and robustness are analyzed by a transmission line pulse measurement and an ESD pulse generator (ESS‐6008).     

一种新型的高维持电压可控硅

可控硅(SCR)作为静电放电(ESD)保护器件,因具有高的鲁棒性而被广泛应用,但其维持电压很低,容易导致闩锁问题。针对高压集成电路的ESD保护,提出了一种新颖的具有高维持电压的SCR结构(HHVSCR)。通过添加一个重掺杂的N型掺杂层(NIL),减小了SCR器件自身固有的正反馈效应,从而提高了SCR的维持电压。Sentaurus TCAD仿真结果表明,与传统的SCR相比,改进的HHVSCR无需增加额外的面积就可将维持电压从1.88 V提高到11.9 V,可应用于高压集成电路的ESD防护。     

Holding voltage investigation of advanced SCR-based protection structures for CMOS technology

A new silicon-controlled rectifier low voltage triggered (SCR-LVT), to be adopted as protection structure against electrostatic discharge (ESD) events, has been developed and characterized. A high holding voltage has been obtained thanks to the insertion of two parasitic bipolar transistors, achieved adding a n-buried region to a conventional SCR structure. These two parasitic transistors partially destroy the loop feedback gain of the two main npn and pnp BJTs, resulting in an increase of the sustaining (holding) voltage during the ESD event. A strong dependence of the holding voltage with the ESD pulse width has also been observed, caused by self-heating effects. 2D-device simulations (DESSIS Synopsys) have been performed obtaining results that perfectly fit the measurements over a wide temperature range (25 °C − 125 °C). Using device simulation results, the factors that influence the holding voltage, in terms of temperature dependence, but also in the behavior of the parasitic BJTs, are explained. A guideline to change the SCR holding voltage, related to the SCR design layout without any change to process parameters, is also proposed.     

TLP和VFTLP应力下高压LDMOS的触发特性研究

本文通过TCAD软件－Sentaurus Device工具, 基于文献[1]所提出的一套物理宏模型进行仿真,研究了高压LDMOS功率器件（击穿电压大于160伏）在传输线脉冲和快速传输线脉冲应力下的静电放电（ESD）触发物理机制,发现在快速传输线脉冲应力下,高压LDMOS的触发电压有明显的提高,这一现象和低压普通静电放电保护器件（如NMOS器件和SCR器件）有明显的差异。本文详细分析了触发电压的上升现象和寄生电容的关系,并且用一个简单的等效电路原理图分析了上述现象。最后,本文提出了一种能够减轻触发电压上升这一现象的改进结构,并且得到了测试结果的验证。     

Design of SCR-based ESD protection device for power clamp using deep-submicron CMOS technology

The proposed device has a high holding voltage and a high triggering current characteristic. These characteristics enable latch-up immune normal operation as well as superior full chip electro-static-discharge (ESD) protection. The device has a small area in requirement robustness in comparison to gate-grounded NMOS (ggNMOS). The proposed ESD protection device is designed in 0.25 μm CMOS technology. In the experimental result, the proposed ESD clamp has a double trigger characteristic, a high holding voltage of 3.8 V and a high trigger current of greater than 120 mA. The robustness has measured to HBM 8 kV (HBM: human body model) and MM 400 V (MM: machine model). The proposed device has a high-level It2 of 52 mA/μm approximately.     

Complementary-SCR ESD protection circuit with interdigitatedfinger-type layout for input pads of submicron CMOS IC's

A new ESD protection circuit with complementary SCR structures and junction diodes is proposed. This complementary-SCR ESD protection circuit with interdigitated finger-type layout has been successfully fabricated and verified in a 0.6 μm CMOS SRAM technology with the LDD process. The proposed ESD protection circuit can be free of VDD-to-VSS latchup under 5 V VDD operation by means of a base-emitter shorting method. To compensate for the degradation on latching capability of lateral SCR devices in the ESD protection circuit caused by the base-emitter shorting method, the p-well to p-well spacing of lateral BJT's in the lateral SCR devices is reduced to lower its ESD-trigger voltage and to enhance turn-on speed of positive-feedback regeneration in the lateral SCR devices. This ESD protection circuit can perform at high ESD failure threshold in small layout areas, so it is very suitable for submicron CMOS VLSI/ULSI's in high-pin-count or high-density applications     

Implementation of Initial-On ESD Protection Concept With PMOS-Triggered SCR Devices in Deep-Submicron CMOS Technology

In order to enhance the applications of SCR devices for deep-submicron CMOS technology, a novel SCR design with "initial-on" function is proposed to achieve the lowest trigger voltage and the highest turn-on efficiency of SCR device for effective on-chip ESD protection. Without using the special native device (NMOS with almost zero or even negative threshold voltage) or any process modification, this initial-on SCR design is implemented by PMOS-triggered SCR device, which can be realized in general CMOS processes. This initial-on SCR design has a high enough holding voltage to avoid latchup issues in a VDD operation voltage of 2.5 V. The new proposed initial-on ESD protection design with PMOS-triggered SCR device has been successfully verified in a fully-silicided 0.25-mum CMOS process     

Stacked zener trigger SCR for HV IC ESD protection

In HV BCD technology, SCR cannot been directly used as ESD protection owing to its high trigger voltage and low holding voltage. Stacked zener trigger SCRs for HV ESD protection is proposed and Compared to the traditional SCR. The proposed devices are fabricated with 0.35 um BCD process on P-type bulk wafers without buried layer. TLP testing results show that the single zener trigger SCR with 50 um width has a 6.7 V trigger voltage and 4.1 A failure current It2. Stacked 4 zener trigger SCRs is designed for 24 V I/O ESD protection, which has 8 V holding voltage, 27 V trigger voltage and pass7 KV HBM.     

On a dual-polarity on-chip electrostatic discharge protectionstructure

A novel dual-polarity on-chip electrostatic discharge (ESD) protection structure is designed. The new ESD structure protects IC chips against ESD stressing in the two opposite directions. The ESD structure features symmetric deep-snapback current-voltage (I-V) characteristics, low-impedance active overcurrent discharging path, low holding voltage for overvoltage clamping, fast ESD response of ~0.18 ns, low leakage (~pA), adjustable triggering voltage, and good scalability. It passes 14 KV HBM ESD zapping tests and achieves high ESD-performance-to-Si ratio of ~80 V/μm width. The new ESD structure reduces Si areas consumed by ESD protection units and ESD-induced parasitic effects significantly     

Design of fabrication of ESD protection circuit with high holding voltage for power IC

In this paper, A newly Silicon Controlled Rectifier (SCR)-based Electric Static Discharge (ESD) protection circuit is proposed. The proposed circuit has the latch-up immunity in normal operating conditions with the high holding voltage by inserting the floating regions. To verify the electrical characteristics, a Technology Computer Aided Design (TCAD) simulation is performed by setting each of variables: D1, D2, D3, and D4. The results of the simulation show that the proposed protection circuit has the holding voltage 5 V higher than the conventional circuits and has the same level of robustness properties as the existing SCR. In addition, the proposed circuit is fabricated through a 0.18 μm Bipolar-CMOS-DMOS process. The electrical characteristics are confirmed by measuring Transmission Line Pulse, and the robustness properties are measured through Human Body Model (HBM) and Machine Model (MM). The holding voltage is about 20 V, which has the increases above 18 V or more compared to the conventional SCR. Therefore, the proposed circuit is proved to have the better ESD protection performance than HBM 8 kV and MM 800 V higher than HBM 2 kV and MM 200 V, the commercial standard.     

Analysis of a Parasitic‐Diode‐Triggered Electrostatic Discharge Protection Circuit for 12 V Applications

In this paper, an electrostatic discharge (ESD) protection circuit is designed for use as a 12 V power clamp by using a parasitic‐diode‐triggered silicon controlled rectifier. The breakdown voltage and trigger voltage (V_t) of the proposed ESD protection circuit are improved by varying the length between the n‐well and the p‐well, and by adding n+/p+ floating regions. Moreover, the holding voltage (V_h) is improved by using segmented technology. The proposed circuit was fabricated using a 0.18‐μm bipolar‐CMOS‐DMOS process with a width of 100 μm. The electrical characteristics and robustness of the proposed ESD circuit were analyzed using transmission line pulse measurements and an ESD pulse generator. The electrical characteristics of the proposed circuit were also analyzed at high temperature (300 K to 500 K) to verify thermal performance. After optimization, the V_t of the proposed circuit increased from 14 V to 27.8 V, and V_h increased from 5.3 V to 13.6 V. The proposed circuit exhibited good robustness characteristics, enduring human‐body‐model surges at 7.4 kV and machine‐model surges at 450 V.     

Highly Robust AHHVSCR‐Based ESD Protection Circuit

In this paper, a new structure for an advanced high holding voltage silicon controlled rectifier (AHHVSCR) is proposed. The proposed new structure specifically for an AHHVSCR‐based electrostatic discharge (ESD) protection circuit can protect integrated circuits from ESD stress. The new structure involves the insertion of a PMOS into an AHHVSCR so as to prevent a state of latch‐up from occurring due to a low holding voltage. We use a TACD simulation to conduct a comparative analysis of three types of circuit — (i) an AHHVSCR‐based ESD protection circuit having the proposed new structure (that is, a PMOS inserted into the AHHVSCR), (ii) a standard AHHVSCR‐based ESD protection circuit, and (iii) a standard HHVSCR‐based ESD protection circuit. A circuit having the proposed new structure is fabricated using 0.18 μm Bipolar‐CMOS–DMOS technology. The fabricated circuit is also evaluated using Transmission‐Line Pulse measurements to confirm its electrical characteristics, and human‐body model and machine model tests are used to confirm its robustness. The fabricated circuit has a holding voltage of 18.78 V and a second breakdown current of more than 8 A.     

Design and integration of novel SCR-based devices for ESD protection in CMOS/BiCMOS technologies

Robust and novel devices called high-holding low-voltage trigger silicon controlled rectifiers (HH-LVTSCRs) for electrostatic discharge (ESD) protection of integrated circuits (ICs) are designed, fabricated and characterized. The S-type current-voltage (I-V) characteristics of the HH-LVTSCRs are adjustable to different operating conditions by changing the device dimensions and terminal interconnections. Comparison between complementary n- and p-type HH-LVTSCR devices shows that n-type devices perform better than p-type devices when a low holding voltage (V/sub H/) is allowed during the on-state of the ESD protection structure, but when a relatively high holding voltage is required, p-type devices perform better. Results further demonstrate that HH-LVTSCRs with a multiple-finger layout render high levels of ESD protection per unit area, applicable in the design of ICs with stringent ESD protection requirements of over 15 kV IEC.     

Electrostatic discharge (ESD) protection for CMOS output buffers in scaled-down VLSI technology

To provide area-efficient output ESD protection for the scaled-down CMOS VLSI, a new output ESD protection is proposed. In the new output ESD protection circuit, there are two novel devices, the PTLSCR (PMOS-trigger lateral SCR) and the NTLSCR (NMOS-trigger lateral SCR). The PTLSCR is in parallel and merged with the output PMOS, and the NTLSCR is in parallel and merged with the output NMOS, to provide area-efficient ESD protection for CMOS output buffers. The trigger voltages of PTLSCR and NTLSCR are lowered below the breakdown voltages of the output PMOS and NMOS in the CMOS output buffer. The PTLSCR and NTLSCR are guaranteed to be turned on first before the output PMOS or NMOS are broken down by the ESD voltage. Experimental results have shown that the PTLSCR and NTLSCR can sustain over 4000 V (700 V) of the human-body-model (machine-model) ESD stresses within a very small layout area in a 0.6 μm CMOS technology with LDD and polycide processes. The noise margin of the proposed output ESD protection design is greater than 8 V (lower than −3.3 V) to avoid the undesired triggering on the NTLSCR (PTLSCR) due to the overshooting (undershooting) voltage pulse on the output pad when the IC is under normal operating conditions with 5 V VDD and 0 V VSS power supplies.     

Design of Gate‐Ground‐NMOS‐Based ESD Protection Circuits with Low Trigger Voltage,Low Leakage Current,and Fast Turn‐On

In this paper, electrostatic discharge (ESD) protection circuits with an advanced substrate‐triggered NMOS and a gate‐substrate‐triggered NMOS are proposed to provide low trigger voltage, low leakage current, and fast turn‐on speed. The proposed ESD protection devices are designed using 0.13 μm CMOS technology. The experimental results show that the proposed substrate‐triggered NMOS using a bipolar transistor has a low trigger voltage of 5.98 V and a fast turn‐on time of 37 ns. The proposed gate‐substrate‐triggered NMOS has a lower trigger voltage of 5.35 V and low leakage current of 80 pA.     

A double RESURF LDMOS with drain profile engineering for improvedESD robustness

This letter reports a novel 50 V lateral power MOSFET structure that is self-protecting with respect to electrostatic discharge (ESD) strikes. This device features a double RESURF technique in conjunction with a deep drain engineered profile that eliminates soft leakage degradation after snapback, thus demonstrating immunity to filamentation. Maximum second breakdown current (I_t2) of 16 mA/μm has been realized in a 100 ns transmission line pulse (TLP) measurement even with a higher holding voltage of 20 V. ESD protection level in excess of 5 kV with an equivalent human body model (HBM) has been shown to be feasible for this device without significant compromise in device size     

基于人体起电实验外推超低电压研究

随着电子工业技术的飞速发展,电子产品静电放电(electrostatic discharge,ESD)敏感度电压已经低于人体模型(human body model,HBM)电压50 V,然而现有防静电工作区(electrostatic discharge protected area,EPA)配置要求标准只是针对于ES...     

纵向NPN管ESD保护结构的设计与分析

针对一种5V0.6μm BiCMOS工艺的纵向NPN管,设计了ESD保护结构。为了克服传统纵向NPN管ESD自触发结构触发电压较高的缺陷,提出一种带P+/N阱二极管的改进型自触发ESD结构,利用NPN管集电极与基极之间的寄生电容和二极管作为电容耦合元件。流片及测试结果表明,该保护结构的触发电压得到有效降低,且抗ESD能力超过4kV的人体模型。