粗糙界面对超薄栅MOS结构的直接隧穿电流的影响

研究了粗糙界面对电子隧穿超薄栅金属 -氧化物 -半导体场效应晶体管的氧化层的影响 .对于栅厚为 3nm的超薄栅 MOS结构的界面用高斯粗糙面进行模拟来获取界面粗糙度对直接隧穿电流的影响 ,数值模拟的结果表明 :界面粗糙度对电子的直接隧穿有较大的影响 ,且直接隧穿电流随界面的粗糙度增加而增大 ,界面粗糙度对电子的直接隧穿的影响随着外加电压的增加而减小 .     

Oxide roughness effect on tunneling current of MOS diodes

Two-dimensional (2-D) device simulation is used to investigate the tunneling current of metal ultra-thin-oxide silicon tunneling diodes with different oxide roughness. With the conformal nature of ultrathin oxide, the tunneling current density is simulated in both direct tunneling and Fowler-Nordheim (FN) tunneling regimes with different oxide roughness. The results show that oxide roughness dramatically enhances the tunneling current density and the 2-D electrical effect is responsible for this increment of tunneling current density. Furthermore, a set of devices with controlled oxide roughness is fabricated to verify the simulation results and our model qualitatively agrees with the experiment results.     

Tunneling into interface states as reliability monitor for ultrathin oxides

This paper reports experimental data and simulations of low-voltage tunneling in ultrathin oxide MOS devices. When the substrate is very heavily doped, a thermionic barrier is present that opposes the direct tunneling of gate electrons when the applied gate voltage is between 0 V and the flatband voltage. In such conditions, we show that the measured gate current cannot be explained by direct tunneling, but features an additional, dominant component. The temperature dependence of this extra component indicates that it is due to gate electrons tunneling into the anode interface states. By comparing measurements and simulations, it is possible to exploit this extra current to estimate the interface state density within the silicon band gap. In addition, it is shown that this tunneling current component is very sensitive to electrical stress and allows a clear detection of oxide wear out even for stress at very low field. Therefore, it can be adopted as monitor of oxide degradation in ultrathin oxides where the traditional stress induced leakage current due to bulk-oxide traps is not detectable.     

超薄栅MOS结构恒压应力下的直接隧穿弛豫谱

随着器件尺寸的迅速减小 ,直接隧穿电流将代替 FN电流而成为影响器件可靠性的主要因素 .根据比例差值算符理论和弛豫谱技术 ,针对直接隧穿应力下超薄栅 MOS结构提出了一种新的弛豫谱——恒压应力下的直接隧穿弛豫谱 (DTRS) .该弛豫谱保持了原有弛豫谱技术直接、快速和方便的优点 ,能够分离和表征超薄栅 MOS结构不同氧化层陷阱 ,提取氧化层陷阱的产生 /俘获截面、陷阱密度等陷阱参数 .直接隧穿弛豫谱主要用于研究直接隧穿注入的情况下超薄栅 MOS结构中陷阱的产生和复合 ,为超薄栅 MOS结构的可靠性研究提供了一强有力工具 .     

On the tunneling component of charge pumping current in ultrathingate oxide MOSFETs

A simple method is described for separating the charge pumping current from the parasitic tunneling component in a charge pumping measurement performed on MOS transistors with ultrathin (<2 nm) gate oxide thickness. The method is presented here for a two-level charge pumping signal and can be used to significantly increase the accuracy of the technique to extract interface trap parameters in tunnel MOS devices     

超薄氧化层中的中性陷阱对隧穿电流的影响和应变诱导漏电流

用数值分析的方法讨论了中性陷阱对超薄场效应晶体管(MOSFET )隧穿电流的影响.中性陷阱引起势垒的变化在二氧化硅的导带中形成一个方形的势阱.对于不同的势垒变化,计算了电子隧穿氧化层厚度为4nm的超薄金属氧化物半导体结构的电流.结果表明,中性陷阱对隧穿电流的影响不能被忽略,中性陷阱的存在使隧穿电流增加,并且通过这个简单的模型能够理解应变诱导漏电流的产生机制.     

超薄氧化层中的中性陷阱对隧穿电流的影响和应变诱导漏电流

用数值分析的方法讨论了中性陷阱对超薄场效应晶体管(MOSFET )隧穿电流的影响.中性陷阱引起势垒的变化在二氧化硅的导带中形成一个方形的势阱.对于不同的势垒变化,计算了电子隧穿氧化层厚度为4nm的超薄金属氧化物半导体结构的电流.结果表明,中性陷阱对隧穿电流的影响不能被忽略,中性陷阱的存在使隧穿电流增加,并且通过这个简单的模型能够理解应变诱导漏电流的产生机制.     

Impact of gate direct tunneling current on circuit performance: asimulation study

The influence of gate direct tunneling current on ultrathin gate oxide MOS (1.1 nm⩽t_ox⩽1.5 nm, L_g=50-70 nm) circuits has been studied based on detailed simulations. For the gate oxide thickness down to 1.1 nm, gate direct tunneling currents, including the edge direct tunneling (EDT), show only a minor impact on low V_dd static-logic circuits. However, dynamic logic and analog circuits are more significantly influenced by the off-state leakage current for oxide thickness below 1.5 nm, under low-voltage operation. Based on the study, the oxide thicknesses which ensure the International Technological Roadmap for Semiconductors (ITRS) gate leakage limit are outlined both for high-performance and low-power devices     

The effect of transition region on the direct tunneling current and Fowler–Nordheim tunneling current oscillations in ultrathin MOS structures

The effects of transition region on direct tunneling and Fowler–Nordheim (FN) tunneling in ultrathin metal–oxide–semiconductor field transistors are investigated by numerical analysis. Direct tunneling current in ultrathin gate oxide is shown to increase with the width of transition region. The applied voltage across the oxide at the maximum and minimum of FN tunneling current oscillations is observed to increase with the width of the transition region, and its relative increase also strongly depends on the width. Furthermore, the amplitude of FN tunneling current oscillations descends with the width of transition region, however, its attenuation factor trends to increase with the width. Usually the amplitude and its attenuation factor decrease with the ordinal number of current oscillation increasing. So the effect of the transition region on FN tunneling current oscillations may be used to extract the information about the transition region.     

Potentials and direct current in Si-(20 to 40 Å)SiO2-metal structures

The effects of oxide thickness and interface states on potentials in and direct currents through MOS structures with various metal contacts on 20–40 Å thick SiO₂ films and nondegenerate Si were investigated using a recently developed method of determining surface potential vs. bias and interface state vs. energy distributions of such structures from conventional admittance measurements. For Cr, Cu, and Mg contacts, the interface states are predominantly of acceptor type. The metal silicon work function differences are φ_MS = 0.91 V for Au, −0.04 for Cr, 0.18 for Cu, and −1.07 V for Mg. The forward device current consists mainly of majority carriers emitted over the Si barrier and tunneling through the oxide into the metal for depletion or weak inversion of Si, and of majority carriers tunneling from Si through the oxide into the metal for Si accumulation. Excess currents in forward and reverse direction are caused by carrier generation-recombination in interface states and tunneling through the oxide to and from the metal. The drooping of the forward current, deviating strongly from an ideal exponential characteristic, is mainly caused by the drop of a considerable part of the applied bias across the oxide layer.     

Tunneling leakage current in ultrathin (<4 nm) nitride/oxidestack dielectrics

The leakage current in high-quality ultrathin silicon nitride/oxide (N/O) stack dielectric is calculated based on a model of one-step electron tunneling through both the nitride and the oxide layers. The results show that the tunneling leakage current in the N/O stack is substantially lower than that in the oxide layer of the same equivalent oxide thickness (EOT). The theoretical leakage current in N/O stack has been found to be a strong function of the nitride/oxide EOT ratio: in the direct tunneling regime, the leakage current decreases monotonically as the M/O ratio increases, while in the Fowler-Nordheim regime the lowest leakage current is realized with a N/O EOT ratio of 1:1. Due to the asymmetry of the N/O barrier shape, the leakage current under substrate injection is higher than that under gate injection, although such a difference becomes smaller in the lower voltage regime. Experimental data obtained from high quality ultrathin N/O stack dielectrics agree well with calculated results     

A study of the effects of tunneling currents and reliability of sub-2 nm gate oxides on scaled n-MOSFETs

This work examined various components of direct gate tunneling currents and analyzed reliability of ultrathin gate oxides (1.4–2 nm) in scaled n-metal-oxide-semiconductor field effective transistor (MOSFETs). Direct gate tunneling current components were studied both experimentally and theoretically. In addition to gate tunneling currents, oxide reliability was investigated as well. Constant voltage stressing was applied to the gate oxides. The oxide breakdown behaviors were observed and their effects on device performance were studied. The ultrathin oxides in scaled n-MOSFETs used in this study showed distinct breakdown behavior and strong location dependence. No “soft” breakdown was seen for 1.5 nm oxide with small area, implying the importance of using small and more realistic MOS devices for ultrathin oxide reliability study instead of using large area devices. Higher frequency of oxide breakdowns in the source/drain extension to the gate overlap region was then observed in the channel region. Possible explanations to the observed breakdown behaviors were proposed based on the quantum mechanical effects and point-contact model for electron conduction in the oxide during the breakdown. It was concluded that the source/drain extension to the gate overlap regions have strong effects on the device performance in terms of both gate tunneling currents and oxide reliability.     

Tunneling leakage current in oxynitride: dependence onoxygen/nitrogen content

It is widely known that the addition of nitrogen in silicon oxide, or the addition of oxygen in silicon nitride, affects its reliability as a gate dielectric. The authors examine the gate leakage current as a function of the oxygen and nitrogen contents in ultrathin silicon oxynitride films on Si substrates. It is shown that, provided that electron tunneling is the dominant current conduction mechanism, the gate leakage current in the direct tunneling regime increases monotonically with the oxygen content for a given equivalent oxide thickness (EOT), such that pure silicon nitride passes the least amount of current while pure silicon oxide is the leakiest     

Observation of near-interface oxide traps with the charge-pumpingtechnique

In studies of MOS devices with the charge pumping technique, the authors have encountered a low-frequency increase in the charge recombined per cycle, which they attribute to the charging and discharging of traps located within a tunneling distance of the Si-SiO ₂ interface, i.e., near-interface oxide traps. MOS devices subjected to ionizing radiation as well as ultrathin tunnel oxide polysilicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory devices possess a high density of near-interface oxide traps. When the charge recombined per cycle is examined as a function of frequency, a breakpoint is observed at a particular frequency with an inverse equivalent to a trap-to-trap tunneling time constant     

Tunneling component suppression in charge pumping measurement and reliability study for high-k gated MOSFETs

Although charge pumping (CP) is a powerful technique to measure the energy and spatial distributions of interface trap and oxide trap in MOS devices, the parasitic gate leakage current in it is the bottleneck. A CP method was modified and applied to high-k gate dielectric in this work to separate the CP current from the parasitic tunneling component in MOS devices. The stress-induced variations of electrical parameters in high-k gated MOS devices were investigated and the physical mechanism was studied by the modified CP technique. The stress-induced trap generation for devices with HfO₂-dominated high-k gate dielectrics is like mobile defect; while that with SiO₂-dominated ones is similar to the near-interface/border trap.     

SiSiO2 interface state spectroscopy using MOS tunneling structures

This paper provides a critical review and classification of the studies of SiSiO₂ interface state parameters and energy distributions by means of MOS tunneling in structures with ultrathin SiO₂ layers (10–100 Å). Suggestions are made of experiments that will help to elucidate the importance of materials and processing conditions on these states, and to separate the various mechanisms involving charge exchange with the metal, the conduction band, and the valence band of the semiconductor.     

Reduction of carrier depletion in p/sup +/ polysilicon gates using laser thermal processing

A novel laser thermal processing (LTP) technique was used to fabricate p/sup +/-gated MOS capacitors with ultrathin gate oxides. It is found that the introduction of LTP prior to the gate activation anneal increases the carrier concentration at the poly-Si gate/gate oxide interface substantially, as compared to rapid thermal anneal (RTA) alone. Thus, LTP readily reduces the poly-depletion effect in p/sup +/-poly-Si gates. This is achieved without observable gate oxide degradation or boron penetration. Secondary ion mass spectrometry analyzes show that the boron concentration near the gate/gate oxide interface increases significantly after the post-LTP anneal. A possible mechanism for this increase in carrier concentration is the diffusion of boron atoms toward the gate oxide by a complex process known as explosive crystallization.     

Extraction of Si-SiO/sub 2/ interface trap densities in MOS structures with ultrathin oxides

Si-SiO/sub 2/ interface trap densities can be measured in MOS structures with ultrathin oxides using charge pumping (CP) and small gate pulses. This presents three decisive advantages with respect to the conventional large gate voltage swing approach. First, the extraction is simple as carrier emission does not contribute to the CP signal so that the CP current magnitude directly reflects the interface trap density. Second, the tunneling current is strongly reduced allowing a more easy extraction of the CP signal and third, such a reduction prevents the insulator and the insulator-silicon interface from any degradation. By doing so, Si-SiO/sub 2/ interface trap densities are measured in MOSFETs with oxides which are 1.8 and 1.3 nm thick.     

Direct tunneling of electrons in Al-n+-Si-SiO2-n-Si structures under conditions of nonstationary depletion of the semiconductor surface of the majority charge carriers

Specific features of direct tunneling of electrons through an ultrathin (∼40 ?) oxide in metal-SiO₂-Si structures under nonstationary conditions of depletion of the semiconductor surface, in which case the potential relief in the insulator is only slightly perturbed by external electric fields, have been experimentally studied. Penetrability of the tunneling barrier is appreciably limited by a classically forbidden region in n-Si (this region is brought about by fixed negative charge in SiO₂). As the voltage drop across oxide is increased, the electrons localized within this oxide transfer to the semiconductor, which is accompanied by a drastic increase in the tunneling current. The values of coefficients linear rise in the logarithm of tunneling current as the voltage at the isolator is increased are determined from the experiment. These values are not consistent with the data calculated on the basis of a model of a rectangular barrier with parameters typical of “thick” oxides. It is shown that actual values of the effective mass are bound to be larger than 0.5m ₀, while the height of the barrier is bound to be lower than 3.1 eV.     

Transistor characteristics with Ta2O5 gatedielectric

As the gate oxide thickness decreases below 2 nm, the gate leakage current increases dramatically due to direct tunneling current. This large gate leakage current will be an obstacle to reducing gate oxide thickness for the high speed operation of future devices. A MOS transistor with Ta₂O₅ gate dielectric is fabricated and characterized as a possible replacement for MOS transistors with ultra-thin gate silicon dioxide. Mobility, I_d-V_d, I_d-V_g, gate leakage current, and capacitance-voltage (C-V) characteristics of Ta₂O₅ transistors are evaluated and compared with SiO₂ transistors. The gate leakage current is three to five orders smaller for Ta₂O₅ transistors than SiO₂ transistors