Determination of Si/SiO2 interface roughness using weaklocalization

The interface roughness of intentionally textured Si/SiO₂ interfaces was measured using the quantum weak localization (WL) correction to the electrical conductivity at low temperatures. The deduced roughness was confirmed by observation of the Si surface replicas by atomic force microscopy (AFM). Quantitative agreement between the two methods was found (Δ=1.2 to 1.4 Å from WL and 1.35 Å from AFM). For a surface with artificially induced texture, it is found that WL can easily distinguish a significant increase in roughness relative to the smooth surfaces. AFM confirms this qualitative conclusion     

The doped Si/SiO2 interface

A study is reported of the influence of dopant atoms on the SiSiO₂ interface states of thermally oxidized silicon. It was found that acceptor or donor atoms induce interface states and oxide charges. The effect is largest in the case of acceptor dopants and is independent of the doping process. The influence of the dopant atoms on oxide charge is probably related to the different segregation coefficients of acceptors and donors.     

Laser-induced self-organization of nano-wires on SiO2/Si interface

Original observation of new graded band gap structures formed on the surface of elementary Si semiconductor at studying the optical properties of Si nano-hills formed at the SiO₂/Si interface by pulsed Nd:YAG laser irradiation is reported. The self-organized nano-hills on Si surface are characterized by a strong photoluminescence in the visible range of spectrum with a shoulder extended to the long-wave part of the spectrum. The feature is explained by the quantum confinement effect in nano-hills-nano-wires of gradually changing diameter.     

Characterising the surface roughness of AFM grown SiO2 on Si

The reliability of AFM grown SiO₂ as a gate oxide needs to be examined if nanodevices fabricated from the oxide are to be integrated into standard microelectronic technology. In this article we present our preliminary results on AFM fabrication and topographical characterisation of large area oxide, electrical characterisation is to follow. Roughness is the central issue of this work due to its importance in relation to the quality of ultra thin dielectrics.     

The influence of mobile ions on the Si/SiO2 interface traps

An investigation of the relation between mobile ions and interface traps was carried out, using an appropriate technique to determine the number and type of mobile ions. It was found that mobile ions do not cause interface traps in the middle 0.8 eV of the bandgap. It appears that interface traps are rather caused by some stress effect. The results are considered in light of previously reported work.     

SiSiO2 interface states based on optically activated conductance technique

Experimental technique recently developed by Poon and Card has been used to determine the energy distribution of the interface states at the SiSiO₂ interface using AlSiO₂nSi structure with an oxide thickness $\text{?38}\text{A}\text{?}$. The distribution obtained in the band gap of silicon was distorted U-shaped. The distortion in the lower half of the band gap was more pronounced. Surface state density in the structure studied was of the order of 10¹²/cm² eV.     

SiSiO2 interface state spectroscopy using MOS tunneling structures

This paper provides a critical review and classification of the studies of SiSiO₂ interface state parameters and energy distributions by means of MOS tunneling in structures with ultrathin SiO₂ layers (10–100 Å). Suggestions are made of experiments that will help to elucidate the importance of materials and processing conditions on these states, and to separate the various mechanisms involving charge exchange with the metal, the conduction band, and the valence band of the semiconductor.     

Effects of nitrogen annealing on electron scatterings in SiSiO2 interface

The effective mobility of electrons at Si (100) surfaces was measured as a function of electron density N_s = 5 × 10¹¹?1 × 10¹³ cm^?2 at 4.2K for samples with and without annealing (10 min–2 hr) in nitrogen gas at 1000°C after wet thermal oxidation. A great part of the scattering by Coulomb and short-range potentials was reduced by a short (～10 min) anneal time, although the subsequent annealing resulted in a slight increase in the number of the scatterers. On the other hand, scattering by a surface roughness potential was reduced with increase in the anneal time. These scattering effects associated with N₂ annealing are discussed.     

Charge-pumping characterization of SiO2/Si interface invirgin and irradiated power VDMOSFETs

The applicability of charge-pumping technique to characterize the oxide/silicon interface in standard power Vertical Double-diffused (VD)MOS transistors is studied. Qualitative analysis of the charge-pumping threshold and flat-band voltage distributions in the VDMOS structure, supported with rigorous transient numerical modeling of the charge-pumping effect, shows that the measurements can be carried out in the subthreshold region. This conclusion is confirmed by various experimental results. The characteristics, i.e. charge-pumping current versus gate top level, is studied in detail. The changes in the characteristics after γ-ray irradiation are analyzed. A charge-pumping-based method for separate extraction of interface state density and density of charge trapped in the oxide after irradiation of VDMOSFETs is proposed. The validity and limitations of the method are studied by experiments and modeling     

Flat-field spectrograph in SiO2/Si

The operation of a flat-field spectrograph in silica glass on silicon (SiO₂/Si) as a demultiplexer with 4-nm channel spacing in the 1.5-μm waveguide length region is demonstrated. The concept allows fabrication tolerances to be compensated simultaneously with the adjustment of fan-out. Fiber-to-fiber insertion loss of 10.1 dB and crosstalk attenuation >15 dB have been achieved     

Thermally stimulated current in SiO2

Thermally stimulated current (TSC) techniques provide information about oxide-trap charge densities and energy distributions in MOS (metal-oxide-semiconductor) capacitors exposed to ionizing radiation or high-field stress that is difficult or impossible to obtain via standard capacitance–voltage or current–voltage techniques. The precision and reproducibility of measurements through repeated irradiation/TSC cycles on a single capacitor is demonstrated with a radiation-hardened oxide, and small sample-to-sample variations are observed. A small increase in E′_δ center density may occur in some non-radiation-hardened oxides during repeated irradiation/TSC measurement cycles. The importance of choosing an appropriate bias to obtain accurate measurements of trapped charge densities and energy distributions is emphasized. A 10 nm deposited oxide with no subsequent annealing above 400°C shows a different trapped-hole energy distribution than thermally grown oxides, but a similar distribution to thermal oxides is found for deposited oxides annealed at higher temperatures. Charge neutralization during switched-bias irradiation is found to occur both because of hole-electron annihilation and increased electron trapping in the near-interfacial SiO₂. Limitations in applying TSC to oxides thinner than 5 nm are discussed.     

High-quality MOSFETs with ultrathin LPCVD gate SiO2

MOSFETs and MOS capacitors with ultrathin (65 Å) low-pressure chemical vapor deposition (LPCVD) gate SiO₂ have been fabricated and compared to those with thermal SiO₂ of identical thickness. Results show that the devices with LPCVD SiO₂ have higher transconductance and current drivability, better channel hot-carrier immunity, lower defect density, and better time-dependent dielectric breakdown (TDDB) characteristics than devices with conventional thermal SiO₂     

An epitaxial Si/SiO2 superlattice barrier

An epitaxial strain layer Si/SiO₂ superlattice barrier (SLSB) for silicon formed by monolayers of adsorbed oxygen, sandwiched between adjacent thin silicon layers deposited with molecular beam, showed good epitaxy with an effective barrier height of 1.7 eV. Such a barrier should be important for future quantum devices in silicon, as well as new applications in conventional MOS technology.     

Visible light emitting Si/SiO2 superlattices

Six-period superlattices of Si/SiO₂ have been grown at room temperature using molecular beam epitaxy. With this mature technology, the ultra-thin (1–3 nm) Si layers were grown to atomic layer precision. These layers were separated by 1 nm thick SiO₂ layers whose thickness was also well controlled by using a rate-limited oxidation process. The chemical and physical structures of the multilayers were characterized by cross-sectional TEM, X-ray diffraction, Raman spectroscopy, Auger sputter-profile, and X-ray photoelectron spectroscopy. The analysis showed that the Si layer is free of impurities and is amorphous, and that the SiO₂/Si interface is sharp (0.5 nm). Photoluminescence (PL) measurements were made at room temperature using 457.9 nm excitation. The PL peak occurred at wavelengths across the visible range for these multilayers. The peak energy position E was found to be related to the Si layer thickness d by E (eV) = 1.60+0.72d⁻² in accordance with a quantum confinement mechanism and the bulk amorphous-Si band gap.     

Electrical properties of SiO2/TiO2 high-k gate dielectric stack

The trapping/detrapping behavior of charge carriers in ultrathin SiO₂/TiO₂ stacked gate dielectric during constant current (CCS) and voltage stressing (CVS) has been investigated. Titanium tetrakis iso-propoxides (TTIP) was used as the organometallic source for the deposition of ultra-thin TiO₂ films at low temperature (<200 °C) on strained-Si/relaxed-Si_0.8Ge_0.2 heterolayers by plasma-enhanced chemical vapor deposition (PECVD) in a microwave (700 W, 2.45 GHz) plasma cavity discharge system at a pressure of 66.67 Pa. Stress-induced leakage current (SILC) through SiO₂/TiO₂ stacked gate dielectric is modeled by taking into account the inelastic trap-assisted tunneling (ITAT) mechanism via traps located below the conduction band of TiO₂ layer. The increase in the gate current density observed during CVS from room temperature up to 125 ^oC has been analyzed and modeled considering both the buildup of charges in the layer as well as the SILC contribution. Trap generation rate and trap cross-section are extracted. A capture cross-section in the range of 10⁻¹⁹ cm² as compared to 10⁻¹⁶ cm² in SiO₂ has been observed. A temperature-dependent trap generation rate and defects have also been investigated using time-dependent current density variation during CVS. The time dependence of defect density variation is calculated within the dispersive transport model, assuming that these defects are produced during random hopping transport of positively charge species in the insulating high-k stacked layers. SILC generation kinetics, i.e. defect generation probability under different injected fluences for various high-constant stress voltages in both polarities have been studied. An empirical relation between trap generation probability and applied stress voltage for various injected fluences has been developed.     

Evolution of surface-states density of Si/wet thermal SiO2 interface during bias-temperature treatment

Evolution of Si/SiO₂ surface state density during a negative bias temperature treatment is reported. Two kinds of surface state are observed and their evolution is studied with the oxidation conditions, the type of the substrate and a preliminary electronic irradiation as parameters. A qualitative model is proposed to explain the observed results.     

Thickness limitations of SiO2 gate dielectrics for MOSULSI

The impact of gate leakage current on MOSFET performance is examined and limits on gate oxide thickness for static and dynamic logic are determined. Leakage current has been found to be a greater problem for static logic than for dynamic logic circuits. Gate leakage current limits the minimum oxide thickness to approximately 2 nm for static logic configurations, and to approximately 3 nm in dynamic logic circuits. A poor drain design can become a limiting factor for dynamic logic circuits and raise the minimum oxide thickness required. Switching delay of static logic is relatively immune to the effects of leakage current. A MISFET with a 2.6 nm thick gate insulator of Si₃N ₄ has been fabricated showing typical drain current characteristics, but with a large amount of gate leakage current     

Measurements and modelling of thermal step current in GaN/SiO2/Si structure

In this work, we report results of measurement of space charge in GaN/SiO₂/Si structure by means of thermal step method (TSM) and capacitance-voltage (C-V). TSM is a non destructive method for quantifying and localizing the electric charges in insulating materials. Its principle consists to apply a low thermal step to a short-circuited or dc-biased sample and to record a current response, which depends on the charge present in the device. The C-V characteristics show an almost metal-oxide-semiconductor (MOS) behaviour and retention of charges after forward bias sweeping. The space charge dynamics in the structure are followed under low applied dc voltages. Results show a significant inversion of the TSM currents above applied voltage of 200 mV. A theoretical model is then presented in order to estimate the amount of the trapped charges and to interpret the variation of the TS currents as a function of the applied gate voltages.     

An experimental determination of the carrier lifetime near the SiSiO2 interface

Leakage currents in phosphorus-gettered (111) silicon have been studied at room temperature using a MOS gate-controlled diode structure. The leakage current and the gate-substrate capacitance have each been measured as a function of gate voltage for different values of reverse bias. From these measurements the carrier lifetime in the depletion region near the SiSiO₂ interface has been deduced. It is found that the lifetime decreases with distance from the interface; an explanation for this is suggested.     

Novel low-temperature C-V technique for MOS doping profiledetermination near the Si/SiO2 interface

An inverse modeling technique for doping profile extraction from MOS C-V measurements is presented. The method exploits the “kink” effect observed near flat bands in low-temperature C-V curves to accurately estimate the dopant concentration at the oxide-silicon surface. The inverse modeling approach, based on a self-consistent Schrodinger-Poisson solver, overcomes the limitations of previous analytical methods. The accuracy of the doping extraction is demonstrated by successfully reconstructing doping profiles from simulated C-V curves, including abrupt variations of doping in the vicinity of the oxide interface. When applied to experimental data from boron- and phosphorus-doped samples, the technique is shown to provide a substantial improvement in resolution with respect to room-temperature C-V measurements