Laser microchemical techniques for reversible restructuring of gate-array prototype circuits

Laser direct-write Al etching and poly-Si deposition have been adapted to the mask-free alteration of simple gate-array test circuits. Simple test structures on commercial CMOS chips have been reconfigured with no degradation in device or circuit performance. These new methods may be useful for rapid evaluation and optimization of integrated-circuit prototypes.     

Micromachined thermal radiation emitter from a commercial CMOSprocess

Fabrication of thermally isolated micromechanical structures capable of generating thermal radiation for dynamic thermal scene simulation (DTSS) is described. Complete compatibility with a commercial CMOS process is achieved through design of a novel, but acceptable, layout for implementation by the CMOS foundry using its regular process sequence. Following commercial production and delivery of the CMOS chips, a single maskless etch in an aqueous ethylemediamine-pyrocatechol mixture is performed to realize the micromechanical structures. The resulting structures are suspended plates consisting of polysilicon resistors encapsulated in the field and CVD (chemical-vapor-deposited) oxides available in the CMOS process. The plates are suspended by aluminum heater leads that are also encapsulated in the field and CVD oxides. Studies of the suitability of these structures for DTSS have been initiated, and early favorable results are reported     

Influence of TiSi2 formation temperature on film thermal stability

This work is addressed to investigate thermal stability of a thin TiSi₂ film, that is its ability to resist degradation due to heat treatments at high temperatures. The study was carried out as a function of the formation RT treatment (675–750°C) at the end of a common process flow. Sheet resistance measurements were employed in order to evaluate this degradation. Electrical measures were performed on large and narrow poly-Si lines, on Van Der Pauw structures and on doped mono-Si substrates. An increase in sheet resistance value of an order of magnitude for silicide formed at temperatures below 700°C with respect to the one formed at temperatures above 700°C was found, particularly on poly-Si lines. The effect is detectable independently of the structure: it was observed also on 0.75-μm wide poly-Si lines, increasing when line width decreases. Different morphological analyses were carried out for investigating the influence of the formation temperature. We explain the increase of the final sheet resistance decreasing the formation temperature as a lower thermal stability of the TiSi₂ film, leading to a thermal grooving of the silicide grains.     

双电荷离子注入的倒阱技术

本文从VLSl CMOS倒阱意义出发,结合我所中能离子注入的双电荷产生及其应用研究,介绍了在NV—3204注入机上实现近400keV的B受主高能注入以形成单峰(约1.0μm)、阱深(约2.0μm)的P倒阱。在此基础上,将它应用到新的CMOS硅栅工艺中。结果初步预示:新一代P倒阱CMOS硅栅工艺具有工艺流程简单、高温经历时间短、抗闩锁能力强等优点。对于只有中能离子注入机的单位,这一双电荷离子注入形成倒阱,将是一种现实有效的技术,也是P型深注入结的有效手段。     

Thermal/luminescence characterization and degradation mechanism analysis on phosphor-converted white LED chip scale packages

According to the requirements on minimizing the package size, guaranteeing the performance uniformity and improving the manufacturing efficiency in LEDs, a Chip Scale Packaging (CSP) technology has been developed to produce white LED chips by impressing a thin phosphor film on LED blue chips. In this paper, we prepared two types of phosphor-converted white LED CSPs with high color rendering index (CRI > 80, CCT ~ 3000 K and 5000 K) by using two mixed multicolor phosphor materials. Then, a series of testing and simulations were conducted to characterize both short- and long-term performance of prepared samples. A thermal analysis through both IR thermometry and electrical measurements and thermal simulation were conducted first to evaluate chip-on-board heat dissipation performance. Next, the luminescence mechanism of multicolor phosphor mixtures was studied with the spectral power distribution (SPD) simulation and near-field optical measurement. Finally, the extracted features of SPDs and electrical current-output power (I-P) curves measured before and after a long-term high temperature accelerated aging test were applied to analyze the degradation mechanisms. The results of this study show that: 1) The thermal management for prepared CSP samples provides a safe usage condition for packaging materials at ambient temperature; 2) The Mie theory with Monte-Carlo ray-tracing simulation can be used to simulate the SPD of Pc-white LEDs with mixed multicolor phosphors; 3) The degradation mechanisms of Pc-white LEDs can be determined by analyzing the extracted features of SPDs collected after aging.     

A high-performance directly insertable self-alignedultra-radiation-hard and enhanced isolation field-oxide technology forgigahertz Si-CMOS VLSI

A field-oxide structure for radiation-hard CMOS VLSI is described. It is a three-layer structure consisting of a thin thermal oxide, a doped polysilicon sheet deposited on the thin oxide, and a thick CVD oxide layer deposited on the polysilicon. The polysilicon sheet is maintained at the substrate potential by, e.g. using n-type poly-Si over the n-tub and p-type poly-Si over the p-tub or p-substrate and allowing contacts to be made through the thin oxide. The small effective electrical thickness of the thin oxide combined with the ground potential of the polysilicon enhances the radiation hardness and maintains good isolation even at radiation levels as high as 10⁸ rads and above. This structure is self-aligned to the active regions and directly insertable into a submicrometer CMOS VLSI without any changes in the circuit design. The circuits made with this technology can operate at 2.5-3 GHz even after a total dose of 50-100 Mrad     

The fabrication and dry etching of poly-Si/TaN/Mo gate stack in the metal inserted poly-Si stack structure

The Mo-based metal inserted poly-Si stack (MIPS) structure is an appropriate choice for metal gate and high-k integration in sub-45 nm gate-first CMOS device. A novel metal nitride layer of TaN or AlN with high thermal stability has been introduced between Mo and poly-Si as a barrier material to avoid any reaction of Mo during poly-Si deposition. After Mo-based MIPS structure is successfully prepared, dry etching of poly-Si/TaN/Mo gate stack is studied in detail. The three-step plasma etching using the Cl₂/HBr chemistry without soft landing step has been developed to attain a vertical poly-Si profile and a reliable etch-stop on the TaN/Mo metal gate. For the etching of TaN/Mo gate stack, two methods using BCl₃/Cl₂/O₂/Ar plasma are presented to get both vertical profile and smooth etched surface, and they are critical to get high selectivity to high-k dielectric and Si substrate. In addition, adding a little SF₆ to the BCl₃/O₂/Ar plasma under the optimized conditions is also found to be effective to smoothly etch the TaN/Mo gate stack with vertical profile.     

Radiation-induced degradation in the dynamic parameters of memory chips

A technique for investigating CMOS memory chips under exposure to ionizing radiation and the results of their radiation tests are presented. Possible mechanisms of degradation and approaches to increasing the radiation resistance of integrated circuits by the access time criterion are analyzed. The effect of the nonuniform degradation of the access time depending on the address has been discovered and investigated in the experiment.     

Characteristics of p- and n-channelpoly-Si/Si1-xGex/Si sandwiched conductivitymodulated thin-film transistors

Both p- and n-channel poly-Si/Si_1-xGe_x/Si sandwiched conductivity modulated thin-film transistors (CMTFTs) are demonstrated and experimentally characterized. The transistors use a poly-Si/Si_1-xGe_x/Si sandwiched structure as the active layer to avoid the poor interface between the gate oxide and the poly-Si_1-xGe_x material. Also an offset region placed between the channel and the drain is used to reduce the leakage current. Furthermore, the concept of conductivity modulation in the offset region is used to provide a high on-state current. Results show that the transistors provide a high on-state current as well as a low leakage current compared to those of conventional offset drain TFTs. The p- and n-channel CMTFTs can be combined to form CMOS drivers, which are very suitable for use in low temperature large area electronic systems on glass applications     

Highly thermal robust NiSi for nanoscale MOSFETs utilizing a novel hydrogen plasma immersion ion implantation and Ni-Co-TiN tri-layer

In this letter, hydrogen plasma immersion ion implantation (H PIII) with Ni-Co-TiN tri-layer is introduced for the first time to enhance the thermal stability of the Ni-silicide for nanoscale CMOS technology. The Ni-silicided poly-Si gate and source/drain showed stable sheet resistance in spite of 650/spl deg/C, 30 min post-silicidation annealing. The junction leakage current is even improved a lot without degradation of device performance using the proposed method.     

Sub-1/4-μm dual-gate CMOS technology using in-situ dopedpolysilicon for nMOS and pMOS gates

A new dual poly-Si gate CMOS fabrication process is proposed. The incorporated technology features a boron-penetration-resistant MBN gate structure for pMOSFET's, and a dual poly-Si gate CMOS process involving separate depositions of in-situ doped n⁺ and p⁺ poly-Si for the nMOS and pMOS gates, 0.2-μm CMOS devices with 3.5-nm gate oxide have been successfully fabricated. The advantages of the new process are demonstrated on these test devices. A CMOS 1/16 dynamic frequency divider fabricated by the new process functions properly up to 5.78 GHz at a 2-V supply voltage     

一種製作互補式金氧半複晶矽薄膜電晶體之製程簡化技術

一種製作互補式金氧半複晶矽薄膜電晶體之製程簡化技術被提出, 其藉由大角度離子佈植摻雜物穿透閘極間隙壁. 藉由此技術方法,可使用同一光罩而同時形成淡摻雜區域於閘極間隙壁氧化層下方且形成高摻雜區域,其可於互補式金氧半複晶矽薄膜電晶體製作時簡化製程步驟.更進一步地,藉由此技術,與傳統的單一高濃度摻雜源汲極技術相較,此方法可得到更好的N型及P型薄膜電晶體特性,且無需增加光罩製程.     

一种新型的集成电路片上CMOS温度传感器

介绍了一种可以用于片上温度监控的CMOS温度传感器,该传感器具有面积小、功耗低、精度高、易于实现等优点,可以比较容易地集成到芯片上实现温度监测功能.     

Characterisation and simulation of digital device electromagnetic noise under non-ambient temperature conditions

Presented is a new approach to the evaluation of electromagnetic emissions of electronics circuits under thermal stress. Near-field radiations, of essentially magnetic-type owing to the current switching of CMOS chips, have been measured in different external temperature conditions. Electrical equivalent models are proposed to investigate thermal influences on the electromagnetic compatibility characteristics of a printed circuit board excited by digital sources.     

Temperature measurements and thermal modeling of high power IGBT multichip modules for reliability investigations in traction applications

To study the failure mechanisms induced on high power IGBT multichip modules by thermal cycling stress in traction environment, a good knowledge of the temperature distribution and variations on the chips and in the interfaces between the different layers of the packaging is necessary. This paper presents a methodology for contact temperature measurements on chips surface in power cycling conditions and a fast 3D thermal simulation tool for multilayered hybrid or monolithic circuits. The results of static and dynamic thermal simulation of a 1200A–3300V IGBT module are given and compared with the contact temperature measurements results. The investigation has been done within the RAPSDRA (Reliability of Advanced High Power Semiconductor Device for Traction Applications) European project.     

A process simplification scheme for fabricating CMOS polycrystalline-Si thin film transistors

A process simplification scheme for fabricating CMOS poly-Si thin-film transistors (TFTs) has been pro-posed, which employs large-angle-tilt-implantation of dopant through a gate sidewall spacer (LATITS). By this LATITS scheme, a lightly doped drain region under the oxide spacer is formed by low-dose tilt implantation of phosphorus (orboron) dopant through the spacer, and then the n+-source/drain (n+-S/D) (or p+-S/D) region is formed via using the same photo-mask layer during CMOS integration. For both n-TFT and p-TFT devices, as compared to the sample with conventional single n+-S/D (or p+-S/D) structure, the LATITS scheme can cause an obviously smaller leakage current, due to more gradual dopant distribution and thus smaller electric field. In addition, the resultant on-state currents only show slight degradation for the LATITS scheme, As a result, by the LATITS scheme, CMOS poly-Si TFT devices with an on/off current ratio well above 8 orders may be achieved without needing extra photo-mask layers during CMOS integration.     

Aging comparative analysis of high-performance FinFET and CMOS flip-flops

This paper presents a comparative performance analysis to investigate the impact of aging mechanisms on various flip-flops in CMOS and FinFET technologies. We consider Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI) effects on the robustness of high performance flip-flops. To apply BTI and HCI aging mechanisms, we utilize long-term model to estimate ∆ V_th and employ the updated V_th in transistor model file. The simulation results on performance analysis indicate the high ranking of various flip-flops considering speed and power consumption in each CMOS and FinFET technologies, moreover, approve the superiority of static FinFET flip-flops over CMOS flip-flops. In addition, a comparative analysis considering temperature and V_DD variations over different FinFET flip-flop structures demonstrates the average percentages of T_DQmin and PDP degradation against aging mechanisms are significantly less than similar CMOS flip-flops.     

Laser thermal processing of amorphous silicon gates to reduce poly-depletion in CMOS devices

One major challenge in advanced CMOS technology is to have adequate dopant activation at the polycrystalline silicon (poly-Si) gate/gate oxide interface to minimize the poly-Si depletion effect. In this paper, laser thermal processing (LTP) was employed to fabricate single or dual-layer poly-Si-gated MOS capacitors with ultrathin gate oxides. Capacitance-voltage data show that the carrier concentration at the poly-Si gate/gate oxide interface increases substantially when the devices are subjected to LTP prior to a rapid thermal anneal (RTA). Thus, LTP readily reduces the poly-depletion thickness in MOS devices. For p/sup +/-gated capacitors, this is achieved with boron penetration that is equivalent to the control sample with 1000/spl deg/C, 5 s RTA (without LTP). In addition, results from secondary ion mass spectrometry indicate that the concentration of dopants near the critical gate/gate oxide interface increases significantly after a post-LTP anneal, in good agreement with the electrical data. Time-dependent dielectric breakdown studies show that the gate oxide reliability is not degraded even after LTP at high fluences.     

CMOS sensors for on-line thermal monitoring of VLSI circuits

The paper presents appropriate sensors for the realization of the design principle of design for thermal testability (DfTT). After a short overview of the available CMOS temperature sensors, a new family of temperature sensors will be presented, developed by the authors especially for the purpose of thermal monitoring of VLSI chips. These sensors are characterized by the very low silicon area of about 0.003-0.02 mm² and the low power consumption (200 μW). The accuracy is in the order of 1°C. Using the frequency-output versions an easy interfacing of digital test circuitry is assured. They can be very easily incorporated into the usual test circuitry, via the boundary-scan architecture. The paper presents measured results obtained by the experimental circuits. The facilities provided by the sensor connected to the boundary-scan test circuitry are also demonstrated experimentally     

Multi-dimensional data registration CMOS/MEMS integrated inkjet printhead

This paper describes our work aimed at developing an integrated multi-dimensional thermal inkjet (TIJ) printhead with data registration CMOS de-multiplexer utilizing bulk micromachining technology (MEMS). In this experiment, we developed a new structural design for chips used in inkjet printheads. We designed a thermal inkjet device, whose dimensions could be adjusted to optimize drop generation performance. The energy conversion device and accompanying system were based on an integrated driver head with the performance of a high-frequency, picoliter drop inkjet. The inkjet featured a smart CMOS circuit including D Flip-Flops signal processes along with bi-directional data transfer and 12 V power amplifiers in a printhead chip. All of the jets of the printhead were controlled by very few input lines, a pulse shape (ENABLE), a data line (DATA), a bit shift clock (BIT SHIFT), a state clearing pulse, 5-volt supply for the logic devices, a higher voltage for energizing the heater resisters, and a ground line. The fabricated backside etching of the thermal inkjet (TIJ) printhead was measured by open pool and closed pool systems. The starting voltage was measured at 6.5 V, and its lifespan was 1.5 × 10⁸.