Low electric field breakdown of thin SiO2 films understatic and dynamic stress

A comprehensive study of Time-Dependent Dielectric Breakdown (TDDB) of 6.5-, 9-, 15-, and 22-nm SiO₂ films under dc and pulsed bias has been conducted over a wide range of electric fields and temperatures. Very high temperatures were used at the wafer level to accelerate breakdown so tests could be conducted at electric fields as low as 4.5 MV/cm. New observations are reported for TDDB that suggest a consistent electric field and temperature dependence for intrinsic breakdown and a changing breakdown mechanism as a function of electric field. The results show that the logarithm of the median-test-time-to failure, log (t₅₀), is described by a linear electric field dependence with a field acceleration parameter that is not dependent on temperature. It has a value of approximately 1 decade/MV/cm for the range of oxide thicknesses studied and shows a slight decreasing trend with decreasing oxide thickness. The thermal activation E_a ranged between 0.7 and 0.95 eV for electric fields below 9.0 MV/cm for all oxide thicknesses. TDDB tests conducted under pulsed bias indicate that increased dielectric lifetime is observed under unipolar and bipolar pulsed stress conditions, but diminishes as the stress electric field and oxide thickness are reduced. This observation provides new evidence that low electric field aging and breakdown is not dominated by charge generation and trapping     

Characterization of SiO2 dielectric breakdown forreliability simulation

The authors analyze breakdown distributions of thin oxide MOS capacitors to reveal the limitations of accelerated procedures for reliability simulation at circuit level. The detailed analysis of the breakdown distributions corresponding to different stress voltages shows the presence of three modes of breakdown, associated with different kinds of defects. These breakdown nodes control the shape of the distributions at different oxide field ranges. The mean values of time-to-breakdown, charge-to-breakdown, and energy-to-breakdown and their dependence on oxide field are found to be directly related to the mode dominating the distribution. Since the shape of the breakdown distribution changes with stress voltage, an accelerated testing procedure must provide a way to extrapolate to operation conditions not only the mean value, but also the shape of the distribution. The results indicate that different physical mechanisms cause the breakdown at low and high fields     

Time-dependent breakdown of ultra-thin SiO2 gatedielectrics under pulsed biased stress

Ultra-thin SiO₂ films (t_ox~2.0 nm) were stressed under DC, unipolar, and bipolar pulsed bias conditions up to a pulse repetition frequency of 50 kHz. The time-to-breakdown (t_BD ), the number of defects at breakdown (N_BD), and the number of defects generated inside the oxide as a function of stress time were monitored during each stress condition. Oxide lifetime under unipolar pulsed bias is similar to that under DC conditions; however lifetime under bipolar pulsed bias is significantly improved and exhibits a dependence on pulse repetition frequency. The observation of a lifetime increase under bipolar pulsed bias for the oxide thickness and voltage range used in this study suggests that a different physical mechanism may be responsible for the lifetime increase from that assumed in earlier studies for thicker films     

High-frequency time-dependent breakdown of SiO2

The time-dependent dielectric breakdown of thin oxides (8.6-11 nm) are compared under DC, pulse, and bipolar pulse conditions for frequencies up to 4 MHz. Lifetime under unipolar pulse conditions does not deviate largely from that under DC conditions; however, lifetime under bipolar stress conditions increases by a factor of 40 to 100 at frequencies above 10 kHz. The field accelerations of breakdown time are similar for DC and pulse stressing     

Pre-breakdown in thin SiO2 films

The on-off fluctuations of the tunnel current in 5.6 nm SiO₂ films before dielectric breakdown are analyzed in detail. For this purpose, a low noise measurement system has been realized which allows detection of pre-breakdown phenomena and interruption of the stress before catastrophic failure occurs. A spectral analysis of these fluctuations is presented along with preliminary results of the experiments made possible, for the first time, by the new measurement system     

Simulation of degradation of dielectric breakdown field of thermalSiO2 films due to voids in Si wafers

Degradation of the dielectric breakdown field of thermal SiO₂ film caused by voids that are formed during growth of silicon single crystal has been a serious problem with reliability of MOS devices. To understand the degradation of breakdown field, local thinning of oxide film grown on pits (i.e., voids exposed at the wafer surface) is simulated using a simple model, and the degradation of breakdown field expected from the thinning is compared with experimental reports. In the model, oxide film grown on the inner surface of a sphere is calculated by assuming that deformation of oxide film is visco-elastic and that oxidation reaction rate is reduced by compressional normal stress acting on the Si/SiO₂ interface. The calculated results show appreciable thinning of oxide film, which explains the low breakdown field observed experimentally. It also helps to understand the unique degradation characteristics reported for pits and voids: lower breakdown field for thicker oxide film and recovery of breakdown field by chemical etching. No clear pit size dependence observed in the experiments suggests that the oxide thinning is localized at corners of voids     

High-field-induced degradation in ultra-thin SiO2 films

Very thin thermal oxides are shown to exhibit a failure mode that is undetected by conventional breakdown tests. This failure mode appears in the form of excessive leakage current at low field and is induced by high-field stresses. The stress-induced oxide leakage is permanent and stable with time and thermal annealing. It becomes the dominant failure mode of thin oxides because it always precedes destructive breakdown. Experimental results and theoretical calculations show that the leakage current is not caused by positive charge generation and accumulation in the oxide. It is proposed that the oxide leakage originates from localized defect-related weak spots where the insulator has experienced significant deterioration from electrical stress. The leakage conduction mechanism appears to be thermally assisted tunneling through the locally reduced injection barrier, and the model seems to be consistent with both I-V measurements at temperatures from 77 K to 250°C and theoretical calculations     

Time-dependent dielectric breakdown characteristics ofN2O oxide under dynamic stressing

Time-dependent dielectric breakdown (TDDB) characteristics of MOS capacitors with thin (120-Å) N₂O gate oxide under dynamic unipolar and bipolar stress have been studied and compared to those with control thermal gate oxide of identical thickness. Results show that N₂O oxide has significant improvement in t _BD (2×under-V_g unipolar stress, 20×under+V_g unipolar stress, and 10×under bipolar stress). The improvement of t_BD in N₂O oxide is attributed to the suppressed electron trapping and enhanced hole detrapping due to the nitrogen incorporation at the SiO₂/Si interface     

Electrical properties of SiO2/TiO2 high-k gate dielectric stack

The trapping/detrapping behavior of charge carriers in ultrathin SiO₂/TiO₂ stacked gate dielectric during constant current (CCS) and voltage stressing (CVS) has been investigated. Titanium tetrakis iso-propoxides (TTIP) was used as the organometallic source for the deposition of ultra-thin TiO₂ films at low temperature (<200 °C) on strained-Si/relaxed-Si_0.8Ge_0.2 heterolayers by plasma-enhanced chemical vapor deposition (PECVD) in a microwave (700 W, 2.45 GHz) plasma cavity discharge system at a pressure of 66.67 Pa. Stress-induced leakage current (SILC) through SiO₂/TiO₂ stacked gate dielectric is modeled by taking into account the inelastic trap-assisted tunneling (ITAT) mechanism via traps located below the conduction band of TiO₂ layer. The increase in the gate current density observed during CVS from room temperature up to 125 ^oC has been analyzed and modeled considering both the buildup of charges in the layer as well as the SILC contribution. Trap generation rate and trap cross-section are extracted. A capture cross-section in the range of 10⁻¹⁹ cm² as compared to 10⁻¹⁶ cm² in SiO₂ has been observed. A temperature-dependent trap generation rate and defects have also been investigated using time-dependent current density variation during CVS. The time dependence of defect density variation is calculated within the dispersive transport model, assuming that these defects are produced during random hopping transport of positively charge species in the insulating high-k stacked layers. SILC generation kinetics, i.e. defect generation probability under different injected fluences for various high-constant stress voltages in both polarities have been studied. An empirical relation between trap generation probability and applied stress voltage for various injected fluences has been developed.     

Structural properties of fluorinated SiO2 thin films

Fluorinated SiO₂ (SiOF) films, prepared by plasma enhanced chemical vapour deposition from SiH₄, N₂O and CF₄ precursors, have been analysed by infrared (IR) spectroscopy and X-ray photoelectron spectroscopy (XPS) to extract chemical and structural information. Notwithstanding XPS reveals that fluorine concentrations are quite low (less than 4 at.%), the analysis of the Si–O–Si vibration modes in the IR spectra indicates that CF₄ addition involves a deeper modification of the film structure, than the simple formation of Si–F bonds. In particular, by increasing the F concentration in the oxides, the stretching frequency of the Si–O–Si bonds increases, while the bending frequency decreases. On the basis of the central force model, both observations are consistent with the occurrence of a Si–O–Si bond angle relaxation phenomenon, the importance of which increases with the fluorine concentration in the films.     

超薄SiO2/HfO2双层栅介质的时变击穿特性和击穿机制的研究

The characteristics of TDDB （time-dependent dielectric breakdown） and SILC （stress-induced leakage current） for an ultra-thin SiO2/HfO2 gate dielectric stack are studied. The EOT （equivalent-oxide-thickness） of the gate stack （Si/SiO2/HfOz/TiN/TiA1/TiN/W） is 0.91 am. The field acceleration factor extracted in TDDB experi- ments is 1.59 s.cm/MV, and the maximum voltage is 1.06 V when the devices operate at 125 ℃ for ten years. A detailed study on the defect generation mechanism induced by SILC is presented to deeply understand the break- down behavior. The trap energy levels can be calculated by the SILC peaks： one S1LC peak is most likely to be caused by the neutral oxygen vacancy in the HfO2 bulk layer at 0.51 eV below the Si conduction band minimum; another SILC peak is induced by the interface traps, which are aligned with the silicon conduction band edge. Fur- thermore, the great difference between the two SILC peaks demonstrates that the degeneration of the high-k layer dominates the breakdown behavior of the extremely thin gate dielectric.     

Comparison of electrical stress-induced charge carrier generation/trapping and related degradation of SiO2 and HfO2/SiO2 gate dielectric stacks

We compare charge carrier generation/trapping related degradation in control oxide (SiO₂) and HfO₂/SiO₂ stack of an identical equivalent-oxide-thickness (EOT) during constant gate voltage stress of n-type metal-oxide-semiconductor (nMOS) capacitors. Irrespective of these two dielectrics, the kinetics of generation of both surface states and oxide-trapped positive charges are found to be similar. Our analysis shows that the positive oxide charge buildup during CVS is due to trapping of protons by the strained SiOSi bonds in either of the devices. We demonstrate that compared to SiO₂ devices, HfO₂ devices with an equal EOT better perform in CMOS logic applications. On the other hand, our results indicate that the control oxide is better in charge trapping memory devices. Furthermore, the lifetime of the control oxide devices is observed longer than that of HfO₂ devices at a given operating voltage.     

Contact potential measurements on thin SiO2 films

Contact potential measurements by the Kelvin method were performed in vacuum on silicon wafers whose thermal oxide film was etched into the shape of a wedge. A given position along the oxide corresponded directly to a given depth and by scanning a reference electrode stripe across the wafer, information about the distribution of the oxide charge through the thickness was obtained. It was found that the oxide charge was positive and concentrated within a few hundred angstroms of the SiSiO₂ interface.     

A detailed study of current–voltage characteristics in Au/SiO2/n-GaAs in wide temperature range

The forward and reverse-bias current–voltage (I–V) characteristics of Au/SiO₂/n-GaAs (MIS) type Schottky barrier diode (SBDs) have been investigated in the wide temperature range of 80–400 K. The zero-bias barrier height (_Bo) and ideality factor (n) assuming the thermionic emission (TE) mechanism show strong temperature dependence. While n decreases, _Bo increases with increasing temperature. Such temperature dependence of _Bo is an obvious disagreement with the reported negative temperature coefficient (α_temp) of barrier height. Therefore, we have reported a modification which includes the n and electron-tunneling parameter (αχ^1/2δ) in the expression of reverse-saturation current (I₀). After this modification, the value of α_temp obtained as −4 × 10⁻⁴ eV/K which is very close to α_temp of GaAs band-gap (−5.4 × 10⁻⁴ eV/K). Richardson plot of the ln(I₀/T²) versus 1/T has two linear region; the first region is (200–400 K) and the second region (80–150 K). The values of the activation energy (E_a) and Richardson constant were obtained from this plot and the values of E_a and Richardson constants (A^*) are much lower than the known values. These behaviors of the Au/SiO₂/n-GaAs (MIS) type (SBDs) have been interpreted by the assumption of a double-Gaussian distribution of barrier heights (BHs) at the metal–semiconductor interface giving a mean BHs () of 1.20 and 0.68 eV and standard deviation (σ_s) of 0.1503 and 0.0755 V, respectively. Thus the modified ln versus q/kT for two different temperature ranges (200–400 K and 80–150 K) plot then gives mean barrier heights and A^*, 1.18 and 0.66 eV and 7.08 and 3.81 A/cm² K², respectively. This value of the A^* 7.08 A/cm² K² is very close to the theoretical value of 8.16 A/cm² K² for n-type GaAs. Hence, all these behaviours of the forward-bias I–V characteristics of the Au/SiO₂/n-GaAs (MIS) type SBDs can be successfully explained on the basis of a TE mechanism with a double-Gaussian distribution of the BHs.     

Photo-CVD process for ultra thin SiO2 films

In this paper we first report the use of very low deposition rate photo-induced chemical vapor deposition process, (below 0.05 nm/min). This photo-CVD process is adequate to grow very thin and ultra thin layers of SiO₂. Details on the design of the reaction chamber, reactive gases and process parameters to obtain the desired deposition regime are presented. Dependence of deposition rate on pressure in the chamber and gas flow ratio is discussed. Deposited layers were characterized using I–V and C–V techniques.     

SiON and SiO2/HfSiON gate oxides time dependent dielectric breakdown measurements at nanoscale in ultra high vacuum

Time dependent dielectric breakdown (TDDB) measurements on a nano-scale using an AFM tip under ultra high vacuum as upper electrode are systematically compared to device measurements in this paper. Both studies were performed on the same SiON or SiO₂/HfSiON gate oxides. The shape factor of the TDDB distribution and the acceleration factor are compared at both scales.     

Spin synthesis of monolayer of SiO2 thin films

The highly ordered monolayer of submicron size silica (SiO₂) particles (235 nm) is developed on p-silicon by using three-step spin-coating in colloidal suspension, which has significant potential in various applications. The influence of three-step spin speeds, spinning time, acceleration time between different steps, concentration of SiO₂ particles in the solution, solution quantity, and the ambient humidity (relative humidity) on the properties of monolayer SiO₂ are studied in order to achieve a large area monolayer film. A relatively high surface coverage and uniform monolayer film of SiO₂ particles in the range of 85%-90% are achieved by appropriate control of the preparative parameters. We conclude that this method can be useful in industrial applications, because of the fabrication speed, surface coverage and cost of the process.     

Thin-film transistors incorporating a thin, high-quality PECVD SiO2 gate dielectric

Thin-film transistors (TFTs) have been made that incorporate a thin (~380 Å), high-quality plasma-enhanced chemical vapor deposition (PECVD) SiO₂ film as the gate dielectric in a staggered-inverted structure. Threshold voltages and mobilities have been found to be in the range of 1.6-2.4 V and 0.20-0.25 cm² V^-1 s^-1, respectively, where the exact values are dependent on the measurement technique used. Very low gate leakage currents (<10^-11 A) were recorded when measured using a ramped I-V technique, even for electric fields as high as 5×10⁶ V/cm     

Statistics of soft and hard breakdown in thin SiO2 gate oxides

Assuming that there are circuit applications which can tolerate one or several soft breakdown events before failure, we study the implications of soft/hard breakdown prevalence ratios on the device failure statistics. Our results demonstrate that these two breakdown modes are triggered by the same type of defect-related path, showing identical statistics if considered as independent breakdown mechanisms. An energy dissipation model for the breakdown current runaway transient is presented as a possible way to model soft and hard breakdown prevalence ratios as a function of stress conditions and sample characteristics.     

高介电常数栅介质/二氧化硅界面偶极子成因研究

The formation of an electric dipole at the high-k/SiO2 interface is quantitatively analyzed. The band lineups and physical origin of dipole formation at the high-k/SiO2 interface are explained by the dielectric contact induced gap states(DCIGS). The charge neutrality level(CNL) of the DCIGS, which represents a distribution of high-k and SiO2 contact induced gap states, is utilized to study the dipole moment. The charge transfer due to different CNLs of high-k and SiO2 is considered as the dominant origin of dipole formation. The theoretically calculated dipole strengths of high-k/SiO2 systems based on this model are in good agreement with the experimental data.