Performance and hot-carrier reliability of 100 nm channel lengthjet vapor deposited Si3N4 MNSFETs

Metal-nitride-semiconductor FETs (MNSFETs) having channel lengths down to 100 mm and a novel jet vapor deposited (JVD) Si₃N₄ gate dielectric have been fabricated and characterized. When compared with MOSFETs having a thermal SiO₂ gate insulator, the MNSFETs show a comparable drain current drive, transconductance, subthreshold slope and pre-stress interface quality. A novel charge pumping technique is employed to characterize the hot-carrier induced interface-trap generation in MNSFETs and MOSFETs. Under identical substrate current during stress, MNSFETs show less interface-state generation and drain current degradation, for various channel lengths, stress times and supply voltages, despite the fact that the Si-Si₃N₄ barrier (2.1 eV) is lower than the Si-SiO₂ barrier (3.1 eV). The time and voltage dependence of hot-carrier degradation has been found to be distinctly different for MNSFETs compared to SiO₂ MOSFETs     

A new method to characterize border traps in submicron transistors using hysteresis in the drain current

In this paper, a new method for measuring border trap density (n/sub BT/) in submicron transistors using hysteresis in the drain current is proposed. This method is used to measure energy and spatial distribution of border traps in jet vapor deposited (JVD) metal-silicon nitride-semiconductor field effect transistors (MNSFETs). The drain current transient varies linearly with logarithmic time suggesting that tunneling to and from the spatially uniform border traps is the dominant charge exchange mechanism. Using a feedback mechanism gate voltage transients are obtained from which n/sub BT/ is calculated. The prestress energy distribution in JVD MNSFETs is found to be uniform whereas the post-stress energy distribution shows a peak near the midgap.     

The Ge condensation technique: A solution for planar SOI/GeOI co-integration for advanced CMOS technologies?

This paper presents a general study on the germanium (Ge) condensation technique to assess its potential, issues and applications for advanced metal oxide semiconductor field effect transistor (MOSFET) technologies. The interest in such process for fabrication of ultrathin germanium on insulator (GeOI) layers for fully depleted GeOI MOSFETs application is first described. We highlight the impact of initial silicon on insulator (SOI) substrates uniformity on the process, determined as the key parameter to be improved. Next, a global procedure is described for MOSFETs integration on Ge layers grown on 75% Ge-enriched silicon germanium on insulator (SGOI) substrates obtained by the Ge condensation technique. A third section reviews the different local Ge condensation techniques for fabrication of SOI–GeOI hybrid substrates. Interests of such substrates for SOI–GeOI planar co-integration either at the microprocessor, at the cell or at the transistor level will be discussed. Finally, the fabrication of a first 50-nm-thick SOI–GeOI hybrid substrate is described.     

Application of charge pumping technique for sub-micron MOSFET characterization

In this paper, charge pumping technique for MOSFET interface characterization will be reviewed. The basic principles of charge pumping technique will be elaborated and its evolution as an excellent tool for a thorough characterization of MOSFET interface properties will be illustrated. Published results regarding the applicability of charge pumping technique for a study of sub-micron MOSFET interface and its degradation under various electrical stress conditions and radiation will be analyzed. The effect of geometric components on charge pumping current as well as the recent reports of single interface trap characterization in sub-micron MOSFETs will be described. The application of charge pumping technique at cryogenic temperatures and in other MOS based devices will also be included.     

Jet vapor deposition nitride processing and application to advanced CMOS devices for reduction of gate leakage current and boron penetration

The increase in gate leakage current and boron penetration are major problems for scaled gate dielectrics in advanced device technology. We have demonstrated, for the first time, reduction in gate leakage current and strong resistance to boron penetration when jet vapor deposition (JVD) nitride is used as a gate dielectric in an advanced CMOS process. JVD nitride provides a robust interface in addition to well behaved bulk properties, MOSFET characteristics and ring oscillator performance. Process optimization is discussed. Manufacturing issues remain to be addressed.     

Direct tunneling gate leakage current in transistors with ultrathinsilicon nitride gate dielectric

We present a study on the characterization and modeling of direct tunneling gate leakage current in both N- and P-type MOSFETs with ultrathin silicon nitride (Si₃N₄) gate dielectric formed by the jet-vapor deposition (JVD) technique. The tunneling mechanisms in the N- and PMOSFETs were clarified. The electron and hole tunneling masses and barrier potentials for the different tunneling mechanisms mere extracted from measured data using a new semi-empirical model. This model was used to project the scaling limits of the JVD Si ₃N₄ gate dielectric based on the supply voltages for the various technology nodes and the maximum tolerable direct tunneling gate current for high-performance and low-power applications     

Modeling early failure in integrated circuit interconnect

A model based on the random electron–atom scattering is developed to characterize the effects of defects and grain sizes on electromigration caused failure in confined sub-micron metal interconnect lines. Our study shows that lines at sub-micron widths with a more uniform microstructure exhibit a greater consistency in time to failure. Taking mean time to failure and dispersion in time to failure as criteria, the simulator predicts that grain sizes in the 0.03–0.05 μm range are optimal for 0.125 μm wide Al alloy lines. We also argue that the early failure mechanism associated with the missing metal defects is eliminated by using a homogeneous, fine-grained material. The uniformity of the structure results in a mono-modal failure distribution and contributes to increasing the built-in reliability of the interconnect lines.     

Jet vapor deposition of organic guest-inorganic host thin films for optical and electronic applications

The optical and electronic properties of organic molecules suggest application in hybrid optical-electronic integrated circuits and thin film devices, but pure, high quality, organic solid films are difficult to make. A better approach is to trap organic molecules as guests at high concentration in a durable host-guest film. Polymer, plastic, and sol-gel films can serve as hosts,^1–3but their properties are less than ideal, and the techniques for making them time consuming and involved. Here we describe our Jet Vapor Deposition (JVD) technology for trapping complex organic dyes in hard, adherent inorganic hosts. Jet vapor deposition is the only vapor deposition technique able to make organic-ceramic films, and it offers a number of advantages over other approaches. Individual organic guests can be trapped at high doping levels of several percent, and the possible combinations of guest and host are nearly unlimited. The properties of vapor deposited ceramic hosts are superior to those of polymer hosts. Deposition at high rate and room temperature enables reliable, high throughput, economic production, and renders JVD compatible with semiconductor vapor deposition technology. Here we review the principles of JVD, describe experimental applications to thin film waveguides, lasers, and chemical sensors, and discuss some of the properties of JVD host-guest materials.     

应用于深亚微米DSOI器件的埋氧层的制备

利用低剂量、低能量的SIMOX（separation by implanted oxygen）图形化技术实现了深亚微米间隔埋氧层的制备．在二氧化硅掩膜尺寸为172nm的情况下，可以得到间隔为180nm的埋氧层．通过TEM（transmission electron microscope）观察发现埋层形貌完整、界面陡峭、无硅岛及其他缺陷．该结果为DSOI（dain/source on insulator）器件向更小尺寸发展奠定了工艺基础．     

Gate dielectrics for Si,SiC, and GaN as synthesized by jet vapor deposition

The principle of the Jet-Vapor Deposition (JVD) technique for thin dielectric deposition will be introduced, the properties of JVD silicon nitride (SiN), silicon oxide, and oxide/nitride/oxide (ONO) stacks as MOS gate dielectrics for Si, SiC, and GaN will be presented.     

High-quality MNS capacitors prepared by jet vapor deposition atroom temperature

The properties of metal-nitride-Si (MNS) capacitors in which the silicon nitride layer is produced by the jet vapor deposition (JVD) technique at room temperature are reported. Despite the room-temperature deposition, the electrical properties of these devices are far better than any previously reported MNS capacitors. Especially remarkable is the low density of interface traps (D_it<5×10¹⁰ /cm²-eV near midgap). In addition, these MNS capacitors are highly resistant to damage caused by hot electrons and ionizing radiation     

FORWARD GATED-DIODE R-G CURRENT METHOD:A SIMPLE NOVEL TECHNIQUE FOR CHARACTERIZING LATERAL LIGHTLY DOPING REGION OF LDD MOSFET's

This paper presents a simple novel technique-forward gated-diode R-G current method-to determine the lateral lightly-doped source/drain (S/D) region interface state density and effective surface doping concentration of the lightly-doped drain (LDD) N- MOSFET's simultaneously. One interesting result of the numerical analysis is the direct characterization of the interface state density and characteristic gate voltage values corresponding to LDD effective surface doping concentration. It is observed that the S/D N- surface doping concentration and corresponding region's interface state density are R-G current peak position and amplitude dependent, respectively. It is convincible that the proposed method is well suitable for the characterization of deep sub-micron MOSFET's in the current ULSI technology.     

B-Spline Based, Large-Signal DC and Microwave-Model for SOI MOSFETs

We present a large/small-signal, non-quasi-static, charge conserving, SOI MOSFET modeling technique suitable for DC and high frequency circuit design. The device model is extracted from small signal microwave iso-thermal Y-parameter data and DC I–V characteristics. Low frequency dispersions associated with self-heating and floating body effects are verified to not limit the performance of this technique since it relies on both DC and transient I–V characteristics. The technique is applied to the modeling of a short-channel, partially depleted, SOI nMOSFET simulated on PISCES. The model generated is incorporated into a circuit simulator, which is used to perform large-signal transient and harmonic balance simulations. The transient I–V and gate charge extracted from the iso-thermal small-signal microwave Y-parameters, are in excellent agreement with the iso-thermal transient I–V and gate charge obtained from PISCES, respectively. The model topology is extended with a parasitic bipolar sub-circuit which automatically calculates the DC operating point for self-biasing circuits. Transient and non-linear power characterization results predicted with this model agree well with those obtained from PISCES for a wide range of input power drives. A complete electro-thermal model is proposed and verified to be able to predict temperature and transient I–V response.     

FORWARD GATED-DIODE R-G CURRENT METHOD:A SIMPLE NOVEL TECHNIQUE FOR CHARACTERIZING LATERAL LIGHTLY DOPING REGION OF LDD MOSFET’s

 This paper presents a simple novel technique-forward gated-diode R-G current method-to determine the lateral lightly-doped source/drain (S/D) region interface state density and effective surface doping concentration of the lightly-doped drain (LDD) N- MOSFET’s simultaneously. One interesting result of the numerical analysis is the direct characterization of the interface state density and characteristic gate voltage values corresponding to LDD effective surface doping concentration. It is observed that the S/D N- surface doping concentration and corresponding region’s interface state density are R-G current peak position and amplitude dependent, respectively. It is convincible that the proposed method is well suitable for the characterization of deep sub-micron MOSFET’s in the current ULSI technology.     

A case study of defects due to process marginalities in deep sub-micron technology

The difficulties in identifying the precise defect location and real leakage path is increasing as the integrated circuit design and process have become more and more complicated in and below deep sub-micron technology node. Most of the defects causing chip leakage are detectable with only one of the failure analysis (FA) tools such as liquid crystal detection (LCD) or photon emission microscope (PEM). However, due to process marginalities some defects are often not detectable with only one FA tool [Hung-Sung Lin, Wen-Tung Chang, Chun-Lin Chen, Tsui-Hua Huang, Vivian Chiang, Chun-Ming Chen. A study of asymmetrical behaviour in advanced nano SRAM devices. In: 13th IPFA proceedings; July 2006. p. 63–6; Kruseman Bram, Majhi Ananta, Hora Camelia, Eichenberger Stefan, Meirlevede Johan. Systematic defects in deep sub-micron technologies. ITC international test conference, 2004. p. 290–9.]. This paper present an example of an abnormal power consumption process related defect which could only be detected with more advanced FA tools.     

Modified Viterbi decoders for joint data detection and timingrecovery of convolutionally encoded PPM and OPPM optical signals

Two novel Viterbi decoders, known as joint Viterbi decoder (JVD) and enhanced Viterbi decoder (EVD), for synchronization and data detection are introduced and analyzed for convolutionally-encoded (CE) optical pulse-position modulation (PPM) and overlapping PPM (OPPM) channels. For the JVD algorithm, a count metric is employed to perform the Viterbi decoding in the absence of synchronization. For the EVD algorithm, a memory array is utilized to reduce the computation time of the JVD algorithm. With the aid of a previously proposed upper-bound and taking advantage of the minimal asymptotic normalized timing error (MANTE) concept, approximate performance measures for the EVD and JVD receivers are obtained     

High-quality oxide/nitride/oxide gate insulator for GaN MISstructures

We report on a SiO₂/Si₃N₄/SiO₂ (ONO) gate insulator stack deposited on GaN by jet vapor deposition (JVD) technique. Capacitors fabricated using the JVD-ONO on GaN are characterized from room temperature to 450°C using capacitance-voltage (C-V), current-voltage (I-V), AC conductance, and constant-current stress measurements. We find excellent operating characteristics over the measured range, most notably: (1) very low leakage current, (2) extremely high hard-breakdown strength, (3) low interface-trap density, and (4) low net dielectric-charge density. Moreover these performance figures remain well within acceptable limits even for operating temperatures as high as 150°C. In addition, we measure both the capture cross-section of the interface traps and the surface-potential fluctuation at the GaN/ONO interface. All results suggest that JVD-ONO is an excellent choice for a gate dielectric in GaN-based MISFETs     

LPCVD-silicon oxynitride films: interface properties

The interface properties of silicon oxynitride films prepared by low-pressure chemical vapor deposition at a temperature of 860 ° C have been investigated analyzing the capacitance–voltage and ac conductance–voltage characteristics of the metal-SiO_xN_y-silicon capacitors. Consistent results for the interface trap density have been obtained from single frequency ac conductance technique, approximation C–V method and from the interface density spectrum. The post-deposition annealing results in an improvement of the interface charge properties. The contribution of the interface traps to the estimation of the fixed oxide charge has been discussed which is important for the threshold voltage control in MOS devices.     

Numerical prediction of failure paths at a roughened metal/polymer interface

Debonding of polymer–metal interfaces often involves both interfacial and cohesive failure. This paper extends the investigation of Yao and Qu presented in [Yao Q, Qu J. Interfacial versus cohesive failure on polymer–metal interfaces in electronic packaging – effects of interface roughness. J Electr Packag 2002;124;127–34] towards a numerical fracture mechanics model that is used to quantitatively predict the relation between cohesive and adhesive failure on a metal–polymer interface. As example, an epoxy–aluminum interface is investigated. The competition between adhesive and cohesive failure depending on surface roughness parameters will be studied. Understanding of these phenomena could enable the optimization of interface properties for different applications.     

Implant dose monitoring by MOS C–V measurement

The most critical parameter for deep sub-micron MOS field effect transistors is the threshold voltage, which is highly dependent on processing specifically, the ion implanted channel dose. Monitoring the channel doping on product wafers is highly desirable and is a major issue for process engineers. MOS C–V methods are widely used for process ramp up and monitoring and MOS C–V doping profiling is an introduced method for monitoring of low dose implants. However, the failure of the depletion approximation in the near surface region implies that conventional MOS C–V measurements yield erroneous doping profiles in that region. Integrating MOS C–V doping profiles yields only a partial implant dose excluding the important near surface dose portion. Here, we report a new approach, which enables the determination of the entire implant dose, taking into account the crucial surface region. Moreover, the MOS threshold voltage can be obtained self-consistently. The method is also applicable to MOS structures with ultra thin gate oxides.