Effect of reverse substrate bias on ultra-thin gate oxide n-MOSFET degradation under different stress modes

Degradation of ultra-thin gate oxide n-MOSFET with halo structure is studied under different stress modes with the increase of reverse substrate bias. The variation of device degradation is characterized by monitoring the substrate current during stress. When the gate voltage is smaller than a critical value, the device degradation first decreases and then increases with the increase of reverse substrate voltage; otherwise, the device degradation increases continually. The critical gate voltage can be determined by measuring the substrate current variation with the increase of reverse substrate voltage.     

Trench insulated gate bipolar transistors submitted to high temperature bias stress

In this work we analyse the behavior of the Non Punch Through Trench Insulated Gate Bipolar Transistors submitted to High Temperature Gate Bias (HTGB) and High Temperature Reverse Bias (HTRB) stresses. The electric stress has been accomplished during 1200 hours at 140 °C with 0.8 V_CEmax Collector - Emitter bias (HTRB) and with V_GE = −20 V or +20 V Gate Bias (HTGB). The results show the evolution of the static parameters as threshold voltage and on-state voltage drop and of switching parameters. The aim is to constitute a database as complete as possible for the analysis and diagnosis of failure causes related to the switching devices in power conversion systems.     

Ni fully GermanoSilicide for gate electrode application in pMOSFETs with HfSiON gate dielectrics

A study on using a novel metal gate-the Ni fully GermanoSilicide (FUGESI)-in pMOSFETs is presented. Using HfSiON high-/spl kappa/ gate dielectrics and comparing to Ni fully Silicide (FUSI) devices, this paper demonstrates that the addition of Ge in poly-Si gate (with Ge/(Si+Ge)/spl sim/50%) results in: 1) an increase of the effective work function by /spl sim/ 210 mV due to Fermi-level unpinning effect; 2) an improved channel interface; 3) a reduced gate leakage; and 4) the superior negative bias temperature instability characteristics. Low-frequency noise measurement reveals a decreased 1/f and generation-recombination noise in FUGESI devices compared to FUSI devices, which is attributed to the reduced oxygen vacancies (V/sub o/)-related defects in the HfSiON dielectrics in FUGESI devices. The reduced V/sub o/-related defects stemming from Ge at FUGESI /HfSiON interface are correlated with the Fermi-level unpinning effect and the improved electrical characteristics observed in FUGESI devices.     

Effects of boron diffusion in pMOSFETs with TiN-HfSiO gate stack

Boron diffusion in TiN-HfSiO gate stack capped with polysilicon layer has been studied. SIMS analysis indicates that a significant amount of B diffused from B-doped polysilicon through TiN layer into nitrided HfSiO gate dielectrics. Grain boundaries in TiN thin film are considered a conduit of B into HfSiO. Even though most of B was stopped within HfSiO film owing to N incorporation, significant V/sub t/ shift and interface properties degradation were observed. It was found that B in HfSiO serves as positive charge and shifts pMOSFET V/sub t/ to negative side.     

Temperature accelerated gate oxide degradation under plasma-inducedcharging

Gate oxide charging during plasma processing of submicron devices becomes a serious yield and reliability concern, especially when oxide thickness and device dimensions shrink to the nanoscale region. This paper shows that wafer temperature is a crucial parameter for charging-induced oxide degradation due to plasma processing. Experimental results from plasma damaged submicron MOS transistors, namely low-level gate leakage and degraded charge-to-breakdown characteristics are analyzed from the point of view of conditions of electrical stress. Laboratory experiments simulating plasma charging, performed at 150°C, confirmed that elevated temperature during plasma processing strongly accelerates oxide degradation and even at low-level stress leads to effects observed in plasma damaged devices     

Temperature dependence of hot carrier induced MOSFET degradation at low gate bias

This paper reports a new experimental finding on the temperature dependence of the substrate current and hot carrier induced device degradation at low gate bias. It has been found that the substrate current increases and the drain current degradation is more significant for high operating temperature at low gate bias. It has been observed that the hot carrier induced performance degradation of a latch-type input buffer increases at the elevated temperature.     

Substrate bias dependence of breakdown progression in ultrathin oxide pMOSFETs

Negative substrate bias-enhanced oxide breakdown (BD) progression in ultrathin oxide (1.4 nm) pMOS is observed. The enhanced progression is attributed to the increase of hole-stress current resulting from BD-induced, channel-carrier heating. The carrier temperature extracted from the spectral distribution of hot-carrier luminescence is around 1300 K. The substrate bias dependence of post-BD hole-tunneling current is confirmed from measurement and calculation. The observed phenomenon is particularly significant to ultrathin gate oxide reliability in floating substrate (SOI) and forward-biased substrate devices.     

Pulse waveform dependence on AC bias temperature instability in pMOSFETs

In this letter, the waveform effects on the degradation enhancement of pMOSFETs under high-frequency (/spl ges/10/sup 4/ Hz) bipolar-pulsed bias-temperature (BT) stresses were systematically studied. The enhancement was found to be mainly governed by the fall time (t/sub F/) of the pulse waveform, namely, the transition time of the silicon surface potential from strong accumulation to strong inversion, rather than the pulse rise time (t/sub R/) and the pulse duty factor (D). The enhancement decreases significantly with t/sub F/ increasing, and is almost eliminated when t/sub F/ is larger than /spl sim/60 ns. This new finding is consistent with our newly proposed assumption that the recombination of free holes and trapped electrons at the SiO/sub 2//Si interface and/or near-interface states can enhance the interface trap generation.     

Method to extract parameters of power law for nano-scale SiON pMOSFETs under negative bias temperature instability

This paper proposes a fast and accurate method to extract parameters of the power law for nano-scale SiON pMOSFETs under negative bias temperature instability (NBTI), which is useful for an accurate estimation of NBTI lifetime. Experimental results show that accurate extraction of the time exponent n of the power law was obstructed by either fast trapping of minority carriers or damage recovery during measurement of threshold voltage V_th. These obstructing effects were eliminated using ΔV_ths obtained from fast and slow measurement-stress-measurement (MSM) procedures. The experimental SiON pMOSFETs had n ≈ 1/4, an activation energy E_a = 0.04 eV for the fast recoverable degradation, and E_a = 0.2 eV for the slow permanent degradation. Based on these experimental observations, a method to estimate NBTI lifetime is proposed.     

Recovery of negative bias temperature instability induced degradation of p-MOSFETs with SiON gate dielectric

This paper investigates the recovery property of p-MOSFETs with an ultra-thin SiON gate dielectric which are degraded by negative bias temperature instability (NBTI). The experimental results indicate that the recovery of the NBTI degradation occurs through an electrical neutralization of the NBTI-induced positive charges at the SiON/Si interface and in the gate dielectric. The neutralization of interface charges was a fast process occurring just after the device returned to the recovery state. The neutralization of positive charges in the gate dielectric was a slow process associated with the electron injection into the gate dielectric. Below the gate voltage for strong accumulation, the amount of recovery increased with an increase of the gate voltage. A further increase of gate voltage did not affect the amount of recovery. These experimental results indicate that the major cause of the recovery is a neutralization of the NBTI-induced positive charges by electrons instead of a hydrogen passivation of the NBTI-induced defect sites.     

Enhancement of power conversion efficiency of PTB7:PCBM-based solar cells by gate bias

We designed and fabricated poly[[4,8-bis[(2-ethylhexyl)oxy]benzo[1,2-b:4,5-b′]dithiophene-2,6-diyl] [3-fluoro-2-[(2-ethylhexyl)carbonyl] thieno[3,4-b]thiophenediyl]] (PTB7): [6,6]-phenyl-C70-butyric-acid-methyl-ester (PC₇₀BM)–based solar cells with gate electrodes, which can introduce an additional electric field within the devices just as in organic thin film transistors (OTFTs). Our proposed realize the simple and convenient modulation of electric field within the device, and power conversion efficiency (PCE) of 8.1% is reached at 2.0 V gate bias, significantly higher than the PCE of 6.8% at the case of no gate structure. By calculating the carrier mobility and the rate of exciton dissociation efficiency in detail, the role of electric field to the exciton dissociation and carrier transport was investigated, respectively. Meanwhile, the feasibility of the proposed device structure in practical application was discussed. The results suggest that such a gate structure has a great of prospects in achieving high efficiency polymer solar cells.     

Time-dependent degradation of thin gate oxide under post-oxidation high-temperature anneal

Charge to breakdown QBDhas been used to evaluate the quality of thin gate oxides for some time. It is well known that the QBDof a thin oxide degrades with subsequent high-temperature thermal cycles. This paper reports on the time-dependent degradation of an 80-Å gate oxide at various post-oxidation annealing temperatures. An empirical relation was obtained asQ_{BD} propto exp (-A(T)t)where t is annealing time, T is annealing temperature, and A is the "rate constant" for the QBDdegradation. An Arrhenius plot of A versus 1/T yields an activation energy in the range of 6-7 eV. Also reported is the observation of an increase in QBDduring short annealing time which may be related to the relaxation of built-in stress induced during the oxidation process.     

Hot-carrier-induced degradation of gate dielectrics grown innitrous oxide under accelerated aging

Gate oxides grown with partial and complete oxidation in N₂ O were studied in terms of hot-carrier stressing. The DC lifetime for 10% degradation in g_m had a 15×improvement over control oxides not grown in a N₂O atmosphere. Further improvement in g_m degradation was observed in oxides that received partial oxidation as compared with control oxides. This improvement is due to the incorporation of nitrogen that reduces strained Si-O bonds at the Si/SiO₂ interface, leading to lower interface state generation (ISG). Improvements were also observed in I_g-V_g characteristics, indicating a reduction of trap sites both at the Si/SiO₂ interface and in the bulk oxide. Improved gate-induced drain leakage (GIDL) characteristics as a function of hot-carrier stressing for partial N₂O oxides were observed over control oxides. However, severe drain leakage that masked GIDL was observed on pure N ₂O oxides and is a subject for further study     

Intermodulation in high-frequency bipolar transistor integrated-circuit mixers

Intermodulation in bipolar-transistor double-balanced mixers at high frequencies is analyzed theoretically and by computer simulation. The dependence of the distortion on a relatively few normalized parameters is illustrated. Computed results are compared with measurements on a monolithic quad mixer.     

Time-dependent degradation due to negative bias temperature instability of p-MOSFET with an ultra-thin SiON gate dielectric

This paper presents the time-dependence of the negative bias temperature instability (NBTI) degradation of p-MOSFETs with an ultra-thin silicon oxynitride gate dielectric. The concentrations of nitrogen in the gate dielectric were approximately 3% and 10%. The device with 10% nitrogen concentration had unique time-dependent degradation characteristics due to the nitrogen enhanced NBTI effect. It degraded significantly just after application of an NBTI stress. After this initial degradation, a fast and slow degradation followed in sequence. The initial, fast, and slow degradations appear to be associated with the deep donor effect of nitrogen, the diffusion of ionic and neutral hydrogen combined with Si-H bond breaking, and the diffusion of neutral hydrogen combined with O-H bond breaking, respectively. Owing to the slow down of the NBTI degradation after the initial and fast degradations, the lifetime for the device with 10% nitrogen concentration was three times longer than that with 3% nitrogen concentration.     

具有积累层沟道的槽栅IGBT结构

提出了一种具有积累层沟道的槽栅IGBT结构。仿真结果表明：在阻断电压为1200V,集电极电流密度为100 A/cm2,温度分别为300K和400K下的情况下,积累层沟道槽栅IGBT的正向压降分别为1.5V 和2V而常规槽栅IGBT分别为1.7V和2.4V。新结构比常规槽栅IGBT具有更低的开态压降和更大的正向安全工作区。文中同时分析了积累层沟道槽栅IGBT的阻断特性和关断特性。     

Atomic modeling of nitrogen neighboring effect on negative bias temperature instability of pMOSFETs

In this letter, further evidence from atomic modeling is presented to support the proposed nitrogen neighboring effect, which explains the two distinct regimes in the dependence of negative bias temperature instability (NBTI) degradation on the interfacial nitrogen concentration N/sub int/ (i.e., the dependence for N/sub int/>8 at. % is stronger than that for N/sub int/<8at. %). Our calculations clearly show that the enhancement of the NBTI degradation by nitrogen becomes stronger when the number of neighboring N atom increases with increasing the N/sub int/. In addition, the role of nitrogen in NBTI is also examined in terms of the electronegativity and atomic charge distribution. This letter clearly suggests that the N neighboring effect is detrimental to future generations of MOS devices that require higher N/sub int/ for the gate oxide.     

Evidence for bulk trap generation during NBTI phenomenon in pMOSFETs with ultrathin SiON gate dielectrics

Negative bias temperature instability (NBTI) of pMOSFETs with direct-tunneling SiON gate dielectrics was studied in detail. By investigating the effects of applying positive gate bias on pMOSFETs after exposure to NBT stress, the generation of bulk charge traps in the gate dielectrics during NBTI was clearly demonstrated. In particular, it was found that a positive charge generated by negative bias temperature stress (NBT stress) can be neutralized and that the neutralized site can return to the positive state. We consider that the bulk trap is due to hydrogen atoms released from the interface between the SiON gate dielectric and the Si substrate (and this is what has conventionally been considered a positive fixed charge). Moreover, the bulk trap generation was shown to give rise to stress-induced leakage current.     

The effect of annealing temperatures on self-aligned replacement (damascene) TaCN-TaN-stacked gate pMOSFETs

In this paper, we report the first self-aligned replacement (Damascene) TaCN-TaN-stacked gate electrode pMOSFETs. The high-temperature (>1000/spl deg/C) implant activation anneal was done prior to the metal electrode deposition. After the fabrication was completed, the transistors were then annealed at lower temperatures (300/spl deg/C-600/spl deg/C), which might affect the critical device parameters, such as subthreshold slope, threshold voltage, gate leakage, on, and off currents. Our data show that TaCN is a promising material for the metal-gate pMOSFETs due to the suitable metal work function and good thermal stability up to 500/spl deg/C, which is much higher than the highest temperature required by the backend very large-scale integration process.     

Negative gate bias instability in polycrystalline silicon TFT's

Degradation of the device characteristics of poly-Si TFT's are seen following negative gate bias stress at elevated temperatures. The degradation has two components, One component is the trapping of holes in the gate oxide; this is a similar phenomenon to the so called `negative bias instability' seen in mono-Si MOSFETs. The other component is state formation and removal in the poly-Si bulk, or at the poly-Si-SiO₂ interface, and this is similar to that seen in αSi:H TFT's. The states formed are not the same as those produced by hot carrier stressing