Modeling integrated injection logic (I/SUP 2/L) performance and operational limits

A new user-oriented I/SUP 2/L macromodel is presented which models I/SUP 2/L performance and predicts operational limits. The macromodel includes n-p-n current gain falloff and injector transport efficiency falloff at both low and high operating currents. Lateral current transfer between adjacent gates may be included in the macromodel. A straightforward parameter measurement scheme is given which requires only simple test gates. The macromodel is easily implemented in commonly available circuit simulators such as SPICE. The modeling of I/SUP 2/L dynamic behavior is demonstrated with computer simulations of a five-stage ring oscillator and `D' flip-flop, where typically 15 percent or better agreement with measured data has been achieved. It is also shown that operational limits of I/SUP 2/L circuits can be accurately predicted. Computer simulation of I/SUP 2/L performance as a function of temperature is discussed. The macromodel is well suited for worst case analysis of I/SUP 2/L, and the close correspondence of the macromodel's parameters to gate geometry makes it possible to use the macromodel to approximately simulate performance changes with layout and geometry variations.     

(MI)/SUP 2/L: multiinput-multioutput integrated injection logic

The (MI)/SUP 2/L structure will be discussed, which is a combination of CHL/CHIL and I/SUP 2/L, taking advantage of ion implantation. It provides improved speed-power product and functional density compared to conventional I/SUP 2/L schemes. The gate consists of a lateral n-p-n transistor with intermediate collectors and a Schottky inverter. The device fabrication is fully compatible with standard bipolar processes for analog circuits. The approach is applied to a standard bipolar process of 6 /spl mu/m epi thickness and 35 V breakdown voltage. The results obtained are a minimum power-delay product of 0.07 pJ and a minimum delay of 17 ns at 0.38 pJ. The improved device parameters, packing density, and design flexibility are discussed with the experimental results of test circuits, including a D-type frequency divider and MS flip-flop.     

Role of the external n-p-n base region on the switching speed of integrated injection logic (I/SUP 2/L)

Two-dimensional simulation and charge control principles have been applied to reveal the factors which determine the minimum delay of an integrated injection logic (I/SUP 2/L) gate, and experimental verifications are carried out. Using a numerical analysis this paper shows that important factors in improving the speed of an I/SUP 2/L gate are reducing the amount of minority charge stored in the external base of the n-p-n transistor and use of a heavily doped emitter. It is, therefore, necessary that the concentration in the external base is increased as high as possible and that the diffusion depth is controlled with good accuracy. Improvement in speed by a factor of 2 is experimentally realized as the simulation predicts. The heavily doped external base improves upward current gain and reduces base resistance, achieving a high fan-out capability.     

Effects of oxide isolation on propagation delay in integrated injection logic (I/SUP 2/L)

Effects of oxide isolation on current gains, signal swing, and propagation delay time of an I/SUP 2/L gate at high dissipation levels are discussed in terms of the backward injection of the p-n-p transistor, the magnitude of which is reduced by the isolation. The reduction enhances the degree of saturation. On the other hand, it causes a larger collector current which enables a rapid discharge of the stored charge. These competing effects given an optimum condition for which the analytical expression is obtained.     

Effects of gate geometry on propagation delay of integrated injection logic (I/SUP 2/L)

The effects of gate geometry on the propagation delay have been investigated for I/SUP 2/L gates with a self-aligned double-diffusion injector (S/SUP 2/L). To improve the switching speed of the I/SUP 2/L gate, the stored charge in the upside-down operated n-p-n transistor in the gate should be minimized. Following this principle, one can straightforwardly find that the reduction of the stored charges in the internal n-p-n base region and in the lateral p-n-p base region is the step to be taken for the further improvement of the speed. This can be realized by simply contracting the geometry of the gate. The minimum delay time realized in the gate was 3.2 ns/gate. Assuming that capabilities of processing the devices with 1-/spl mu/m accuracy become available, it is predicted that 1 ns/gate delay time can be realized with an improved S/SUP 2/L gate.     

An integrated injection logic (I/SUP 2/L) macromodel including lateral and current redistribution effects

An integrated logic (I/SUP 2/L) macromodel for computer simulation of logical configurations of I/SUP 2/L gates is presented. The macromodel is synthesized from the familiar Ebers-Moll equivalent circuit which permits compatibility with numerous presently available circuit simulators. Measurement procedures are described for the complete and self-consistent set of electrical parameters required for macromodel definition. A five-stage ring oscillator is computer simulated to demonstrate the application of the macromodel. Lateral current transfer (LCT) between adjacent gates and injector current redistribution (ICR) effects are shown to reduce gate propagation delay times. When both effects are included, the macromodel produces an agreement between computer simulated and experimental results of better than 10 percent. A ring oscillator example illustrates the use of the macromodel to provide physical insight into the layout sensitivity of I/SUP 2/L.     

Realization of a multivalued integrated injection logic (MI/SUP 2/L) full adder

A multivalued integrated injection logic scheme and its application to the realization of a full adder is described in this correspondence. The integrated full adder is implemented and fabricated using V-groove isolated I/SUP 2/L technology. Results obtained on the experimental structures indicate that the multivalued full adder offers an increase in functional density while retaining approximately the same area x delay product as a binary full adder at identical power levels.     

Schottky I/SUP 2/L (substrate fed logic)-an optimum form of I/SUP 2/L

A modified form of Schottky I/SUP 2/L (originally called substrate fed logic) has been developed, differing from the earlier process mainly in the extrinsic n-p-n base profile. Heavier boron doping in this region has led to reduced charge storage so that minimum delays as low as 8 ns/gate at a power of 50 /spl mu/W are now achieved in ring oscillator circuits. The reduced minimum delay also applies to more complex gates, as demonstrated by a D-type flip-flop which operated at 20 MHz with a power dissipation of 70 /spl mu/W/gate. The excellent yield and high packing density which have been obtained on trial circuits demonstrate that the process is capable of very large scale integration.     

Computer-aided design of large-scale integrated I/SUP 2/L logic circuits

Thanks to the simple, regular structure of its basic gates, integrated injection logic (I/SUP 2/L) is particularly suited to automated design (CAD) procedures for evolving large-scale integrated digital circuits. This paper describes CAD methods for I/SUP 2/L circuits that permit the use of existing, tried CAD programs, and illustrates their application in the design of the I/SUP 2/L basic gate, computer simulation of I/SUP 2/L logic circuits, interconnection pattern generation, and preparation of a final layout plan.     

High-performance integrated injection logic: a microprogram sequencer built with I/SUP 3/L

A microprogram sequencer is described. Its role in a systems environment is indicated. Functional details of the device including its instruction set are given. A newly developed technology isoplanar integrated injection logic (I/SUP 3/L) is discussed. Emphasis is placed on methods to achieve the required high performance. Details of the device structure and layout techniques are included. The resulting speed performance is indicated and general parameters are displayed.     

A new high speed I/SUP 2/L structure

A new improved I/SUP 2/L structure is discussed which has been shown to operate at high speeds with large fan-out capabilities while retaining low power operation. The new `up-diffused' structure is fabricated in such a fashion that Schottky diodes can be readily incorporated. With the addition of Schottky clamps between the collector and base of the n-p-n switching transistor, gate delays as low as 2.5 ns have been achieved.     

Complementary transistor-transistor logic (CT/SUP 2/L)-An approach to high-speed micropower logic

A new approach to micropower integrated circuits has been developed and is called complementary transistor-transistor logic (CR/SUP 2/L). This logic combines the inherent low standby power of a complementary inverter with the high speed of the T/SUP 2/L-type input. Results of the monolithic fabricated circuits are presented.     

An investigation of the intrinsic delay (speed limit) in MTL/I/SUP 2/L

Experimental devices have been fabricated with different epitaxial thicknesses to find out to what extent the charge storage can be reduced by shallow epitaxy. Such a shallow-epitaxy device is investigated using computer simulation. The injection model is used, into which new charge storage parameters are introduced. The majority of the stored mobile charge is associated with the bottom junction of the n-p-n transistor part, while the charges in the p-n-p's intrinsic base are minor. However, the lateral p-n-p transistor contributes to the intrinsic delay by its high level-injection current gain falloff. Furthermore, the significance of high intrinsic base sheet resistance of the n-p-n transistor for high speed is pointed out. A device is laid out that assumes only existing technologies, yet in the simulation yields intrinsic delays as low as 2 ns for a fan-out of 4.     

Schottky I/SUP 2/L

Schottky I/SUP 2/L uses the principles of integrated injection logic (I/SUP 2/L/MTL) and the properties of ion implantation to obtain improved performance at the same densities as conventional I/SUP 2/L. Schottky diodes are formed in the multicollectors of the switching transistor and reduce the signal swing, thus improving the power delay efficiency. An increase in the intrinsic speed limit is also feasible. The Schottky I/SUP 2/L structure and characteristics are described and contrasted with conventional I/SUP 2/L. A model which is useful for its design is discussed. Integrated test structures which provide direct comparison between conventional and Schottky I/SUP 2/L performance have been fabricated. The experimental results demonstrate a factor of 2 improvement in power-delay efficiency of Schottky I/SUP 2/L over conventional I/SUP 2/L.     

A mixed EFL/I/SUP 2/L digital telecommunication integrated circuit

A bipolar integrated circuit has been designed as part of a VLSI upgrade of an existing digital switching circuit. The chip exploits the OXIL (oxide isolated) process which makes it possible to use both high-gain `up' and `down' devices, for I/SUP 2/L (integrated injection logic) and EFL (emitter function logic) respectively. This allowed the circuit designers to tailor power consumption, circuit speed, and gate density as needed. In particular, the high-speed properties of EFL were utilized in the control section to provide accurate timing signals and satisfy tight propagation delay requirements in the register section. I/SUP 2/L, because of its greater density and low power, was used in the gate-intensive register sections. Another novel feature is the treatment of bus lines (up to 250 fanout) such as clock, clear, etc., in the I/SUP 2/L sections. The common multiline I/SUP 2/L drive problem has been overcome by using high-drive translators from EFL circuitry and a single pullup resistor per bus line to provide switched currents to all gates on that line.     

Schottky collector I/SUP 2/L

A new I/SUP 2/L gate which promises increased packing density and increased speed is discussed. It incorporates the use of a Schottky contact as the collector of the vertical switching transistor of an I/SUP 2/L gate. Calculations and experiments show that the problems associated with this structure (low downward beta) can be controlled by limiting both the fan-out and the fan-in. Delays of less than 10 ns have been measured using a 10-/spl mu/m technology and a 6-/spl mu/m-thick epi. A divide-by-two circuit with a maximum toggle frequency of 12.5 MHz has been built. The additional fan-in limitation of the logic is described.     

Stacked I/SUP 2/L structures

In LSI environments where the available power supply is greater than 800 mV, integrated injection-logic's (I/SUP 2/L's) inherent high level of power efficiency is restored by stacking. The use of stacked I/SUP 2/L structures in the realization of random logic and regular arrays is studied. Two approaches are considered and compared. Design examples are given including adders, a seven segment display decoder, and a control logic function. The degradation of the speed of operation because of the stacking is analyzed and experimentally verified.     

Scaling I/SUP 2/L for VLSI

Scaling integrated injection logic for high-density VLSI circuits is discussed. The basic principles governing the operation of an I/SUP 2/L device and the impact of specific process/design changes on performance are reviewed. A procedure for scaling I/SUP 2/L devices with geometries >1 /spl mu/m is described and examples of scaled devices fabricated with e-beam slice writing techniques are given. It is shown that the I/SUP 2/L gate propagation delay can be scaled over the entire range of operating currents through a combination of scaling and sizing. The physical limitations that apply to submicron geometries are summarized and the performance attainable with a submicron device design is predicted.     

I/SUP 2/L DC functional requirements

Factors controlling the DC operational limits of integrated injection logic (I/SUP 2/L) imposed by the interaction between the inverse n-p-n switching transistors and the lateral p-n-p transistor formed with the injector are discussed. The operational limit is shown to be a function only of structural and doping level parameters. An upper limit on epitaxial resistivity is shown to result.     

Considerations for high-speed and analog-circuit-compatible I/SUP 2/L and the analysis of Poly I/SUP 2/L

Expressions are derived for minimum propagation-delay time and DC operational conditions in the I/SUP 2/L circuit configuration, and are applied to several kinds of I/SUP 2/L limitations. 1) Ultimately achievable (roughly 0.34 ns, fan-out of 2) and reasonably expected minimum propagation-delay values (0.75-1.0 ns considering simple n-p-n limitations) are estimated. 2) Speed improvements of the standard I/SUP 2/L structure via doping level adjustment is shown to be minimal (it is primarily useful for ensurance of DC operation). 3) Requiring analog compatibility further constrains performance; a figure of merit of about 1 to 2 V/ns is derived and experimentally confirmed for the product of analog device BV/SUB CBO/ and I/SUP 2/L speed for standard epitaxial I/SUP 2/L processing. Radical techniques using dual buried layers, dual epitaxial layers, or Poly I/SUP 2/L offer considerably enhanced performance by attacking the parameter with primary leverage on these tradeoffs: base-to-buried layer spacing W/SUB epi/. Analysis of Poly I/SUP 2/L reveals specific advantages.