Approaches to extra low voltage DRAM operation by SOI-DRAM

The newly designed scheme for a low-voltage 16 MDRAM/SOI has been successfully realized and the functional DRAM operation has been obtained at very low supply voltage below 1 V. The key process and circuit technologies for low-voltage/high-speed SOI-DRAM will be described here. The extra low voltage DRAM technologies are composed of the modified MESA isolation without parasitic MOS operation, the dual gate SOI-MOSFETs with tied or floating bodies optimized for DRAM specific circuits, the conventional stacked capacitor with increased capacitance by thinner dielectric film, and the other bulk-Si compatible DRAM structure. Moreover, a body bias control technique was applied for body-tied MOSFETs to realize high performance even at low voltage. Integrating the above technologies in the newly designed 0.5-μm 16 MDRAM, high-speed DRAM operation of less than 50 ns has been obtained at low supply voltage of 1 V     

Design of ultrahigh-speed low-voltage CMOS CML buffers and latches

A comprehensive study of ultrahigh-speed current-mode logic (CML) buffers along with the design of novel regenerative CML latches will be illustrated. First, a new design procedure to systematically design a chain of tapered CML buffers is proposed. Next, two new high-speed regenerative latch circuits capable of operating at ultrahigh-speed data rates will be introduced. Experimental results show a higher performance for the new latch architectures compared to the conventional CML latch circuit at ultrahigh-frequencies. It is also shown, both through the experiments and by using efficient analytical models, why CML buffers are better than CMOS inverters in high-speed low-voltage applications.     

导通于放大状态的高速低压TTL与非门

本文在分析低压TTL门按传统方式实现高速的困难之后,首先提出一个利用射极跟随器钳位和反馈电路组成的导通于放大状态低压TTL电路,并设计出延迟时间tpd＜1ns的高速低压TTL与非门.接着进行电路分析和参数估算.用计算机模拟证明理论和电路的正确性.     

The SDC cell-A novel design methodology for high-speed arithmeticmodules using CMOS/BiCMOS precharged circuits

The shielded dynamic complex-gate (SDC) cell is a cell-based design methodology for generating high-speed modules or macrocells using precharged circuit technology. In order to achieve ultrafast operation, a BiCMOS precharged circuit has been developed. This circuit is about 1.5 to 2.0 times faster than the conventional CMOS precharged circuit. The effect of alpha-particle injection under low-voltage operation has been studied, and CMOS/BiCMOS precharged circuits with alpha-particle-induced noise suppression have been proposed. A 32-b arithmetic and logic unit (ALU) utilizing a BiCMOS SDC cell designed and fabricated with 0.5-μm BiCMOS technology is discussed. The application of the SDC cell design to a mainframe execution unit (parallel adder) is also described     

Low-voltage fourth-order CMOS sigma-delta modulator implementation

A low-voltage, high-speed, fourth-order sigma-delta modulator implementation is presented. The low-voltage and high-speed operation are obtained by using a novel combination of architectural features, proper circuit structure selections, specific clocking strategies, and efficient circuit optimisation algorithms. Measurement results from fabricated CMOS chip prototypes show a good match with simulations     

A 6-bit 3.5-GS/s 0.9-V 98-mW Flash ADC in 90-nm CMOS

A 6-bit 3.5-GS/s flash ADC is reported. A load circuit with a clamp diode and a replica-biasing scheme is developed for low-voltage and high-speed operation. An acceleration capacitor is introduced for high-speed overdrive recovery of a comparator. An averaging and interpolation network is employed in this ADC. The interpolation factor is optimized considering random offset, active area, and systematic offset to realize low offset and small active area. The ADC is fabricated in a 90-nm CMOS process and occupies 0.15 mm². It consumes 98 mW with a 0.9-V power supply. With Nyquist input, SNDR and SFDR at 3.5 GS/s are 31.18 dB and 38.67 dB, respectively.     

A new true-single-phase-clocking BiCMOS dynamic pipelined logicfamily for high-speed, low-voltage pipelined system applications

New true-single-phase-clocking (TSPC) BiCMOS/BiNMOS/BiPMOS dynamic logic circuits and BiCMOS/BiNMOS dynamic latch logic circuits for high-speed dynamic pipelined system applications are proposed and analyzed. In the proposed circuits, the bootstrapping technique is utilized to achieve fast near-full-swing operation. The circuit performance of the proposed new dynamic logic circuits and dynamic latch logic circuits in both domino and pipelined applications are simulated by using HSPICE with 1 μm BiCMOS technology. Simulation results have shown that the new dynamic logic circuits and dynamic latch logic circuits in both domino and pipelined applications have better speed performance than that of CMOS and other BiCMOS dynamic logic circuits as the supply voltage is scaled down to 2 V. The operating frequency and power dissipation/MHz of the pipelined system, which is constructed by the new clock-high-evaluate-BiCMOS dynamic latch logic circuit and clock-low-evaluate-BiCMOS (BiNMOS) dynamic latch logic circuit, and the logic units with two stacked MOS transistors, are about 2.36 (2.2) times and 1.15 (1.1) times those of the CMOS TSPC dynamic logic under 1.5-pF output loading at 2 V, respectively. Moreover, the chip area of these two BiCMOS pipelined systems is about 1.9 times and 1.7 times as compared with that of the CMOS TSPC pipelined system. A two-input dynamic AND gate fabricated with 1 μm BiCMOS technology verifies the speed advantage of the new BiNMOS dynamic logic circuit. Due to the excellent circuit performance in high-speed, low-voltage operation, the proposed new dynamic logic circuits and dynamic latch logic circuits are feasible for high-speed, low-voltage dynamic pipelined system applications     

Novel Viterbi decoder VLSI implementation and its performance

An advanced, high-speed, and universal-coding-rate Viterbi decoder VLSI implementation is presented. Two novel circuit design schemes have been proposed: scarce state transition (SST) decoding and direct high-coding-rate convolutional code generation and variable-rate decoding. SST makes it possible to omit the final decision circuit and to reduce the required path memory length without degrading error probability performance. Moreover, the power consumption of the SST Viterbi decoder is significantly reduced when implemented as a CMOS device. These features overcome the speed limits of high-speed and high-coding-gain Viterbi decoder VLSIs in the rate one-half mode imposed by the thermal limitation. The other Viterbi decoding scheme makes it possible to realize a simple and variable coding-rate forward-error-correction circuit by changing only the branch metric calculation ROM tables. By employing these schemes, high-speed (25-Mb/s) and universal-coding-rate Viterbi decoder VLSIs have been developed     

A 1.5-V differential cross-coupled bootstrapped BiCMOS logic forlow-voltage applications

Two new bipolar complementary metal-oxide-semiconductor (BiCMOS) differential logic circuits called differential cross-coupled bootstrapped BiCMOS (DC²B-BiCMOS) and differential cross-coupled BiCMOS (DC²-BiCMOS) logic are proposed and analyzed. In the proposed two new logic circuits, the novel cross-coupled BiCMOS buffer circuit structure is used to achieve high-speed operation under low supply voltage. Moreover, a new bootstrapping technique that uses only one bootstrapping capacitor is adopted in the proposed DC²B-BiCMOS logic to achieve fast near-full-swing operation at 1.5 V supply voltage for two differential outputs. HSPICE simulation results have shown that the new DC²B-BiCMOS at 1.5 V and the new DC²-BiCMOS logic at 2 V have better speed performance than that of CMOS and other BiCMOS differential logic gates. It has been verified by the measurement results on an experimental chip of three-input DC²B-BiCMOS XOR/XNOR gate chain fabricated by 0.8 μm BiCMOS technology that the speed of DC²-BiCMOS at 1.5 V is about 1.8 times of that of the CMOS logic at 1.5 V. Due to the excellent circuit performance in high-speed, low-voltage operation, the proposed DC²B-BiCMOS and DC²-BiCMOS logic circuits are feasible for low-voltage, high-speed applications     

Low-voltage reduced complexity cells for MOS translinear loops

A novel bias scheme for realizing low-voltage second-order translinear loops is introduced in this paper. The provided design examples include current geometric-mean, squarer/divider, and multiplier/divider cells. The performed comparison shows that the derived analog signal processing blocks offer reduced circuit complexity and improved performance, compared with the corresponding already published counterparts.     

全差分BiCMOS采样/保持电路仿真设计

在全差分折叠式共栅-共源运放的基础上,设计了一款BiCMOS采样/保持电路。该款电路采用输入自举开关来提高线性度,同时设计的高速、高精度运放,其建立时间tS只有1.37 ns,提升了电路的速度和精度。所设计的运放中的双通道共模反馈电路使共模电压稳定输出时间tW约达1.5 ns。采用SMIC公司的0.25μmBiCMOS工艺参数,在Cadence Spectre环境下进行了仿真实验,结果表明,当输入正弦电压频率fI为10 MHz、峰-峰值UP-P为1 V,且电源电压VDD为3 V、采样频率fS为250 MHz时,所设计的采样/保持电路的无杂散动态范围SFDR约为-61 dB,信噪比SNR约为62 dB,整个电路的功耗PD约为10.85 mW,适用于10位低压、高速A/D转换器的设计。     

Low-voltage high-speed Schmitt trigger and compact window comparator

Gates with input hysteresis are often necessary in circuits operating in noisy environments. Described is a very simple CMOS Schmitt trigger circuit, well suited for low-voltage and high-speed applications. The circuit also allows the construction of a very compact window comparator.     

A High-Speed Low-Voltage Phase Detector for Clock Recovery From NRZ Data

A novel topology of phase detector (PD) for applications in clock recovery systems from nonreturn-to-zero data is presented in this paper. The PD operates directly on the data stream, without requiring preprocessing, and behaves like a sampling-type PD, providing a sinusoidal phase characteristic. The triple-tail cell principle is exploited to obtain a circuit topology suitable to low-voltage high-speed applications, with a very simple structure and thus limited jitter generation. A model is proposed to understand circuit behavior and optimize its design. The PD has been used in a clock-and-data recovery circuit for 10-Gb/s optical communications, and measurements in agreement with SONET specifications are reported.     

用于CDR电路的相位插值选择电路设计

时钟数据恢复电路是高速多通道串行收发系统中接收端的关键电路,其性能的优劣直接影响了整个系统的功能.描述了双环时钟数据恢复电路利用相位正交的参考时钟进行工作的原理,分析了传统的正交时钟产生方案,提出一种新的相位插值-选择方案并给出了CMOS电路实现.在SMIC 0.18 μm CMOS工艺下采用Cadence公司的仿真工具Spectre进行了晶体管级验证,结果显示,利用该电路恢复出来的时钟对数据进行重定时,能较好地消除传输过程中积累的抖动,有效地提高了输入抖动容限.     

Charge-transferred presensing, negatively precharged word-line, and temperature-insensitive power-up schemes for low-voltage DRAMs

A 256-Mb SDRAM is implemented with a 0.12-/spl mu/m technology to verify three circuit schemes suitable for low-voltage operation. First, a new charge-transferred presensing achieves fast stable low-voltage sensing performance without additional bias levels required in conventional charge-transferred presensing schemes. Second, a negative word-line scheme is proposed to bypass the majority of discharging current to VSS. Without switching signals, main discharging paths are automatically switched from VSS to VBB2 in response to the voltage of each discharging node itself. Finally, to initialize internal nodes during power-up, a temperature-insensitive power-up pulse generator is also proposed. The temperature coefficient of the setup voltage is adjustable through optimization of circuit parameters.     

Ku波段固态高速脉冲功率放大器的设计与实现

提出一种Ku波段固态高速脉冲功率放大器的设计方案.通过分析PHEMT器件模型.精心设计GaAs PHEMT功放管的驱动电路和偏置电路,分模块给出了整个系统的实现方法,并提供主要参数的测试结果.该功率放大器的脉冲功率信号上升、下降沿时间为4 ns,开关隔离度达70 dB.系统在调制响应速度、隔离度和稳定性方面的优良性能验证了该设计的可行性.     

Design techniques for low-voltage high-speed pseudo-differential CMOS track-and-hold circuit with low hold pedestal

A low-voltage pseudo-differential double-sampled track-and-hold circuit with low hold pedestal based on the Miller-effect scheme is proposed. Rail-to-rail operation of bootstrapped switches allows the low-voltage T/H circuit implementation. Simulation results confirm that the proposed circuit is effective in low-voltage applications with low hold pedestal.     

Chip layout design of a Josephson LSI circuit for examininghigh-speed operability by using a standard cell automatic placement androuting technique

A chip layout design technique for a high-speed Josephson LSI circuit using an automatic placement and routing technique with a standard cell method has been developed. A chip layout design of a Josephson LSI circuit with 1500 gates for examining high-speed operability with a 1 GHz clock frequency has been successfully obtained. Related to high-frequency power on a high-speed Josephson LSI circuit, a dividing method for a circuit and a balancing method for power loads are proposed     

A novel ±0.8 V high-performance voltage-tunable CDTA with enhanced bandwidth

In this article, we propose a novel high-performance complementary metal oxide semiconductor (CMOS) current differencing transconductance amplifier (CDTA) with a transconductance gain (G_M) that can be linearly tuned by a voltage. By using a high-speed, low-voltage, cascaded current mirror active resistance compensation technique, the proposed CDTA circuit exhibits wide frequency bandwidths, high current tracking precisions as well as large output impedances. The linear-tunable G_M of the CDTA is designed with the use of linear composite metal oxide semiconductor field-effect transistor as basic cells in the circuit. Combining these two approaches, several design concerns are studied, including: impedance characteristic, tracking errors, offset and linearity and noise. The prototype chip with a 0.25 mm² area is fabricated in a GlobalFoundries’0.18 μm CMOS process. The simulated results and measured results with ±0.8 V DC supply voltages are presented, and show extremely wide bandwidths and wide linear tuning range. In addition, a fully differential band-pass filter for a high-speed system is also given as an example to confirm the high performance of the proposed circuit.     

Low-voltage, high-speed CMOS analog latched voltage comparator using the “flipped voltage follower” as input stage

The design and characterization of a low-voltage, high-speed CMOS analog latched voltage comparator based on the flipped voltage follower (FVF) cell and input signal regeneration is presented. The proposed circuit consists of a differential input stage with a common-mode signal detector, followed by a regenerative latch and a Set-Reset (S-R) latch. It is suitable for successive-approximation type’s analog-to-digital converters (ADC), but can also be adapted for use in flash-type ADCs. The circuit was fabricated using 0.18 μm CMOS technology, and its measured performance shows 12-bit resolution at 20 MHz comparison rate and 1 V single supply voltage, with a total power consumption of 63.5 μW.