CMOS锁相环电路

本文论述了一种CMOS的数字频率变换锁相环电路,内部由电流控制延迟单元和施密特整形电路组成的压控振荡器、鉴频鉴相器、电荷泵滤波器及分频电路组成.文中从原理及实用设计的角度给出了论述,着重讨论了系统的稳定性、收敛速度与稳态误差.     

Quasi-Optimum Digital Phase-Locked Loops

Quasi-optimum digital phase-locked loops (DPLL) are derived utilizing nonlinear estimation theory. Nonlinear approximations are employed to yield realizable loop structures. Baseband equivalent loop gains are derived, which, under high signal-to-noise ratio conditions may be calculated off line. Additional simplifications are made that permit the application of the Kalman filter algorithms to determine the minimum mean-square error (MSE) loop filter. Consideration is given to sampling rate and implementation requirements. Performance is evaluated by a theoretical analysis and by simulation. Theoretical and simulated results are discussed and a comparison to analog results is made.     

Voltage Pump Phase-Locked Loops

This paper is concerned with the phase-locked loop with Voltage Pump Phase Frequency Detector (VPPFD) and resolves the differences in explanation about its somehow peculiar behavior appearing in the literature.     

A CMOS Low-Dropout Regulator With Current-Mode Feedback Buffer Amplifier

Current feedback amplifiers (CFAs) provide fast response and high slew rate with Class-AB operation. Fast response, low-dropout regulators (LDRs) are critical for supply regulation of deep-submicron analog baseband and RF system-on-chip designs. An LDR with an CFA-based second stage driving the regulation field-effect transistor is presented. The low dropout (LDO) achieves an output noise spectral density of 67.7 nV radicHz, and PSR of 38 dB, both at 100 kHz. In comparison to an equivalent power consumption voltage feedback buffer LDO, the proposed CFA-based LDO settles 60% faster, achieving 0.6- settling time for a 25-mA load step. The LDO with CFA buffer is designed and fabricated on a 0.25- CMOS process with five layers of metal, occupying 0.23- silicon area.     

Burst Synchronization of Phase-Locked Loops

Locking a phase-locked loop (PLL) with a sinusoid that is 100-percent AM modulated by a low-duty cycle square wave (i.e., comes in bursts) is an old and well-known technique. Despite this, certain aspects of the technique have not been systematically considered. One of the most important aspects is how to avoid sidelockan undesired mode where the loop locks to a frequency other than the sinusoid's frequency. In this paper, we explain how sidelock arises, how it can be avoided and how to provide a good lock while still avoiding sidelock. Throughout the paper our emphasis is on the situation, that is usually not considered, where the sinusoid's frequency can be considerably different than the center frequency of the voltagecontrolled oscillator (VCO).     

Current-Mode Phase-Locked Loops— A New Architecture

This brief introduces current-mode phase-locked loops (PLLs). The proposed current-mode PLLs differ from conventional voltage-mode PLLs by replacing their RC loop filter with a RL loop filter, eliminating the need for large on-chip capacitors. The large inductance of the current-mode loop filter is obtained from CMOS active inductors, taking the advantage of their large and tunable inductance and small silicon area. Both types I and II current-mode PLLs are introduced. Implemented in TSMC 0.18-mum CMOS technology, the simulation results of a 3-GHz current-mode PLL demonstrate that the PLL has the lock time 50 ns, silicon area 2800 mum², dc power consumption 12.2 mW, and phase noise of -84.5 dBc at 1-MHz frequency offset and the maximum -74 dBc reference spurs     

Quantization Effects in All-Digital Phase-Locked Loops

This brief analyzes the impact of the quantization noise sources in all-digital phase-locked loops (ADPLLs), recently employed as frequency synthesizers. In general, the in-band phase noise is not only caused by the phase quantization of the time-to-digital converter, but also by the frequency quantization of the digitally controlled oscillator (DCO). The delta-sigma modulator placed at the DCO input refines the frequency quantization and adds another source of in-band PLL noise. Interestingly, the higher the modulator order, the higher this source of in-band phase noise. A method for the estimation of all the quantization noise contributors is provided, which is proven by mixed-mode simulations.     

On Frequency Sweeping in Phase-Locked Loops

The following experimental study describes a new representation of the behavior that a second-order phase-locked loop (PLL) shows in the presence of linear frequency sweeping. This paper differs from previously published results in that it presents a general experimental analysis of the PLL during a sweep which is independent of a specific in-lock detection. Hence, the results represent a useful tool for the design of an in-lock detector in PLL sweep systems.     

Concurrent Dual-Frequency Oscillators and Phase-Locked Loops

A dual-frequency oscillator employing a fourth-order tank is shown to have the ability to generate simultaneous oscillations at two frequencies. A nonlinear analysis to determine the steady-state and transient behavior of this oscillator is presented. Further, the phase-noise expression for the dual-frequency oscillator is derived and compared with that of a single-frequency oscillator. A dual-loop phase-locked loop (PLL) is designed to lock the frequencies of the dual-frequency oscillator to two external references independently. A prototype of a dual-frequency voltage-controlled oscillator (VCO) along with the dual-loop PLL is implemented in a BiCMOS SiGe technology. The dual-frequency VCO oscillates simultaneously at 2.33 and 4.98 GHz with 12.5% and 10.3% tuning ranges, respectively. The PLL has locking ranges of 4.2% and 3.6% for 2.33 and 4.98 GHz, respectively. Potential applications of concurrent multifrequency oscillators in multifunctional communication systems and multiband beam forming are discussed.      

锁相环中克服非理想因素的鉴相器和电荷泵设计

讨论了锁相环中鉴相器和电荷泵中非理想因素及其克服方法.电路设计采用SMIC 0.18 μm CMOS工艺和Cadence Spectre仿真器.通过在重置反馈路径上加入延迟单元的方法来消除鉴相器的死区.比较了两种传统电荷泵电路的设计方法,通过加入Replica Bias电路和单位增益运放,实现了上下电流的高匹配性.     

Current-Mode High-Accuracy High-Precision CMOS Amplifiers

In low-voltage, deep sub- mum analog CMOS circuits, the accuracy and precision can be limited by the finite gain as well as by the input offset and 1/f noise voltages of opamps. Here, we show how to design high-accuracy high-precision CMOS amplifiers by properly applying dynamic element matching to a second-generation current conveyor (CCII); if all of the critical, nominally identical transistor pairs are dynamically matched, the resulting amplifier has low residual input offset and noise voltages. When compared with chopper or traditional dynamic element-matching amplifiers, the proposed approach alleviates the tradeoff between output swing and output resistance and is more robust against the finite opamp gain. Transistor-level simulations confirm theoretical results.     

A Novel Calibration Method for Phase-Locked Loops

A novel method to calibrate the frequency response of a Phase-Locked Loop is presented. The method requires just an additional digital counter to measure the natural frequency of the PLL; moreover it is capable of estimating the static phase offset. The measured value can be used to tune the PLL response to the desired value. The method is demonstrated mathematically on a typical PLL topology and it is extended to fractional-N PLLs. A set of simulations performed with two different simulators is used to verify the applicability of the method.This work was carried out as a part of an internship at the QCT department of Qualcomm CDMA Technologies.Marco Cassia was born in Bergamo, Italy, 1974. He received the M.Sc. degree in engineering from the Technical University of Denmark, Lyngby, Denmark, in May 2000 and the M.Sc. degree in electrical engineering from Politecnico di Milano, Italy, in July 2000.From July 2001 to July 2002 he was with the QCT department of Qualcomm CDMA Technologies, San Diego, working in the field of direct modulation synthesizers. He is currently working toward the Ph.D.degree at the Technical University of Denmark.His main research interests are in the areas of low-power low-voltage RF systems.Peter Shah was born in Copenhagen Denmark in 1966. He completed his MScEE and Ph.D at The Technical University of Denmark in 1990 and 1993 respectively. From 1993 to 1995 he was a post doctoral research assistant at Imperial College in London, England, working on switched-current circuits. In 1996 he joined PCSI in San Diego (subsequently acquired by Conexant) as an RFIC design engineer, working on transceiver chips for the PHS cellular phone system. In 1998 he joined Qualcomm, also in San Diego, where he worked on RFICs for CDMA mobile phones and for GPS. In December 2002 he joined RFMagic where he is currently working on RFICs for consumer electronics. His research interests lie mainly in RFIC architecture and design, including sigma-delta PLLs and A/D and D/A converters, LNAs, mixers, and continuous-time filters.Erik Bruun received the M.Sc. and Ph.D. degrees in electrical engineering in 1974 and 1980, respectively, from the Technical University of Denmark. In 1980 he received the B.Com. degree from Copenhagen Business School. In 2000 he also received the dr. techn. degree from the Technical University of Denmark.From January 1974 to September 1974 he was with Christian Rovsing A/S, working on the development of space electronics and test equipment for space electronics. From 1974 to 1980 he was with the Laboratory for Semiconductor Technology at the Technical University of Denmark, working in the fields of MNOS memory devices, I²L devices, bipolar analog circuits, and custom integrated circuits. From 1980 to 1984 he was with Christian Rovsing A/S. From 1984 to 1989 he was the managing director of Danmos Microsystems ApS. Since 1989 he has been a Professor of analog electronics at the Technical University of Denmark where he has served as head of the Sector of Information Technology, Electronics, and Mathematics from 1995 to 2001. Since 2001 he has been head of ØrstedDTU.His current research interests are in the areas of RF integrated circuit design and integrated circuits for mobile phones.     

Phase-Controlled Apertures Using Heterodyne Optical Phase-Locked Loops

In this letter, we demonstrate the use of an electronic feedback scheme using a voltage controlled oscillator (VCO) to control the optical phase of individual semiconductor lasers (SCLs) phase locked to a common reference laser using heterodyne optical phase-locked loops (OPLLs). The outputs of two external cavity SCLs phase-locked to a common reference laser are coherently combined, and the variation in the relative optical path lengths of the combining beams is corrected by dynamically changing the phase of the offset radio-frequency signal fed into one of the OPLLs by means of a VCO. A stable power combination efficiency of 94% is achieved. This inherently different method of phase control, i.e., electronic rather than the use of electrooptic crystals, is deemed essential for new applications involving coherent optoelectronics.     

一种基于ADS和Matlab的锁相环电路设计方法

研究了基于ADS的锁相环电路的设计,针对该软件对仿真输出数据处理能力不足的问题,提出了一种利用Matlab对ADS仿真输出数据进行进一步处理的方法,通过对基于锁相环的线性调频信号产生电路的设计和仿真,证明了该方法的可行性和实用性。     

On the Pull-In Range of Phase-Locked Loops

The problem of determining the pull-in range of phaselocked loops is solved indirectly by evaluating the limit cycles of the loop in which the frequency error has a constant average. The analytical results derived here are in complete agreement with simulation results.     

CMOS Current-Mode Implementation of Fractional-Power Functions

A CMOS current-mode circuit, with only eight transistors and two current sources, is proposed to implement a fractional power function. The compact circuit comprises of an approximating logarithm circuit and an approximating exponential circuit. By sizing one transistor and tuning one current source, we improve the truncation errors in the Taylor series approximation, and reduce the MOS square-law errors that are caused by second-order effects. As example, a circuit, designed for gamma correction, with different gamma values controlled by three switches, is fabricated using 0.35 μm CMOS technology. The demonstration circuit can achieve a bandwidth of 155 MHz for an input range from 40 μA to 130 μA with 3% error, and maximum power dissipation of approximately 970 μW.     

A CMOS Low Noise, Chopper Stabilized Low-Dropout Regulator With Current-Mode Feedback Error Amplifier

Low $1/f$ noise, low-dropout (LDO) regulators are becoming critical for the supply regulation of deep-submicron analog baseband and RF system-on-chip designs. A low-noise, high accuracy LDO regulator (LN-LDO) utilizing a chopper stabilized error amplifier is presented. In order to achieve fast response during load transients, a current-mode feedback amplifier (CFA) is designed as a second stage driving the regulation FET. In order to reduce clock feed-through and $1/f$ noise accumulation at the chopping frequency, a first-order digital ${Sigma}{Delta}$ noise-shaper is used for chopping clock spectral spreading. With up to 1 MHz noise-shaped modulation clock, the LN-LDO achieves a noise spectral density of 32 ${hbox{nV}}/{surd}{hbox{Hz}}$ and a PSR of 38 dB at 100 kHz. The proposed LDO is shown to reduce the phase noise of an integrated 32 MHz temperature compensated crystal oscillator (TCXO) at 10 kHz offset by 15 dB. Due to reduced $1/f$ noise requirements, the error amplifier silicon area is reduced by 75%, and the overall regulator area is reduced by 50% with respect to an equivalent noise static regulator. The current-mode feedback second stage buffer reduces regulator settling time by 60% in comparison to an equivalent power consumption voltage mode buffer, achieving 0.6 $mu{hbox{s}}$ settling time for a 25-mA load step. The LN-LDO is designed and fabricated on a 0.25 $mu{hbox{m}}$ CMOS process with five layers of metal, occupying 0.88 ${hbox{mm}}^{2}$.      

New Four-Quadrant CMOS Current-Mode and Voltage-Mode Multipliers

In this paper, a four-quadrant current-mode multiplier based on a new squarer cell is proposed. The multiplier has a simple core, wide input current range with low power consumption, and it can easily be converted to a voltage-mode by using a balanced output transconductor (BOTA) [1]. The proposed four-quadrant current-mode and voltage-mode multipliers were confirmed by using PSPICE simulation and found to have good linearity with wide input dynamic range. For the proposed current-mode multiplier, the static power consumption is 0.671 mW, the maximum power consumption is 0.72 mW, the input current range is ± 60 μ A, the bandwidth is 31 MHz, the input referred noise current is 46 pA/√Hz, and the maximum linearity error is 3.9%. For the proposed voltage-mode multiplier, the static power consumption is 1.6 mW, the maximum power consumption is 1.85 mW, the input voltage range is ± 1V from ± 1.5V supply, the bandwidth is 25.34 MHz, the input referred noise voltage is 0.85 μV/√Hz, and the maximum linearity error is 4.1%. Mohammed A. Hashiesh was born in Elkharga, New Valley, Egypt, in 1979. He received the B.Sc. degree with honors from the Electrical Engineering Department, Cairo University, Fayoum-Campus, Egypt in 2001, and he received the M.Sc. degree in 2004 from the Electronics and Communication Engineering Department, Cairo University, Egypt. He is currently a Teacher Assistant at the Electrical Engineering Department, Cairo University, Fayoum-Campus. His research interests include analog CMOS integrated circuit design and signal processing, and digitally programmable CMOS analog building blocks. Soliman A. Mahmoud was born in Cairo, Egypt, in 1971. He received the B.Sc. degree with honors, the M.Sc. degree and the Ph.D. degree from the Electronics and Communications Department, Cairo University—Egypt in 1994, 1996 and 1999 respectively. He is currently an Assistant Professor at the Electrical Engineering Department, Cairo University, Fayoum-Campus. He has published more than 50 papers. His research and teaching interests are in circuit theory, fully integrated analog filters, high frequency transconductance amplifiers, low voltage analog CMOS circuit design, current-mode analog signal processing and mixed analog/digital programmable analog blocks. Ahmed M. Soliman was born in Cairo Egypt, on November 22, 1943. He received the B.Sc. degree with honors from Cairo University, Cairo, Egypt, in 1964, the M.S. and Ph.D. degrees from the University of Pittsburgh, Pittsburgh, PA., U.S.A., in 1967 and 1970, respectively, all in Electrical Engineering. He is currently Professor Electronics and Communications Engineering Department, Cairo University, Egypt. From September 1997–September 2003, Dr Soliman served as Professor and Chairman Electronics and Communications Engineering Department, Cairo University, Egypt. From 1985–1987, Dr. Soliman served as Professor and Chairman of the Electrical Engineering Department, United Arab Emirates University, and from 1987–1991 he was the Associate Dean of Engineering at the same University. He has held visiting academic appointments at San Francisco State University, Florida Atlantic University and the American University in Cairo. He was a visiting scholar at Bochum University, Germany (Summer 1985) and with the Technical University of Wien, Austria (Summer 1987). In 1977, Dr. Soliman was decorated with the First Class Science Medal, from the President of Egypt, for his services to the field of Engineering and Engineering Education. Dr Soliman is a member of the Editorial Board of Analog Integrated Circuits and Signal Processing. Presently Dr. Soliman is Associate Editor of the IEEE Transactions on Circuits and Systems I (Analog Circuits and Filters).