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1.
We present a runtime verification framework that allows on-line monitoring of past-time Metric Temporal Logic (ptMTL) specifications in a discrete time setting. We design observer algorithms for the time-bounded modalities of ptMTL, which take advantage of the highly parallel nature of hardware designs. The algorithms can be translated into efficient hardware blocks, which are designed for reconfigurability, thus, facilitate applications of the framework in both a prototyping and a post-deployment phase of embedded real-time systems. We provide formal correctness proofs for all presented observer algorithms and analyze their time and space complexity. For example, for the most general operator considered, the time-bounded Since operator, we obtain a time complexity that is doubly logarithmic both in the point in time the operator is executed and the operator’s time bounds. This result is promising with respect to a self-contained, non-interfering monitoring approach that evaluates real-time specifications in parallel to the system-under-test. We implement our framework on a Field Programmable Gate Array platform and use extensive simulation and logic synthesis runs to assess the benefits of the approach in terms of resource usage and operating frequency.  相似文献   

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Runtime monitoring of timing constraints in distributed real-time systems   总被引:1,自引:0,他引:1  
Embedded real-time systems often operate under strict timing and dependability constraints. To ensure responsiveness, these systems must be able to provide the expected services in a timely manner even in the presence of faults. In this paper, we describe a run-time environment for monitoring of timing constraints in distributed real-time systems. In particular, we focus on the problem of detecting violations of timing assertions in an environment in which the real-time tasks run on multiple processors, and timing constraints can be either inter-processor or intra-processor constraints. Constraint violations are detected at the earliest possible time by deriving and checking intermediate constraints from the user-specified constraints. If the violations must be detected as early as possible, then the problem of minimizing the number of messages to be exchanged between the processors becomes intractable. We characterize a sub-class of timing constraints that occur commonly in distributed real-time systems and whose message requirements can be minimized. We also take into account the drift among the various processor clocks when detecting a violation of a timing assertion. Finally, we describe a prototype implementation of a distributed run-time monitor.This work was done while the first two authors were at the IBM T.J. Watson Research Center.Supported in part by the Office of Naval Research under grant number N00014-89-J-1040 and by National Science Foundation under grant number CCR-9200858.  相似文献   

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We give an overview of correctness criteria specific to concurrent shared-memory programs and runtime verification techniques for verifying these criteria. We cover a spectrum of criteria, from ones focusing on low-level thread interference such as races to higher-level ones such as linearizability. We contrast these criteria in the context of runtime verification. We present the key ideas underlying the runtime verification techniques for these criteria and summarize the state of the art. Finally, we discuss the issue of coverage for runtime verification for concurrency and present techniques that improve the set of covered thread interleavings.  相似文献   

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International Journal on Software Tools for Technology Transfer - Current real-time embedded systems development frameworks lack support for the verification of properties using explicit time where...  相似文献   

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缓存区溢出能引起非常严重的安全问题,对网络和分布式系统(如机群,网格,P2P系统等)构成严重威胁。数组越界在缓存区溢出中占据重要位置,如何检测数组越界错误是一个重要且极具意义的课题。针对该课题,给出一种对C语言数组越界进行运行时验证的方法。分析了数组越界的错误类型,根据这些类型分别研究了数组越界的运行时验证的思想;设计了基于程序插桩进行数组越界动态检测的算法,给出了该方法基于开源编译器Clang的具体实现;用实验证明了该方法是切实可行并且有效的。  相似文献   

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Software Quality Journal - We study the problem of online runtime verification of real-time event streams. Our monitors can observe concurrent systems with a shared clock, but where each component...  相似文献   

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多agent自适应系统在运行过程中需要根据环境进行自适应调整。异构agent能够提高agent的使用效率和降低系统的构建成本,但存在复杂的协作问题,因此提出一种基于概率时间自动机的异构多agent自适应系统运行时验证方法。该方法通过形式化描述异构agent的功能特征并融合环境中的随机因素构建概率时间自动机模型模拟自适应系统的运行过程;针对异构agent之间的协作逻辑制定安全约束条件以确保系统运行中状态迁移流程的安全性。通过模型检查结合运行时定量验证方法进行实验验证,在智能泊车系统案例中应用该方法。实验结果表明,agent之间协作逻辑的正确性可以有效保证系统运行时的稳定性,且相较于不使用运行时定量验证的初始系统在相同时间内正常运行的时间提升了21%左右。  相似文献   

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为了应对日益复杂的电网设备监控信息,通过建立统一的大数据管理平台,实现多元数据共享、信息规范化,从而提高调控人员的决策能力和工作效率。本文针对设备监控管理实际提出设备监控信息校验及实用化事件分析管理方法。首先,通过自然语言解析和设备拓扑关系,实现一、二次设备监控信息的关联融合。其次,通过设备监控信息与EMS模型中监控信息智能比对和检验,实现监控信息表完整性核查。采用变压器负载率智能校验新算法,排查全电网遥测存在的隐患缺陷,为消缺处理提供了重要依据。最终,通过监控数据事件化打包分组和自动识别方法,结合电力设备状态大数据共享平台,有效判断故障、异常“事件”,辅助快速完成对各类电网事件的全过程分析,从而提高事故处理效率, 科学评价监测报警质量。  相似文献   

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The Journal of Supercomputing - Heterogeneous hardware systems consisting of CPUs and different types of accelerators are wide-spread nowadays for large supercomputers as well as smaller cluster...  相似文献   

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This paper considers the adaptive control of discrete-time hybrid stochastic systems with unknown randomly jumping parameters described by a finite-state hidden Markov chain. An intuitive yet longstanding conjecture in this area is that such hybrid systems can be adaptively stabilized whenever the rate of transition of the hidden Markov chain is small enough. This paper provides a rigorous positive answer to this conjecture by establishing the global stability of a gradient-algorithm-based adaptive linear-quadratic control.  相似文献   

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《Parallel Computing》2007,33(10-11):700-719
We explore runtime mechanisms and policies for scheduling dynamic multi-grain parallelism on heterogeneous multi-core processors. Heterogeneous multi-core processors integrate conventional cores that run legacy codes with specialized cores that serve as computational accelerators. The term multi-grain parallelism refers to the exposure of multiple dimensions of parallelism from within the runtime system, so as to best exploit a parallel architecture with heterogeneous computational capabilities between its cores and execution units. We investigate user-level schedulers that dynamically “rightsize” the dimensions and degrees of parallelism on the cell broadband engine. The schedulers address the problem of mapping application-specific concurrency to an architecture with multiple hardware layers of parallelism, without requiring programmer intervention or sophisticated compiler support. We evaluate recently introduced schedulers for event-driven execution and utilization-driven dynamic multi-grain parallelization on Cell. We also present a new scheduling scheme for dynamic multi-grain parallelism, S-MGPS, which uses sampling of dominant execution phases to converge to the optimal scheduling algorithm. We evaluate S-MGPS on an IBM Cell BladeCenter with two realistic bioinformatics applications that infer large phylogenies. S-MGPS performs within 2–10% of the optimal scheduling algorithm in these applications, while exhibiting low overhead and little sensitivity to application-dependent parameters.  相似文献   

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Summary By means of an example, we present a formal method based on CSP to design fault tolerant systems. This method combines algebraic and assertional techniques to achieve complete formal verification of the fault tolerant system's correctness properties. Verification steps are executed in parallel with top-down design, so that correctness proofs can be clearly structured and their completeness easily checked. In this way formal verification is applicable not only to small examples but to reasonably large systems. Jan Peleska was born in 1958 in Hamburg, received his Diploma in Mathematics from the University of Hamburg in 1981 and a Ph.D. in Mathematics in 1982. From 1981 to 1984 he worked in research and software development projects in the field of accoustics. Since 1984 he has been working with Philips and DST in Kiel in the field of distributed information systems. Peleska's current research interests include fault tolerant systems, distributed database systems and formal design and verification methods.  相似文献   

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Real-time embedded systems are often designed with different types of urgencies such as delayable or eager, that are modeled by several urgency variants of the timed automata model. However, most model checkers do not support such urgency semantics, except for the IF toolset that model checks timed automata with urgency against observers. This work proposes an Urgent Timed Automata (UTA) model with zone-based urgency semantics that gives the same model checking results as absolute urgency semantics of other existing urgency variants of the timed automata model, including timed automata with deadlines and timed automata with urgent transitions. A necessary and sufficient condition, called complete urgency, is formulated and proved for avoiding zone partitioning so that the system state graphs are simpler and model checking is faster. A novel zone capping method is proposed that is time-reactive, preserves complete urgency, satisfies all deadlines, and does not need zone partitioning. The proposed verification methods were implemented in the SGM CTL model checker and applied to real-time and embedded systems. Several experiments, comparing the state space sizes produced by SGM with that by the IF toolset, show that SGM produces much smaller state-spaces.  相似文献   

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Applied Intelligence - We provide a survey of the state of the art of rational verification: the problem of checking whether a given temporal logic formula ? is satisfied in some or all...  相似文献   

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Amongst the users of the AIDA applications there is a rapidly growing interest in the use of expert systems, not as independent systems, but as logical extensions of their already existing information systems. In this paper a prototype system (IDEA) will be described that consists of a set of utilities for the construction of an expert system within the context of an AIDA application. Although IDEA does not excel in sophisticated knowledge representations nor in search strategies (the development of which was not our primary concern) it is able to demonstrate that the facilities provided by AIDA together with the IDEA facilities result in an expert system which is characterized by a high degree of integration with the already operational information system.  相似文献   

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In the traditional video and image processing technology field, researchers often focus on the processing of the image content, especially the accuracy and the speed. However, the geographic information data carried by UAV video and image is often ignored, resulting in the image only containing the scene information and losing the geographic data information after the image processing iscomplet- ed, so that the user cannot quickly obtain the geographic information of the target of interest from image processing results. In order to process the geographic information efficiently, an image mosaicking and verification algorithm for UAV image with geographic information regards geographic information data as multi-channel double floating-point matrix data, which can be calculated synchronously using matrix processing algorithms. Meanwhile, the accuracy and speed of a large number of image mosaicking tasks can be improved by using image-splicing algorithm based on grouping control with geographic information. The experimental results show that the proposed algorithm can effectively process the UAV image with geographic information, especially in image mosaicking.  相似文献   

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