An efficient parallelization technique for x264 encoder on heterogeneous platforms consisting of CPUs and GPUs

H.264/AVC video encoders have been widely used for its high coding efficiency. Since the computational demand proportional to the frame resolution is constantly increasing, it has been of great interest to accelerate H.264/AVC by parallel processing. Recently, graphics processing units (GPUs) have emerged as a viable target for accelerating general purpose applications by exploiting fine-grain data parallelisms. Despite extensive research efforts to use GPUs to accelerate the H.264/AVC algorithm, it has not been successful to achieve any speed-up over the x264 algorithm that is known as the fastest CPU implementation, mainly due to significant communication overhead between the host CPU and the GPU and intra-frame dependency in the algorithm. In this paper, we propose a novel motion-estimation (ME) algorithm tailored for NVIDIA GPU implementation. It is accompanied by a novel pipelining technique, called sub-frame ME processing, to effectively hide the communication overhead between the host CPU and the GPU. Further, we incorporate frame-level parallelization technique to improve the overall throughput. Experimental results show that our proposed H.264 encoder has higher performance than x264 encoder.     

Simplified algorithms for rate-distortion optimization in high efficiency video coding

HEVC is the latest coding standard to improve the coding efficiency by a factor of two over the previous H.264/AVC standard at the cost of the increased complexity of computation rate-distortion optimization (RDO) is one of the computationally demanding operations in HEVC and makes it difficult to process the HEVC compression in real time with a reasonable computing power. This paper aims to present various simplified RDO algorithms with the evaluation of their RD performance and computational complexity. The algorithms for the simplified estimation of the sum of squared error (SSE) and context-adaptive binary arithmetic coding (CABAC) proposed for H.264/AVC are reviewed and then they are applied to the simplification of HEVC RDO. By modifying the previous algorithm for H.264/AVC, a new simplified RDO algorithm is proposed for modifying the previous algorithm for H.264/AVC to be optimized for the hierarchical coding structure of HEVC. Further simplification is attempted to avoid the transforms operations in RDO. The effectiveness of the existing H.264/AVC algorithms as well as the proposed algorithms targeted for HEVC is evaluated and the trade-off relationship between the RD performance and computational complexity is presented for various simplification algorithms. Experimental results show that reasonable combinations of RDO algorithms reduce the computation by 80–85% at the sacrifice of the BD-BR by 3.46–5.93% for low-delay configuration.     

Fast Motion Estimation on Graphics Hardware for H.264 Video Encoding

The video coding standard H.264 supports video compression with a higher coding efficiency than previous standards. However, this comes at the expense of an increased encoding complexity, in particular for motion estimation which becomes a very time consuming task even for today's central processing units (CPU). On the other hand, modern graphics hardware includes a powerful graphics processing unit (GPU) whose computing power remains idle most of the time. In this paper, we present a GPU based approach to motion estimation for the purpose of H.264 video encoding. A small diamond search is adapted to the programming model of modern GPUs to exploit their available parallel computing power and memory bandwidth. Experimental results demonstrate a significant reduction of computation time and a competitive encoding quality compared to a CPU UMHexagonS implementation while enabling the CPU to process other encoding tasks in parallel.     

Fast coding unit (CU) determination algorithm for high-efficiency video coding (HEVC) in smart surveillance application

High-efficiency video coding (HEVC) is a successor to the H.264/AVC standard as the newest video-coding standard using a quad-tree structure with the three block types of a coding unit (CU), a prediction unit (PU), and a transform unit (TU). This has become popular to apply to smart surveillance systems, because very high-quality image is needed to analyze and extract more precise features. On standard, the HEVC encoder uses all possible depth levels for determination of the lowest rate-distortion (RD) cost block. The HEVC encoder is more complex than the H.264/AVC standard. An efficient CU determination algorithm is proposed using spatial and temporal information in which 13 neighboring coding tree units (CTUs) are defined. Four CTUs are temporally located in the current CTU and the other nine neighboring CTUs are spatially situated in the current CTU. Based on the analysis of conditional probability values for SKIP and Merge modes, an optimal threshold value was determined for judging SKIP or Merge mode according to the CTU condition and an adaptive weighting factor. When SKIP or Merge modes were detected early, other mode searches were omitted. The proposed algorithm achieved approximately 35 % time saving with random-access configuration and 29 % time reduction with low-delay configuration while maintaining comparable rate-distortion performance, compared with HM 12.0 reference software.     

HEVC optimization based on human perception for real-time environments

High-Efficiency Video Coding (HEVC) is the new emerging video coding standard of the ITU-T Video Coding Experts Group (VCEG) and the ISO/IEC Moving Picture Experts Group (MPEG). The HEVC standard provides a significant improvement in compression efficiency in comparison with existing standards such as H264/AVC by means of greater complexity. In this paper we will examine several HEVC optimizations based on image analysis to reduce its huge CPU, resource and memory expensive encoding process. The proposed algorithms optimize the HEVC quad-tree partitioning procedure, intra/inter prediction and mode decision by means of H264-based methods and spatial and temporal homogeneity analysis which is directly applied to the original video. The validation process of these approaches was conducted by taking into account the human visual system (HVS). The adopted solution makes it possible to perform HEVC real time encoding for HD sequences on a low cost processor with negligible quality loss. Moreover, the frames pre-processing leverages the logic units and embedded hardware available on an Intel GPU, so the execution time of these stages are negligible for the encoding processor.

     

CUDA架构下H.264快速去块滤波算法

针对H.264/AVC视频编码标准中去块滤波器运算复杂度高、耗时巨大这一难题,提出了一种基于NVIDIA计算统一设备架构（CUDA）平台的H.264并行快速去块滤波算法,介绍了CUDA平台硬件结构特点与软件开发流程,根据图形处理器（GPU）的并发结构特点,对BS判定与滤波计算进行了并行优化,降低了算法复杂度,利用共享内存提高了数据访问速率,实现了去块滤波器的并行处理。实验结果表明,在图像质量基本不变的情况下,GPU算法能够明显提高运算速度,平均加速比在20倍左右,取得了良好的效果。     

Dyadic spatial resolution reduction transcoding for H.264/AVC

In this paper, we examine spatial resolution downscaling transcoding for H.264/AVC video coding. A number of advanced coding tools limit the applicability of techniques, which were developed for previous video coding standards. We present a spatial resolution reduction transcoding architecture for H.264/AVC, which extends open-loop transcoding with a low-complexity compensation technique in the reduced-resolution domain. The proposed architecture tackles the problems in H.264/AVC and avoids visual artifacts in the transcoded sequence, while keeping complexity significantly lower than more traditional cascaded decoder–encoder architectures. The refinement step of the proposed architecture can be used to further improve rate-distortion performance, at the cost of additional complexity. In this way, a dynamic-complexity transcoder is rendered possible. We present a thorough investigation of the problems related to motion and residual data mapping, leading to a transcoding solution resulting in fully compliant reduced-size H.264/AVC bitstreams.     

Fast transcoding from H.264 to HEVC based on region feature analysis

The new video coding standard, High Efficiency Video Coding (HEVC), achieves much higher coding efficiency than the state-of-the-art H.264. Transcoding H.264 video to HEVC video is important to enable gradual migration to HEVC. Therefore, a fast H.264 to HEVC transcoding algorithm based on region feature analysis is proposed. First, each frame is segmented into three regions in units of coding tree unit (CTU) based on the correlation between image coding complexities and coding bits of the H.264 source stream. Then the searching depth range of each CTU is adaptively decided according to the region type. After that, motion vectors are de-noise filtered and clustered in order to analyze the region features of coding unit (CU). Based on the analysis results, the minimum searching depth of CU and partitions of prediction unit (PU) are optimally selected, and the motion vector predictor and search window size of motion estimation are also optimally decided for further reduction of the computational complexity. Experimental results show that the proposed algorithm achieves a significant improvement on transcoding speed, while maintaining high Rate-Distortion performance.     

HEVC 熵编码算法优化

新一代视频编码标准HEVC提供了更加灵活的编码工具选择,在提高压缩率的同时也提高了编码的计算复杂度。由于可选择更大的变换单元以及编码中更强的系数间依赖关系,在率失真优化（RDO）模式选择过程中,HEVC熵编码的计算复杂度显著高于H．264/AVC。为了解决这一问题,本文对HEVC熵编码算法进行优化,通过优化熵编码的上下文空间选择过程、非零系数的编码结构,以及对不同大小的变换矩阵进行整体优化。实验结果表明,本文提出的优化算法能够在保证视频编码质量基本不变的同时,平均降低约43％的熵编码时间。     

Fast motion estimation using priority-based inter-prediction mode decision method in high efficiency video coding

The latest video coding standard, high efficiency video coding (HEVC), is developed to acquire a more efficient coding performance than the previous standard, H.264/AVC. To achieve this coding performance, elaborate coding tools were implemented in HEVC. Although those tools show a higher coding performance than H.264/AVC, the encoding complexity is heavily increased. Especially, motion estimation (ME) requires the most computational complexity because that is always performed on three inter-prediction modes: uni-directional prediction in List 0 (Uni-L0), uni-directional prediction in List 1 (Uni-L1), and bi-prediction (Bi). In this paper, we propose a priority-based inter-prediction mode decision method to reduce the complexity of ME caused by inter-prediction. The proposed method computes the priorities of all inter-prediction modes and decides whether ME is performed or not. Experimental results show that the proposed method reduces the computational complexity of ME up to 55.51% while maintaining similar coding performance compared to HEVC test model (HM) version 10.1.     

Parallel strategies analysis over the HEVC encoder

Recently, a new video coding standard called HEVC has been developed to deal with the nowadays media market challenges, being able to reduce to the half, on average, the bit stream size produced by the former video coding standard H.264/AVC at the same video quality. However, the computing requirements to encode video improving compression efficiency have significantly been increased. In this paper, we focus on applying parallel processing techniques to HEVC encoder to significantly reduce the computational power requirements without disturbing the coding efficiency. So, we propose several parallelization approaches to the HEVC encoder which are well suited to multicore architectures. Our proposals use OpenMP programming paradigm working at a coarse grain level parallelization which we call GOP-based level. GOP-based approaches encode simultaneously several groups of consecutive frames. Depending on how these GOPs are conformed and distributed, it is critical to obtain good parallel performance, taking also into account the level of coding efficiency degradation. The results show that near ideal efficiencies are obtained using up to 12 cores.     

A fast inter-frame encoding scheme using the edge information and the spatiotemporal encoding parameters for HEVC

Multimedia Tools and Applications - High Efficiency Video Coding (HEVC), as a novel video coding standard, has shown a better coding efficiency than all existing standards, such as H.264/AVC. It...     

Concealment of Whole-Picture Loss in Hierarchical B-Picture Scalable Video Coding

H.264/AVC scalable video coding (H.264/AVC SVC), as the scalable extension of H.264/AVC, offers the flexible adaptivity in terms of spatial, temporal and SNR scalabilities for the generated bitstream. However, such compressed video still suffers from the bad playback quality when packet loss occurs over unreliable networks. In this paper, we present an error concealment algorithm to tackle the whole-picture loss problem in H.264/AVC SVC when hierarchical B-picture coding is used to support temporal scalability. In the proposed algorithm, by taking advantage of the temporal relationship among the adjacent video pictures, the motion information of the lost picture is derived simply and efficiently based on the principle of temporal direct mode. Utilizing the derived motion information, the lost picture is concealed by performing motion compensation on the correctly received temporally previous and future video pictures. The experimental results demonstrate that as a post-processing tool, the proposed error concealment algorithm is able to significantly improve both the objective and subjective qualities of the decoded video pictures in the presence of packet losses when compared to the error concealment algorithm used in H.264/AVC SVC reference software. The proposed method can also be applied to H.264/AVC with hierarchical B-picture coding for error concealment.     

Power and performance analysis of multimedia applications running on low-power devices by cache modeling

High processing speed is required to support computation intensive applications. Cache memory is used to improve processing speed by reducing the speed gap between the fast processing core and slow main memory. However, the problem of adopting cache into computing systems is twofold: cache is power hungry (that challenges energy constraints) and cache introduces execution time unpredictability (that challenges supporting real-time multimedia applications). Recently published articles suggest that using cache locking improves predictability. However, increased cache activities due to aggressive cache locking make the system consume more energy and become less efficient. In this paper, we investigate the impact of cache parameters and cache locking on power consumption and performance for real-time multimedia applications running on low-power devices. In this work, we consider Intel Pentium-like single-processor and Xeon-like multicore architectures, both with two-level cache memory hierarchy, using three popular multimedia applications: MPEG-4 (the global video coding standard), H.264/AVC (the network friendly video coding standard), and recently introduced H.265/HEVC (for improved video quality and data compression ratio). Experimental results show that cache locking mechanism added to an optimized cache memory structure is very promising to increase the performance/power ratio of low-power systems running multimedia applications. According to the simulation results, performance can be improved by decreasing cache miss rate down to 36 % and the total power consumption can be saved up to 33 %. It is also observed that H.265/HEVC has significant performance advantage over H.264/AVC (and MPEG-4) for smaller caches.     

H.264/AVC解码芯片验证系统及验证策略

H.264/AVC视频编码标准是目前应用广泛的视频压缩标准,具有压缩比高、算法复杂等特点,给视频解码系统的设计和验证带来了挑战。文中基于一款H.264/AVC解码芯片架构,针对H.264/AVC视频解码系统的复杂性,构建了验证系统,提出多形式、分层次的验证策略,在解码芯片设计实现的各个阶段实施验证。根据RTL虚拟仿真、FPGA原型和后仿真等验证手段的特点,分别规划不同阶段的测试激励,形成基于H.264/AVC解码芯片的验证项策划,对类似H.264/AVC解码器的验证工作具有一定的帮助。     

基于H.264 的混沌视频加密系统

为了解决视频信息的安全问题,提出了一种基于视频编码标准H．264／AVC的混沌视频加密算法。利用流密码加密简单、运算速度快等优点,采用Logistic离散混沌序列对H．264／AVC标准的CAVLC（基于上下文的自适应变长编码）熵编码阶段的码流进行加密,并从算法的安全性、加密效率等方面进行分析。试验结果表明：该加密算法在保证视频内容信息安全性的前提下,不改变码流的结构,具有良好的实时性和快速性。     

结合帧率变换与HEVC标准的新型视频压缩编码算法

相比于之前主流的H.264视频压缩编码标准,HEVC在保证重建视频质量相同的前提下,可以将码率降低近50%,节省了传输所需的带宽.即便如此,由于一些特定的网络带宽限制,为继续改善HEVC视频编码性能,进一步提升对视频的压缩效率仍然是当前研究的热点.本文提出一种HEVC标准编码与帧率变换方法相结合的新型的视频压缩编码算法,首先在编码端,提出一种自适应抽帧方法,降低原视频帧率,减少所需传输数据量,对低帧率视频进行编解码;在解码端,结合从HEVC传输码流中提取的运动信息以及针对HEVC编码特定的视频帧的分块模式信息等,对丢失帧运动信息进行估计;最后,通过本文提出的改进基于块覆盖双向运动补偿插帧方法对视频进行恢复重建.实验结果证实了本文所提算法的有效性.     

实时高清H.264编码中CAVLC的流式实现

CAVLC是H.264中熵编码的一种重要实现方式,具有可挖掘的数据级并行特征,但同时具有较强的串行特点。本文分析了CAVLC的程序特征,提出了CAVLC的流式实现方法,并在流处理器STORM-1上进行了实现。实验结果表明本方法能够满足实时高清H.264编码的性能需求。     

Fast HEVC I-frame coding based on strength of dominant direction of CUs

High efficiency video coding (HEVC), the latest international video coding standard, greatly outperforms previous standards such as H.264/AVC in terms of coding bitrate and video quality. The coding efficiency improvement in HEVC is achieved by introducing several new techniques such as recursive quad-tree structure and increased number of intra prediction modes. However, computational load is also increased due to employing the new techniques. In this paper, we propose a solution for fast I-frame coding in HEVC standard using homogeneity of Coding Units (CUs). The proposed solution consists of two stages. In the first stage, we evaluate CU homogeneity by computing a parameter named dominant direction strength and predict CU size by this means. In the second stage, we select 11 modes out of 35 for the specified CU size based on dominant direction of the CU. Experimental results indicate that the proposed method achieves on average 45.8 % reduction on coding time, with very similar coding efficiency as the HEVC reference software. Moreover, we designed tree-stage pipelined architecture for our method which can operate at 235 MHz maximum clock rate which means it can be used for real-time coding of all intra configuration of HEVC videos up to level 6.2.