High throughput entropy decoder design for H.265/HEVC

Multimedia Tools and Applications - The H.265/high efficiency video coding (HEVC) standard employs context-based adaptive binary arithmetic coding (CABAC) as a single entropy coding method. Despite...     

Scene-level two-pass video rate controller for H.265/HEVC standard

Multimedia Tools and Applications - A scene-level two-pass video rate controller for high efficiency video coding (HEVC) standard is proposed in this paper. The proposed rate controller is suitable...     

基于梯度的H.265/HEVC帧内预测硬件加速算法研究

HEVC即H.265,是目前最新的视频编码标准。相比于前一代视频编码标准,H.265/HEVC虽然能够明显改善视频压缩效率,但是却带来了更高的计算复杂度,尤其是在帧内预测过程中。为了解决这个问题,提出一种基于梯度的帧内预测硬件加速算法来跳过一些帧内预测模式和划分深度的预测过程,从而达到减少计算的目的。利用图像梯度信息来粗略估计编码单元的纹理方向和纹理复杂度,其中纹理方向用来估计编码单元的最优帧内预测方向,纹理复杂度用来判断是否跳过当前划分深度的预测编码过程。实验表明,相比于H.265/HEVC测试模型HM16.18,本文提出的算法能够减少6059%的编码时间,仅造成0.38 dB的BD PSNR减少和8.52%的BD-Rate增加。     

An AR based fast mode decision for H.265/HEVC intra coding

As a critical technique to raise coding efficiency in H.265/HEVC (H.265/High Efficiency Video Coding), the number of prediction modes for intra coding is much larger than that in H.264/AVC. However, the large number of prediction modes also leads to high complexity. In this paper, an AR (Auto Regression) based fast mode decision method for H.265/HEVC intra coding is proposed, including an AR based fast mode selection and an MPM (Most Probable Mode) joint fast mode selection method. Considering the correlation between SATD (Sum of Absolute Transformed Differences) cost and RD (Rate-Distortion) cost, we establish a selective function controlled by an adaptive parameter which is acquired by an AR model. According to the distribution of the SATD cost, the selective function can decide which modes can be discarded and which modes can be used for the FMD (Fine Mode Decision). In addition, in order to further reduce the number of candidate modes for FMD, an MPM joint fast mode selection method is presented based on the relationship between MPMs and candidate modes. Experimental results show that just in PU layer, the proposed AR based fast intra mode decision method can save encoding time by 32 % with negligible coding loss in all-intra main configuration compared to the intra mode decision of HM13.0.     

Prediction mode based H.265/HEVC video watermarking resisting re-compression attack

Multimedia Tools and Applications - This paper proposes a novel compressed domain robust watermarking scheme which embeds watermark by altering the intra prediction modes of 4 × 4 intra...     

基于SSE2对H.265/HEVC中分像素插值的优化

分像素插值算法是视频编码算法中的一项关键技术,对视频编码性能有非常重要的影响。在最新的视频编码标准H.265/HEVC中,提出了使用DCT插值滤波器（DCTIF）分别进行半像素和1/4像素插值,但是计算复杂度较大,尤其对于高分辨率和超高分辨率的视频编码应用。对滤波器系数的理论推导过程进行了详细介绍,并利用SSE2指令集进行了优化设计和实现,实验结果表明该方法比参考代码中的方法提高了217%~259%的性能。     

A new data hiding method for H.265/HEVC video streams without intra-frame distortion drift

Multimedia Tools and Applications - This paper presents a readable H.265/HEVC data hiding method. First, three conditions of the directions of intra-frame prediction and the multi-coefficients are...     

An efficient mechanism of cryptographic synchronization within selectively encrypted H.265/HEVC video stream

The challenge to which the encryption of multimedia data needs to respond is ensuring the security of data intensive video stream in an efficient way. Unlike full data encryption, selective encryption manages to achieve this by encrypting only a part of the data stream, while providing a satisfactory level of video security. This optimizes the processing time and the size of encrypted data. Regardless of the encryption technique, there is a lack of cryptographic synchronization when providing random access to the selected part of the encrypted multimedia stream. In this paper we propose a novel and efficient method of cryptographic synchronization as an extension to the H.265/HEVC crypto encoder in order to support random access in selectively encrypted video stream.     

H.264编码器存储带宽分析及DRAM控制器设计

在分析H.264/AVC编码过程中存储器带宽需求的基础上,提出一种DRAM控制器结构,并实现了几种不同调度策略的DRAM控制器结构设计。实现了令牌环、固定优先级和抢占式等三种结构,结合已有的存储空间映射方法,通过减少换行及Bank切换过程中的冗余周期,进一步提高存储器的带宽利用率。实验结果表明,提出的三种存储器结构中抢占式调度具有最高的宽利用率,可满足150 MHz时钟频率条件下HDTV1080P实时编码的应用。     

Square-type-first inter-CU tree search algorithm for acceleration of HEVC encoder

In this paper, a fast inter-coding algorithm is proposed to reduce the computational load of HEVC encoders. The HEVC reference model (HM) employs the recursive depth-first-search (DFS) of the quad-tree search in terms of rate-distortion optimization in selecting the best coding modes for the best CU, PU, TU partitions, and many associated coding modes. The proposed algorithm evaluates the RD costs of the current CU only for its square-type PUs in the top-down search of the DFS. When the CU partition with the square-type PU is better than its sub-level CU partitions in terms of RD cost in bottom-up search of the DFS, the square type of current CU partition, along with its coding mode, is selected as the best partition. Otherwise, non-square-type PUs for the current CU level are evaluated. If the sub-partition is better than the CU with the non-square PUs, the sub-partition is finally selected as the optimum PU. Otherwise, the best non-square PU is selected as the best PU for the current level. Experimental results demonstrate that the proposed square-type-first inter-PU search can reduce the computational load in average encoding time by 66.7 % with 1–2 % BD loss over HM reference software. In addition, the proposed algorithm can yield an additional average time saving of 26.8–35.5 % against the three fast encoding algorithms adopted in HM.     

Low-complexity heterogeneous architecture for H.264/HEVC video transcoding

High efficiency video coding (HEVC) was developed by the Joint Collaborative Team on video coding to replace the current H.264/AVC standard, which has been widely adopted over the last few years. Therefore, there is a lot of legacy content encoded with H.264/AVC, and an efficient conversion to HEVC is needed. This paper presents a hybrid transcoding algorithm which makes use of soft computing techniques as well as parallel processing. On the one hand, a fast quadtree level decision algorithm tries to exploit the information gathered at the H.264/AVC decoder to make faster decisions on coding unit splitting in HEVC using a Naïve–Bayes probabilistic classifier that is determined by a supervised data mining process. On the other hand, a parallel HEVC-encoding algorithm makes use of a heterogeneous platform composed of a multi-core central processing unit plus a graphics processing unit (GPU). In this way, from a coarse point of view, groups of frames or rows of a frame (both options are possible) are divided into threads to be executed on each core (each of which executes one of the aforementioned classifiers) and, from a finer point of view, all these threads work in a collaborative way on a single GPU to perform the motion estimation process on the co-processor. Experimental results show that the proposed transcoder can achieve a good tradeoff between coding efficiency and complexity compared with the anchor transcoder.     

Effectiveness of crypto-transcoding for H.264/AVC and HEVC video bit-streams

Multimedia Tools and Applications - To avoid delays arising from a need to decrypt a video prior to transcoding and then re-encrypt it afterwards, this paper assesses a selective encryption (SE)...     

H.264/AVC的复杂度分析以及实时实现

新发展的H.264/AVC比原有的视频编码标准大幅度提高了编码效率,但其运算复杂度也大大增加,影响了其推广。本文简要分析了H.264/AVC的复杂度,并指出对其优化的途径,提出了对其中的帧内预测编码和多尺度块模式搜索运动估计等主要模块的优化算法。实验结果显示可以实现对CIF格式的图像进行实时编码。     

Architecture design of low-power motion estimation based on DHS-NPDS for H.264/AVC

A novel architecture of motion estimation(ME) based on improved normalized partial distortion search is proposed to meet three primary requirements for real-time video encoding,which are low-power,lowbandwidth and high area utilization efficiency.The ME engine supports both normalized partial distortion search and adaptive search window adjustment.The former can reduce the computational complexity of ME to save power and area;the latter can avoid unnecessary accessing the external memory to lower the data bandwidth.The proposed engine has been implemented with UMC 90nm CMOS technology.The implementation results show that,compared with traditional engines,the engine can achieve significant improvements of the hardware efficiency and the power efficiency respectively with a little throughput compromise.     

基于DHS-NPDS的低功耗运动估计硬件结构设计

为了达到实时视频编码的低功耗、低带宽、省资源3个要求,文中基于改进的归一化部分失真搜索算法,提出一种新颖的运动估计硬件结构.新结构同时支持归一化部分失真搜索和自适应搜索区域调整.前者可降低运动估计的计算复杂度,从而实现低功耗省资源两个要求,后者能避免不必要的外存访问,从而降低数据带宽.在UMC 90 nm CMOS工艺下实现结果表明,相比于传统结构的最好结果,文中结构以6.2%的吞吐率损失,换取面积效率和功耗效率分别提高425.5%和397.5%.     

一种改进的H.264码率控制算法

码率控制是H.264/AVC的一个重要组成部分,它通过调节编码比特流的的码率变化从而在给定的信道带宽下获得持续较好的图像质量。在Nejat Kamaci提出的码率控制算法上进行了改进,增加了宏块级码率控制,并针对传统的平均绝对误差（Mean Absolute difference,MAD）线性预测模型计算量大且存在一定误差的缺点,提出一种新的MAD加权预测模型,降低了算法复杂度和预测误差。实验结果表明,改进算法的码率控制更加准确,并且图像的PSNR值也有所提高。     

H.264/AVC High Profile视频编码中自适应变换模块的设计

提出了一种可配置的整数变换运算单元并将其用于H.264/AVC HiProfile视频编码器的自适应变换模块中。通过变换类型信号的配置,该变换单元可以完成相应的变换操作。本设计采用Altera公司的CycloneⅡ系列FPGA进行实现和验证,布局布线后的最大工作频率为63 MHz,采用4个可配置变换单元的变换模块,可以满足HD1080P@50帧/s视频的实时编码要求。     

A real-time H.264/AVC VLSI encoder architecture

Evolving applications related to video technologies require video encoder and decoder implemented with low cost and achieving real-time performance. In order to meet this demand and targeting especially the applications imposing low VLSI area requirements, the present paper describes a VLSI H.264/AVC encoder architecture performing at real-time. The encoder uses a pipeline architecture and all the modules have been optimized with respect to the VLSI cost. The encoder design complies with the reference software encoder of the standard, follows the baseline profile level 3.0 and it constitutes an IP-core and/or an efficient stand-alone solution. The architecture operates at a maximum frequency of 100 MHz and achieves maximum throughput of 30 frames/s with frame size 1,024 × 768. Results and performance measurements of the entire encoder have been validated on FPGA and VLSI 0.18 μm occupying a total area of 3.9 mm².     

基于H.264码率控制算法的改进

码率控制作为H.264中的重要的技术之一,在平稳码率和保证良好的接收端质量方面起着重要的作用。针对Joint Model (JM)采用的算法存在的对不同的初始量化参数码率不平稳和PSNR(峰值信噪比)差异过大等问题进行分析,在原有算法基础上作出一定的改进。实验结果表明,改进的算法能很好的保证码率和PSNR的平稳性。