一种高效CAVLC编码结构的VLSI设计实现

CAVLC是H.264/AVC标准新引入的一项重要特性。通过对已有游程编码结构的分析和改进,提出了一种可满足H.264/AVC实时编码应用的高效CAVLC编码结构。该结构采用优化的数据处理顺序,提高了系统的吞吐率。同时利用算术结构设计代替查找表所需的ROM,降低了设计的硬件成本。在133 MHz频率约束下采用0.18 um工艺的综合结果表明,所需的逻辑门数为13 114,以较少的逻辑资源实现了HD1080@30fps的实时处理.     

实时高清H.264编码中CAVLC的流式实现

CAVLC是H.264中熵编码的一种重要实现方式,具有可挖掘的数据级并行特征,但同时具有较强的串行特点。本文分析了CAVLC的程序特征,提出了CAVLC的流式实现方法,并在流处理器STORM-1上进行了实现。实验结果表明本方法能够满足实时高清H.264编码的性能需求。     

H.264标准中的CAVLC编码算法与FPGA实现

H.264视频编码标准在基本档次和扩展档次采用CAVLC（基于上下文的自适应可变长编码）熵编码方法,但标准并未给出详细的CALVC编码句法。从CALVC的解码原理出发,详细分析了H.264视频编码标准中的CAVLC编码算法,提出了一种应用于H.264标准的快速低功耗CAVLC编码器结构,给出了各个功能模块的详细设计原理与FPGA实现方法,并对较复杂的几个模块进行了算法和结构上的优化,降低了实现的复杂度。FPGA实验验证表明,该方案编码系统时钟可达100 MHz,能满足对高速、实时应用的编码要求。     

Thermodynamic modeling of the Mg–Nd–Sr ternary system with key experimental investigation

The phase equilibria in the Mg-rich region of the Mg–Nd–Sr ternary system at 300 and 350 °C were established using equilibrated-sample method. Powder X-ray diffraction (XRD) technique and scanning electron microscopy (SEM) equipped with energy-dispersive spectroscopy (EDS) were used for phase composition determination. Four three-phase equilibria and four two-phase equilibria have been experimentally determined at both isothermal sections of 300 and 350 °C. The phase equilibria relationships in the Mg-rich side were studied. The major invariant reaction temperatures of vertical sections with 80 at. % Mg and 10 at. % Sr were determined with differential scanning calorimetry (DSC) test. Moreover, thermodynamic modeling of Mg–Nd–Sr ternary system has been carried out by CALPHAD method based on the present key experimental results. The liquid solution was described using the modified quasi-chemical model in the pair approximation (MQMPA). The compound energy formalism (CEF) was used for the solid phases. The present obtained thermodynamic database of Mg–Nd–Sr ternary system will provide an important support for the Mg-based biodegradable implant development.     

A hardware architecture for real-time image compression using a searchless fractal image coding method

In this paper we present a novel hardware architecture for real-time image compression implementing a fast, searchless iterated function system (SIFS) fractal coding method. In the proposed method and corresponding hardware architecture, domain blocks are fixed to a spatially neighboring area of range blocks in a manner similar to that given by Furao and Hasegawa. A quadtree structure, covering from 32 × 32 blocks down to 2 × 2 blocks, and even to single pixels, is used for partitioning. Coding of 2 × 2 blocks and single pixels is unique among current fractal coders. The hardware architecture contains units for domain construction, zig-zag transforms, range and domain mean computation, and a parallel domain-range match capable of concurrently generating a fractal code for all quadtree levels. With this efficient, parallel hardware architecture, the fractal encoding speed is improved dramatically. Additionally, attained compression performance remains comparable to traditional search-based and other searchless methods. Experimental results, with the proposed hardware architecture implemented on an Altera APEX20K FPGA, show that the fractal encoder can encode a 512 × 512 × 8 image in approximately 8.36 ms operating at 32.05 MHz. Therefore, this architecture is seen as a feasible solution to real-time fractal image compression.

基于H.264的熵编码结构

Exp-Golomb和CAVLC是H.264引入的新的熵编码形式,通过引入上下文的方式,减少编码码流,提高鲁棒性。该文提出一种熵编码的硬件结构,采用全0子块探测,双RAM结构,流水线技术,以及通过计算代替查找表的方法,加快编码过程,同时减少硬件的复杂度。FPGA综合结果显示,关键路径为11.449 ns,系统时钟最高支持到87.346 MHz。     

A Highly Efficient VLSI Architecture for H.264/AVC CAVLC Decoder

In this paper, an efficient algorithm is proposed to improve the decoding efficiency of the context-based adaptive variable length coding (CAVLC) procedure. Due to the data dependency among symbols in the decoding flow, the CAVLC decoder requires large computation time, which dominates the overall decoder system performance. To expedite its decoding speed, the critical path in the CAVLC decoder is first analyzed and then reduced by forwarding the adaptive detection for succeeding symbols. With a shortened critical path, the CAVLC architecture is further divided into two segments, which can be easily implemented by a pipeline structure. Consequently, the overall performance is effectively improved. In the hardware implementation, a low power combined LUT and single output buffer have been adopted to reduce the area as well as power consumption without affecting the decoding performance. Experimental results show that the proposed architecture surpassing other recent designs can approximately reduce power consumption by 40% and achieve three times decoding speed in comparison to the original decoding procedure suggested in the H.264 standard. The maximum frequency can be larger than 210 MHz, which can easily support the real-time requirement for resolutions higher than the HD1080 format.     

Ddelta: A deduplication-inspired fast delta compression approach

Delta compression is an efficient data reduction approach to removing redundancy among similar data chunks and files in storage systems. One of the main challenges facing delta compression is its low encoding speed, a worsening problem in face of the steadily increasing storage and network bandwidth and speed. In this paper, we present Ddelta, a deduplication-inspired fast delta compression scheme that effectively leverages the simplicity and efficiency of data deduplication techniques to improve delta encoding/decoding performance. The basic idea behind Ddelta is to (1) accelerate the delta encoding and decoding processes by a novel approach of combining Gear-based chunking and Spooky-based fingerprinting for fast identification of duplicate strings for delta calculation, and (2) exploit content locality of redundant data to detect more duplicates by greedily scanning the areas immediately adjacent to already detected duplicate chunks/strings. Our experimental evaluation of a Ddelta prototype based on real-world datasets shows that Ddelta achieves an encoding speedup of 2.5×–8× and a decoding speedup of 2×–20× over the classic delta-compression approaches Xdelta and Zdelta while achieving a comparable level of compression ratio.     

H.264/AVC中CAVLC编码器的硬件设计与实现

设计了一种H.264标准的CAVLC编码器,对原有软件流程进行部分改进,提出了并行处理各编码子模块的算法结构。重点对非零系数级(level)编码模块进行优化,采用并行处理和流水线相结合的结构,减少了cavlc编码的时钟周期,提供了稳定吞吐量。采用Xilinx公司VirtexⅡ系列的xc2v250 FPGA进行实现验证,最高时钟频率可达158.1 MHz,可满足实时编码H.264高清视频要求。     

Phase equilibria and microstructure development in Mg-rich Mg-Gd-Sr alloys: Experiments and CALPHAD assessment

Mg-Sr alloys are promising to fabricate orthopedic implants. The alloying of rare earth elements such as Gd may improve the comprehensive mechanical properties of Mg-Sr alloys. The information on the phase diagram and the microstructure development are required to design chemical composition and microstructure of Gd alloyed Mg-Sr alloys. The phase equilibria and the microstructure development in Mg-rich Mg-Gd-Sr alloys (Gd, Sr < 30 at. %) are experimentally investigated via phase identification, chemical analysis, and microstructure observation with respect to the annealed ternary alloys. The onset temperatures of liquid formation are measured by differential scanning calorimetry. A thermodynamic database of the Mg-rich Mg–Gd–Sr ternary system is developed for the first time via CALPHAD (CALculation of PHAse Diagram) approach assisted by First-Principles calculations. The thermodynamic calculations with the developed database enable a well reproduction of the experimental findings and the physical-metallurgical understanding of the microstructure formation in solidification and annealing.     

Experimental investigation and thermodynamic assessment of the Zn–Cu–Sr ternary system

Zn–Cu–Sr alloys play a crucial role in the development of biodegradable implant materials based on zinc. The current study aimed to investigate the phase equilibria of the Zn–Cu–Sr ternary system in the Cu–Zn-rich region, through experimental analysis. For this purpose, fifteen and fourteen samples were respectively prepared and equilibrated at 350 and 400 °C, to determine the isothermal sections. The equilibrated alloys were then subjected to various analytical techniques such as scanning electron microscopy (SEM) equipped with energy dispersive spectrometry analysis (EDS), electron probe microanalysis (EPMA), and powder X-ray diffraction analysis (XRD). The analysis revealed the presence of five three-phase equilibria and ten two-phase equilibria in the two isothermal sections. Differential scanning calorimetry (DSC) was used to investigate the phase transformation temperature with constant values of 8 at. % Sr and 30 at. % Cu. The obtained experimental results were used to perform a thermodynamic assessment of the Zn–Cu–Sr system especial in Zn-rich region using the calculation of phase diagrams (CALPHAD) method. The modified quasi-chemical model (MQM) was used to model the liquid solution, while the compound energy formalism (CEF) was used to represent Gibbs free energies of the solid phases. The present obtained thermodynamic parameters were found to accurately reproduce the experimentally measured phase relationships in the Zn–Cu–Sr ternary system.     

Polymeric (SU-8) optical microscanner driven by electrostatic actuation

A torsional micromechanical scanner was fabricated using photosensitive polymer (SU-8). The proposed polymer-based optical microscanner with reduced torsional stiffness offers a new approach to increase scanning angles. The scanner consists of two parts; the top layer (micro mirror and electrodes) and the bottom layer (anchors and electrodes). The SU-8 scanner is actuated by electrostatic force generated by gap-closing electrodes. For the fabricated optical scanner with the mirror size of 3 × 3 mm², the experimentally obtained scanning angles were 0.43° for 60 Hz (non-resonant) and 1.54° for 1.13 kHz (resonant) at the input voltage of 160 V. This paper also proposes a simple and new fabrication method, which can effectively control the stiffness of the torsional springs by molding SU-8 photoresist through V-groove on the silicon substrate, thereby increasing the scanning angles.     

The secure wavelet transform

There has been an increasing concern for the security of multimedia transactions over real-time embedded systems. Partial and selective encryption schemes have been proposed in the research literature, but these schemes significantly increase the computation cost leading to tradeoffs in system latency, throughput, hardware requirements and power usage. In this paper, we propose a light-weight multimedia encryption strategy based on a modified discrete wavelet transform (DWT) which we refer to as the secure wavelet transform (SWT). The SWT provides joint multimedia encryption and compression by two modifications over the traditional DWT implementations: (a) parameterized construction of the DWT and (b) subband re-orientation for the wavelet decomposition. The SWT has rational coefficients which allow us to build a high throughput hardware implementation on fixed point arithmetic. We obtain a zero-overhead implementation on custom hardware. Furthermore, a Look-up table based reconfigurable implementation allows us to allocate the encryption key to the hardware at run-time. Direct implementation on Xilinx Virtex FPGA gave a clock frequency of 60 MHz while a reconfigurable multiplier based design gave a improved clock frequency of 114 MHz. The pipelined implementation of the SWT achieved a clock frequency of 240 MHz on a Xilinx Virtex-4 FPGA and met the timing constraint of 500 MHz on a standard cell realization using 45 nm CMOS technology.     

Adsorption of glucose oxidase at platinum-multiwalled carbon nanotube-alumina-coated silica nanocomposite for amperometric glucose biosensor

Glucose oxidase (GOx) has been immobilized in platinum-multiwalled carbon nanotube-alumina-coated silica (Pt-MWCNT-ACS) nanocomposite modified glassy carbon electrode by adsorption to provide a novel amperometric glucose biosensor. The morphology, nature, and performance of the resulting GOx-Pt-MWCNT-ACS nanobiocomposite modified glassy carbon electrode were characterized by field emission scanning electron microscopy, energy dispersive X-ray spectroscopy, cyclic voltammetry, and amperometry. The influence of various experimental conditions was examined for the determination of the optimum analytical performance. The optimized glucose biosensor displayed a wide linear range of up to 10.5 mM, a high sensitivity of 113.13 mA M⁻¹ cm⁻², and a response time of less than 5 s. The sensitivity for the determination of glucose at the GOx-Pt-MWCNT-ACS nanobiocomposite modified glassy carbon electrode is better than at common GOx-Pt-CNT nanobiocomposite modified electrodes. The proposed biosensor has good anti-interferent ability and long-term storage stability after coating with Nafion, and it can be used for the determination of glucose in synthetic serum.     

Fuzzy modeling of fluidized catalytic cracking unit

The paper deals with the fuzzy system identification of reactor–regenerator–stripper–fractionator's (RRSF) section of a fluidized catalytic cracking unit (FCCU). The fuzzy system identification based on the data collected from an operating refinery of FCCU of capacity, 1.2 MMPTA, with a sample time of 10 min. A generalized fuzzy model (GFM) and identification of structure and model parameter for multi-input/single output is presented. The GFM has the capability of representing both the CRI model and TS model under certain conditions. The structure identification and the parameter estimation are carried out using hybrid learning approach comprising modified mountain clustering and gradient descent learning with least square estimation (LSE) for the identification of a fuzzy model. The modified mountain clustering considers every data point as a potential cluster center in x × y hyperspace. The optimum number of clusters, which leads to an optimum number of rules, is determined with the help of validity function that guides the search. The obtained result from the modified mountain clustering initializes the GFM. Further hybrid of the gradient descent technique and LSE is aimed at learning of the GFM parameters in two phases. In the first phase of an epoch of learning gradient descent tunes the premise parameter and index of fuzziness of each rule. In second phase, LSE utilizes the results of first phase for evaluating the coefficient of local linear model of corresponding rules.     

Experimental study and thermodynamic modelling of the B-Fe-Mn ternary system

This work is focused on an experimental study of phase equilibria in the B-Fe-Mn ternary system combined with a CALPHAD theoretical analysis with the aim of creating a reliable theoretical thermodynamic dataset for calculation of the phase diagram of the ternary system. Boron is modelled as an interstitial element in all solid solutions of Fe and Mn. In the experimental study, B-Mn-Fe alloys were prepared and heat-treated at 873 K for 90 days/2160 h and at 1223 K for 60 days/1440 h. Following heat treatment, the phase equilibria and composition of the coexisting phases were determined using scanning electron microscopy and X-ray diffraction analysis. The experimental results obtained, together with experimental results collected from the literature, were used in the optimization of the thermodynamic parameters by using the CALPHAD method. The result of this work is an optimized thermodynamic dataset for the B-Fe-Mn ternary system allowing the phase diagram and thermodynamic properties to be calculated.     

Multimodal registration of visible,SWIR and LWIR images in a distributed smart camera system

We present a multimodal registration algorithm between images in the visible, short-wave infrared and long-wave infrared spectra. The algorithm works with two reference-objective image pairs and operates in two stages: (1) A calibration phase between static frames to estimate the transformation parameters using histogram of oriented gradients and the Chi-square distance; (2) a frame-by-frame mapping with these parameters using a projective transformation and a bilinear interpolation to map the objective video stream to the coordinate system of the reference video stream. We present a distributed heterogeneous architecture that combines a programmable processor core and a custom hardware accelerator for each node. The software performs the calibration phase, whereas the hardware computes the frame-by-frame mapping. We implemented our design using a Xilinx Zynq XC7Z020 system-on-a-chip for each node. The prototype uses 2.38W of power, 25% of the logic resources and 65% of the available on-chip memory per node. Running at 100MHz, the core can register 640  ×  512-pixel frames in 4ms after initial calibration, which allows our module to operate at up to 250 frames per second.     

A 5 GHz LC-VCO frequency synthesizer for unlicensed band of WiMAX

This paper presents a low power and low phase noise CMOS integer-N frequency synthesizer based on the charge-pump Phase Locked Loop (PLL) topology. The frequency synthesizer can be used for IEEE 802.16 unlicensed band of WiMAX (World Interoperability for Microwave Access). The operation frequency of the proposed design is ranged from 5.13 to 5.22 GHz. The proposed Voltage-Controlled Oscillator (VCO) achieves low power consumption and low phase noise. The high speed divider is implemented by an optimal extended true single phase clock (E-TSPC) prescaler. It can achieve higher operating frequency and lower power consumption. A new frequency divider is also proposed to eliminate the hardware overhead of the S counter in the conventional programmable divider. The proposed frequency synthesizer consists of a phase-frequency detector (PFD), a charge pump, a low-pass loop filter, a VCO, and a frequency divider. The simulated phase noise of the proposed VCO is −121.6 dBc/Hz at 1 MHz offset from the carrier frequency. The proposed frequency synthesizer consumes 13.1 mW. The chip with an area of 1.048 × 1.076 mm² is fabricated in a TSMC 0.18 μm CMOS 1P6M technology process.     

Architectural implementation of modified K-best algorithm for detection in MIMO systems

We present novel architectures for the modified K-best algorithm and its very-large-scale integration implementation for spatially multiplexed wireless multiple-input multiple-output systems. The objective was to propose a simplified architecture based on the algorithm and to significantly improve the suitability for hardware implementation. Two different architecture designs were proposed: a distributed arithmetic- based tree-search detector and a breadth-first search sphere detector. The implementations were performed to obtain a configurable architectural solution for different antenna configurations and constellations. The synthesis analysis shows that the proposed architectures achieve a throughput of > 500 Mbps with reduced hardware complexity compared to previously reported architectures.     

An architecture of a high-speed digital hologram generator based on FPGA

In this paper, a hardware architecture to generate a computer-generated hologram (CGH) in a real-time is proposed and implemented in FPGAs. The algorithm that generates digital hologram is reinterpreted and rearranged for higher operation speed. In order to optimize the hardware architecture and performance, the precision is analyzed using fixed-point simulation. The bit-width inside the hardware is obtained by numerical and visual precision analysis. The structure of the basic calculational unit (CGH Cell), an arrangement of these cells (CGH Kernel) to calculate a row of a hologram, and a processor (CGH Processor) with the kernels to perform the modified CGH algorithm are proposed.The proposed processor was implemented with Xilinx XC2VP70 FPGAs. A 1408 × 1050 sized hologram for a 3D object consisting of 10,000 light sources can be generated in 0.0093 [s] at the operating frequency of 285 MHz. Our architecture showed 37.32% and 87.32% higher speed than the best previous work when 1408 cells and 5632 cells are used, respectively.