餐厅无线呼叫服务系统设计

对当前餐厅管理系统进行分析,设计了一种快速及时的无线呼叫系统。该系统除了解决服务及时问题外,还使得餐厅服务总台对每张餐桌的使用情况了如指掌,进而为餐桌的科学管理提供了可靠依据。     

高性能二维9/7离散小波变换VLSI结构

为了降低二维小波变换中的存储消耗并同时提高电路处理速度,提出了一种二维并行的VLSI结构。通过充分挖掘二维变换中行变换和列变换之间的关系,优化了行变换核和列变换核的并行数据扫描输入方式,将9/7小波变换的中间存储降低至4N。同时,采用基于翻转格式的流水线技术,将电路的关键路径缩短至一级乘法器延时,有效地提高了电路处理速度,并通过伸缩电路合并的优化方法将乘法器个数降低至10个,从而有效地减少了硬件资源消耗。     

Development of Industry 4.0 predictive maintenance architecture for broadcasting chain

Industry 4.0 Predictive Maintenance (PdM 4.0) architecture in the broadcasting chain is one of the taxonomy challenges for deploying Industry 4.0 frameworks. This paper proposes a novel PdM framework based on advanced Reference Architecture Model Industry 4.0 (RAMI 4.0) to reduce operation and maintenance costs. This framework includes real-time production monitoring, business processes, and integration based on Design Science Research (DSR) to generate an innovative Business Process Model and Notation (BPMN) meta-model. The addressed model visualizes sub-processes based on experts' and stakeholders' knowledge to reduce the cost of maintenance of audiovisual services including satellite TV, cable TV, and live audio and video broadcast services. Based on the recommendation and the concept of Industry 4.0, the proposed framework tolerates the predictable failures and further concerns in similar related industries. Some empirical experiments have been conducted by using the Islamic Republic of Iran Broadcasting’s (IRIB) high-power station (located near the capital city of Iran, Tehran) to evaluate the functionality and efficiency of the proposed predictive maintenance framework. Practical outcomes demonstrate that interval times between data collection should be increased in audio and video broadcasting predictive maintenance because of the limitation of the internal processing performance of equipment. The framework also indicates the role of the Frequency Modulation (FM) transmitters’ data clearance to reduce the instability and untrustworthy data during data mining. The proposed DSR method endorses using a customized RAMI 4.0 meta-model framework to adapt distributed broadcasting and communication with PdM 4.0, which increases the stability as well as decreasing maintenance costs of the broadcasting chain in comparison to state-of-the-art methodologies. Furthermore, it is shown that the proposed framework outperforms the best-evaluated methods in terms of acceptance.     

A real-time architecture for time-aware agents

This paper describes the specification and implementation of a new three-layer time-aware agent architecture. This architecture is designed for applications and environments where societies of humans and agents play equally active roles, but interact and operate in completely different time frames. The architecture consists of three layers: the April real-time run-time (ART) layer, the time aware layer (TAL), and the application agents layer (AAL). The ART layer forms the underlying real-time agent platform. An original online, real-time, dynamic priority-based scheduling algorithm is described for scheduling the computation time of agent processes, and it is shown that the algorithm's O(n) complexity and scalable performance are sufficient for application in real-time domains. The TAL layer forms an abstraction layer through which human and agent interactions are temporally unified, that is, handled in a common way irrespective of their temporal representation and scale. A novel O(n2) interaction scheduling algorithm is described for predicting and guaranteeing interactions' initiation and completion times. The time-aware predicting component of a workflow management system is also presented as an instance of the AAL layer. The described time-aware architecture addresses two key challenges in enabling agents to be effectively configured and applied in environments where humans and agents play equally active roles. It provides flexibility and adaptability in its real-time mechanisms while placing them under direct agent control, and it temporally unifies human and agent interactions.     

High performance hardware architecture for singular spectrum analysis of Hankel tensors

This paper presents a hardware architecture for singular spectrum analysis of Hankel tensors, including computation of tucker decomposition, tensor reconstruction and final Hankelization. In the proposed design, we explore two level of optimization. First, in algorithm level, we optimize the calculation process by exploiting the Hankel property to reduce the computation complexity and on-chip BRAM resource usage. Secondly, in hardware level, parallelism is explored for acceleration. Resource sharing is applied to reduce look-up tables (LUTs) usage. To enable flexibility, the number of processing elements (PEs) can be changed through parameter setting. Our proposed design is implemented on Field-Programmable Gate Arrays (FPGAs) to process third order tensors. Experiment results show that our design achieve a speed-up from 172 to 1004 compared with CPU implementation via Intel MKL and 5 to 40 compared with GPU implementation.     

An architecture for Java-based real-time distributed visualization

In this paper, we present a Java-based software architecture for real-time visualization that utilizes a cluster of conventional PCs to generate high-quality interactive graphics. Normally, a large multiprocessor computer would be needed for interactive visualization tasks requiring more processing power than a single PC can provide. By using clusters of PCs, enormous cost savings can be realized, and proprietary "high-end" hardware is no longer necessary for these tasks. Our architecture minimizes the amount of synchronization needed between PCs, resulting in excellent scalability. It provides a modular framework that can accommodate a wide variety of rendering algorithms and data formats, provided that the rendering algorithms can generate pixels individually and the data is duplicated on each PC. Demonstration modules that implement ray tracing, fractal rendering, and volume rendering algorithms were developed to evaluate the architecture. Results are encouraging-using 15 PCs connected to a standard 100 Megabit/s Ethernet network, the system can interactively render simple to moderately complex data sets at modest resolution. Excellent scalability is achieved; however, our tests were limited to a cluster of 15 PCs. Results also demonstrate that Java is a viable platform for real-time distributed visualization.     

A VLSI architecture for real-time edge linking

A real-time algorithm and its VLSI implementation for edge linking is presented. The linking process is based on the break points' directions and the weak level points. The proposed VLSI architecture is capable of outputting one pixel of the linked edge map per clock cycle with a latency of 11n+12 clock cycles, where n is the number of pixel columns in the image     

Agent-based reconfigurable architecture for real-time object tracking

Most conventional object tracking algorithms are implemented on general-purpose processors in software due to its great flexibility. However, the real-time performance is hard to achieve due to the inherent characteristics of the sequential processing of these processors. To tackle this issue, a reconfigurable system-on-chip (rSoC) platform with microprocessors and FPGAs is applied in this paper. To simplify the hardware/software interface, a Belief–Desire–Intention (BDI)-based multi-agent architecture is proposed as the unified framework. Then an agent-based task graph and two heuristic partitioning methods are proposed to partition the hardware and software on an rSoC platform. Compared to the module-based architecture, this BDI-based multi-agent architecture provides more efficiency, flexibility, autonomy, and scalability for the real-time tracking systems. A particle swarm optimization (PSO)-based object detection and tracking algorithm is applied to evaluate the proposed architecture. Extensive experimental results of object tracking demonstrate that the proposed architecture is efficient and highly robust with real-time performance.     

Efficient verification of distributed real-time systems with broadcasting behaviors

Binary synchronization has been used extensively in the construction of mathematical models for the verification of embedded systems. Although it allows for the modeling of complex cooperation among many processes in a natural environment, not many tools have been developed to support the modeling capability in this regard. In this article, we first give examples to argue that special algorithms are needed for the efficient verification of systems with complex synchronizations. We then define our models of distributed real-time systems with synchronized cooperation among many processes. We present algorithms for the construction of BDD-like diagrams for the characterization of complex synchronizations among many processes. We present weakest precondition algorithms that take advantage of the just-mentioned BDD-like diagrams for the efficient verification of complex real-time systems. Finally, we report experiments and argue that the techniques could be useful in practice.     

Bio-inspired heterogeneous architecture for real-time pedestrian detection applications

Along with the development of powerful processing platforms, heterogeneous architectures are nowadays permitting new design space explorations. In this paper, we propose a novel heterogeneous architecture for reliable pedestrian detection applications. It deploys an efficient Histogram of Oriented Gradient pipeline tightly coupled with a neuro-inspired spatio-temporal filter. By relying on hardware–software co-design principles, our architecture is capable of processing video sequences from real-word dynamic environments in real time. The paper presents the implemented algorithm and details the proposed architecture for executing it, exposing in particular the partitioning decisions made to meet the required performance. A prototype implementation is described and the results obtained are discussed with respect to other state-of-the-art solutions.     

General-purpose vision chip architecture for real-time machine vision

To solve the I/O bottleneck problem in existing vision systems and to realize versatile processing adaptive to various and changing environments, we propose a new vision chip architecture for applications such as robot vision. The chip has general-purpose processing elements (PEs) with each PE being directly connected to a photo detector (PD) and can implement various visual processing algorithms. We developed and simulated some sample programs for the chip and proved that they can be processed within 1 ms/frame, a rate that is high enough for high-speed visual feedback for robot control. Aiming to complete the chip, we are now developing test chips based on the architecture. The latest design has 8 x 8 PEs and PDs in an area 3.3 mm x 3.0 mm using a 0.8 μm CMOS process.     

Quality-driven model-based architecture synthesis for real-time embedded SoCs

The recent spectacular progress in modern microelectronics created a big stimulus towards development of embedded systems. Unfortunately, it also introduced unusual complexity which results in many serious issues that cannot be resolved without new more adequate development methods and electronic design automation tools for the system-level design. This paper discusses the problem of an efficient model-based multi-objective optimal architecture synthesis for complex hard real-time embedded systems, when using as an example a system-level architecture exploration and synthesis method that we developed.     

An architecture for real-time distributed artificial intelligent systems

This paper introduces a new architecture for a real-time distributed artificial intelligence system: DENIS—a Dynamic Embedded Noticeboard Information System. The fundamental idea underlying the architecture draws heavily upon a distributed human system analogy, as seen, for example, in the workplace. The aim of DENIS is to provide a simple, meaningful means by which autonomous intelligent agents can cooperate and coordinate their actions in order to enhance the reliability and effectiveness of a real-time distributed control system. Based on a human paradigm, the architecture inherently allows for the control of an intelligent agent to be taken over by a human operator, yet still to maintain consistency in the distributed system. The key to the thinking in this new approach is to try to model how humans work together, and to implement this in a distributed architecture. One of the main issues raised is that humans owe much of their flexibility to their ability to reason, not only logically, but also in terms of time.     

Robot-vision architecture for real-time 6-DOF object localization

This paper presents a new robot-vision system architecture for real-time moving object localization. The 6-DOF (3 translation and 3 rotation) motion of the objects is detected and tracked accurately in clutter using a model-based approach without information of the objects’ initial positions. An object identification task and an object tracking task are combined under this architecture. The computational time-lag between the two tasks is absorbed by a large amount of frame memory. The tasks are implemented as independent software modules using stereo-vision-based methods which can deal with objects of various shapes with edges, including planar to smooth-curved objects, in cluttered environments. This architecture also leads to failure-recoverable object tracking, because the tracking processes can be automatically recovered, even if the moving objects are lost while tracking. Experimental results obtained with prototype systems demonstrate the effectiveness of the proposed architecture.     

A composable real-time architecture for replicated railway applications

Triple-modular-redundant applications are widely used for fault-tolerant safety–critical computation. They have strict timing requirements for correct operation. We present an architecture which provides composability and mixed-criticality to support integration and to ease certification of such safety–critical applications. In this architecture, an additional layer is required for the sharing/partitioning of resources. This potentially jeopardizes the synchronization necessary for the triple-modular-redundant applications.We investigate the effects of different (unsynchronized) scheduling methods for the resource-sharing layer in this architecture and conclude that an out-of-the-box solution, which guarantees the technical separation between applications with fast reaction time requirements is only feasible when executing at most one instance of a triple-modular-redundant application per CPU-core for single and multi-core CPUs. Only when accepting changes in the applications or the applications’ synchronization mechanisms, are more flexible solutions with good performance and resource utilization available.     

High performance dynamic voltage/frequency scaling algorithm for real-time dynamic load management

Modern cyber-physical systems assume a complex and dynamic interaction between the real world and the computing system in real-time. In this context, changes in the physical environment trigger changes in the computational load to execute. On the other hand, task migration services offered by networked control systems require also management of dynamic real-time computing load in nodes. In such systems it would be difficult, if not impossible, to analyse off-line all the possible combinations of processor loads. For this reason, it is worthwhile attempting to define new flexible architectures that enable computing systems to adapt to potential changes in the environment.We assume a system composed by three main components: the first one is responsible of the management of the requests arisen when new tasks require to be executed. This management component asks to the second component about the resources available to accept the new tasks. The second component performs a feasibility analysis to determine if the new tasks can be accepted coping with its real-time constraints. A new processor speed is also computed. A third component monitors the execution of tasks applying a fixed priority scheduling policy and additionally controlling the frequency of the processor.This paper focus on the second component providing a “correct” (a task never is accepted if it is not schedulable) and “near-exact” (a task is rarely rejected if it is schedulable) algorithm that can be applicable in practice because its low/medium and predictable computational cost. The algorithm analyses task admission in terms of processor frequency scaling. The paper presents the details of a novel algorithm to analyse tasks admission and processor frequency assignment. Additionally, we perform several simulations to evaluate the comparative performance of the proposed approach. This evaluation is made in terms of energy consumption, task rejection ratios, and real computing costs. The results of simulations show that from the cost, execution predictability, and task acceptance points of view, the proposed algorithm mostly outperforms other constant voltage scaling algorithms.     

GUARDS: a generic upgradable architecture for real-time dependablesystems

The development and validation of fault-tolerant computers for critical real-time applications are currently both costly and time consuming. Often, the underlying technology is out-of-date by the time the computers are ready for deployment. Obsolescence can become a chronic problem when the systems in which they are embedded have lifetimes of several decades. This paper gives an overview of the work carried out in a project that is tackling the issues of cost and rapid obsolescence by defining a generic fault-tolerant computer architecture based essentially on commercial off-the-shelf (COTS) components (both processor hardware boards and real-time operating systems). The architecture uses a limited number of specific, but generic, hardware and software components to implement an architecture that can be configured along three dimensions: redundant channels, redundant lanes, and integrity levels. The two dimensions of physical redundancy allow the definition of a wide variety of instances with different fault tolerance strategies. The integrity level dimension allows application components of different levels of criticality to coexist in the same instance. The paper describes the main concepts of the architecture, the supporting environments for development and validation, and the prototypes currently being implemented